| blob | 50c0c8b11e7517283ea7560199abebb8a3d5ebeb |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
6 ; CHECK-LABEL: and8xi8:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
9 ; CHECK-NEXT: ret
10 %tmp1 = and <8 x i8> %a, %b;
11 ret <8 x i8> %tmp1
12 }
14 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
15 ; CHECK-LABEL: and16xi8:
16 ; CHECK: // %bb.0:
17 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
18 ; CHECK-NEXT: ret
19 %tmp1 = and <16 x i8> %a, %b;
20 ret <16 x i8> %tmp1
21 }
24 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
25 ; CHECK-LABEL: orr8xi8:
26 ; CHECK: // %bb.0:
27 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
28 ; CHECK-NEXT: ret
29 %tmp1 = or <8 x i8> %a, %b;
30 ret <8 x i8> %tmp1
31 }
33 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
34 ; CHECK-LABEL: orr16xi8:
35 ; CHECK: // %bb.0:
36 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
37 ; CHECK-NEXT: ret
38 %tmp1 = or <16 x i8> %a, %b;
39 ret <16 x i8> %tmp1
40 }
43 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
44 ; CHECK-LABEL: xor8xi8:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
47 ; CHECK-NEXT: ret
48 %tmp1 = xor <8 x i8> %a, %b;
49 ret <8 x i8> %tmp1
50 }
52 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
53 ; CHECK-LABEL: xor16xi8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
56 ; CHECK-NEXT: ret
57 %tmp1 = xor <16 x i8> %a, %b;
58 ret <16 x i8> %tmp1
59 }
61 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
62 ; CHECK-SD-LABEL: bsl8xi8_const:
63 ; CHECK-SD: // %bb.0:
64 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
65 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
66 ; CHECK-SD-NEXT: ret
67 ;
68 ; CHECK-GI-LABEL: bsl8xi8_const:
69 ; CHECK-GI: // %bb.0:
70 ; CHECK-GI-NEXT: adrp x8, .LCPI6_0
71 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI6_0]
72 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
73 ; CHECK-GI-NEXT: ret
74 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
75 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
76 %tmp3 = or <8 x i8> %tmp1, %tmp2
77 ret <8 x i8> %tmp3
78 }
80 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
81 ; CHECK-SD-LABEL: bsl16xi8_const:
82 ; CHECK-SD: // %bb.0:
83 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
84 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
85 ; CHECK-SD-NEXT: ret
86 ;
87 ; CHECK-GI-LABEL: bsl16xi8_const:
88 ; CHECK-GI: // %bb.0:
89 ; CHECK-GI-NEXT: adrp x8, .LCPI7_0
90 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
91 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
92 ; CHECK-GI-NEXT: ret
93 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
94 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
95 %tmp3 = or <16 x i8> %tmp1, %tmp2
96 ret <16 x i8> %tmp3
97 }
99 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
100 ; CHECK-LABEL: orn8xi8:
101 ; CHECK: // %bb.0:
102 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
103 ; CHECK-NEXT: ret
104 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
105 %tmp2 = or <8 x i8> %a, %tmp1
106 ret <8 x i8> %tmp2
107 }
109 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
110 ; CHECK-LABEL: orn16xi8:
111 ; CHECK: // %bb.0:
112 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
113 ; CHECK-NEXT: ret
114 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
115 %tmp2 = or <16 x i8> %a, %tmp1
116 ret <16 x i8> %tmp2
117 }
119 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
120 ; CHECK-LABEL: bic8xi8:
121 ; CHECK: // %bb.0:
122 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
123 ; CHECK-NEXT: ret
124 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
125 %tmp2 = and <8 x i8> %a, %tmp1
126 ret <8 x i8> %tmp2
127 }
129 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
130 ; CHECK-LABEL: bic16xi8:
131 ; CHECK: // %bb.0:
132 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
133 ; CHECK-NEXT: ret
134 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
135 %tmp2 = and <16 x i8> %a, %tmp1
136 ret <16 x i8> %tmp2
137 }
139 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
140 ; CHECK-SD-LABEL: orrimm2s_lsl0:
141 ; CHECK-SD: // %bb.0:
142 ; CHECK-SD-NEXT: orr v0.2s, #255
143 ; CHECK-SD-NEXT: ret
144 ;
145 ; CHECK-GI-LABEL: orrimm2s_lsl0:
146 ; CHECK-GI: // %bb.0:
147 ; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff
148 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
149 ; CHECK-GI-NEXT: ret
150 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
151 ret <2 x i32> %tmp1
152 }
154 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
155 ; CHECK-SD-LABEL: orrimm2s_lsl8:
156 ; CHECK-SD: // %bb.0:
157 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
158 ; CHECK-SD-NEXT: ret
159 ;
160 ; CHECK-GI-LABEL: orrimm2s_lsl8:
161 ; CHECK-GI: // %bb.0:
162 ; CHECK-GI-NEXT: movi d1, #0x00ff000000ff00
163 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
164 ; CHECK-GI-NEXT: ret
165 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
166 ret <2 x i32> %tmp1
167 }
169 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
170 ; CHECK-SD-LABEL: orrimm2s_lsl16:
171 ; CHECK-SD: // %bb.0:
172 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
173 ; CHECK-SD-NEXT: ret
174 ;
175 ; CHECK-GI-LABEL: orrimm2s_lsl16:
176 ; CHECK-GI: // %bb.0:
177 ; CHECK-GI-NEXT: movi d1, #0xff000000ff0000
178 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
179 ; CHECK-GI-NEXT: ret
180 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
181 ret <2 x i32> %tmp1
182 }
184 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
185 ; CHECK-SD-LABEL: orrimm2s_lsl24:
186 ; CHECK-SD: // %bb.0:
187 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
188 ; CHECK-SD-NEXT: ret
189 ;
190 ; CHECK-GI-LABEL: orrimm2s_lsl24:
191 ; CHECK-GI: // %bb.0:
192 ; CHECK-GI-NEXT: movi d1, #0xff000000ff000000
193 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
194 ; CHECK-GI-NEXT: ret
195 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
196 ret <2 x i32> %tmp1
197 }
199 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
200 ; CHECK-SD-LABEL: orrimm4s_lsl0:
201 ; CHECK-SD: // %bb.0:
202 ; CHECK-SD-NEXT: orr v0.4s, #255
203 ; CHECK-SD-NEXT: ret
204 ;
205 ; CHECK-GI-LABEL: orrimm4s_lsl0:
206 ; CHECK-GI: // %bb.0:
207 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
208 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
209 ; CHECK-GI-NEXT: ret
210 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
211 ret <4 x i32> %tmp1
212 }
214 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
215 ; CHECK-SD-LABEL: orrimm4s_lsl8:
216 ; CHECK-SD: // %bb.0:
217 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
218 ; CHECK-SD-NEXT: ret
219 ;
220 ; CHECK-GI-LABEL: orrimm4s_lsl8:
221 ; CHECK-GI: // %bb.0:
222 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
223 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
224 ; CHECK-GI-NEXT: ret
225 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
226 ret <4 x i32> %tmp1
227 }
229 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
230 ; CHECK-SD-LABEL: orrimm4s_lsl16:
231 ; CHECK-SD: // %bb.0:
232 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
233 ; CHECK-SD-NEXT: ret
234 ;
235 ; CHECK-GI-LABEL: orrimm4s_lsl16:
236 ; CHECK-GI: // %bb.0:
237 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
238 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
239 ; CHECK-GI-NEXT: ret
240 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
241 ret <4 x i32> %tmp1
242 }
244 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
245 ; CHECK-SD-LABEL: orrimm4s_lsl24:
246 ; CHECK-SD: // %bb.0:
247 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
248 ; CHECK-SD-NEXT: ret
249 ;
250 ; CHECK-GI-LABEL: orrimm4s_lsl24:
251 ; CHECK-GI: // %bb.0:
252 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
253 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
254 ; CHECK-GI-NEXT: ret
255 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
256 ret <4 x i32> %tmp1
257 }
259 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
260 ; CHECK-SD-LABEL: orrimm4h_lsl0:
261 ; CHECK-SD: // %bb.0:
262 ; CHECK-SD-NEXT: orr v0.4h, #255
263 ; CHECK-SD-NEXT: ret
264 ;
265 ; CHECK-GI-LABEL: orrimm4h_lsl0:
266 ; CHECK-GI: // %bb.0:
267 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
268 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
269 ; CHECK-GI-NEXT: ret
270 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
271 ret <4 x i16> %tmp1
272 }
274 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
275 ; CHECK-SD-LABEL: orrimm4h_lsl8:
276 ; CHECK-SD: // %bb.0:
277 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
278 ; CHECK-SD-NEXT: ret
279 ;
280 ; CHECK-GI-LABEL: orrimm4h_lsl8:
281 ; CHECK-GI: // %bb.0:
282 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
283 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
284 ; CHECK-GI-NEXT: ret
285 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
286 ret <4 x i16> %tmp1
287 }
289 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
290 ; CHECK-SD-LABEL: orrimm8h_lsl0:
291 ; CHECK-SD: // %bb.0:
292 ; CHECK-SD-NEXT: orr v0.8h, #255
293 ; CHECK-SD-NEXT: ret
294 ;
295 ; CHECK-GI-LABEL: orrimm8h_lsl0:
296 ; CHECK-GI: // %bb.0:
297 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
298 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
299 ; CHECK-GI-NEXT: ret
300 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
301 ret <8 x i16> %tmp1
302 }
304 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
305 ; CHECK-SD-LABEL: orrimm8h_lsl8:
306 ; CHECK-SD: // %bb.0:
307 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
308 ; CHECK-SD-NEXT: ret
309 ;
310 ; CHECK-GI-LABEL: orrimm8h_lsl8:
311 ; CHECK-GI: // %bb.0:
312 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
313 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
314 ; CHECK-GI-NEXT: ret
315 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
316 ret <8 x i16> %tmp1
317 }
319 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
320 ; CHECK-SD-LABEL: bicimm2s_lsl0:
321 ; CHECK-SD: // %bb.0:
322 ; CHECK-SD-NEXT: bic v0.2s, #16
323 ; CHECK-SD-NEXT: ret
324 ;
325 ; CHECK-GI-LABEL: bicimm2s_lsl0:
326 ; CHECK-GI: // %bb.0:
327 ; CHECK-GI-NEXT: mvni v1.2s, #16
328 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
329 ; CHECK-GI-NEXT: ret
330 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
331 ret <2 x i32> %tmp1
332 }
334 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
335 ; CHECK-SD-LABEL: bicimm2s_lsl8:
336 ; CHECK-SD: // %bb.0:
337 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #8
338 ; CHECK-SD-NEXT: ret
339 ;
340 ; CHECK-GI-LABEL: bicimm2s_lsl8:
341 ; CHECK-GI: // %bb.0:
342 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #8
343 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
344 ; CHECK-GI-NEXT: ret
345 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
346 ret <2 x i32> %tmp1
347 }
349 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
350 ; CHECK-SD-LABEL: bicimm2s_lsl16:
351 ; CHECK-SD: // %bb.0:
352 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #16
353 ; CHECK-SD-NEXT: ret
354 ;
355 ; CHECK-GI-LABEL: bicimm2s_lsl16:
356 ; CHECK-GI: // %bb.0:
357 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #16
358 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
359 ; CHECK-GI-NEXT: ret
360 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
361 ret <2 x i32> %tmp1
362 }
364 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
365 ; CHECK-SD-LABEL: bicimm2s_lsl124:
366 ; CHECK-SD: // %bb.0:
367 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #24
368 ; CHECK-SD-NEXT: ret
369 ;
370 ; CHECK-GI-LABEL: bicimm2s_lsl124:
371 ; CHECK-GI: // %bb.0:
372 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #24
373 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
374 ; CHECK-GI-NEXT: ret
375 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
376 ret <2 x i32> %tmp1
377 }
379 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
380 ; CHECK-SD-LABEL: bicimm4s_lsl0:
381 ; CHECK-SD: // %bb.0:
382 ; CHECK-SD-NEXT: bic v0.4s, #16
383 ; CHECK-SD-NEXT: ret
384 ;
385 ; CHECK-GI-LABEL: bicimm4s_lsl0:
386 ; CHECK-GI: // %bb.0:
387 ; CHECK-GI-NEXT: mvni v1.4s, #16
388 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
389 ; CHECK-GI-NEXT: ret
390 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
391 ret <4 x i32> %tmp1
392 }
394 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
395 ; CHECK-SD-LABEL: bicimm4s_lsl8:
396 ; CHECK-SD: // %bb.0:
397 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #8
398 ; CHECK-SD-NEXT: ret
399 ;
400 ; CHECK-GI-LABEL: bicimm4s_lsl8:
401 ; CHECK-GI: // %bb.0:
402 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #8
403 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
404 ; CHECK-GI-NEXT: ret
405 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
406 ret <4 x i32> %tmp1
407 }
409 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
410 ; CHECK-SD-LABEL: bicimm4s_lsl16:
411 ; CHECK-SD: // %bb.0:
412 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #16
413 ; CHECK-SD-NEXT: ret
414 ;
415 ; CHECK-GI-LABEL: bicimm4s_lsl16:
416 ; CHECK-GI: // %bb.0:
417 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #16
418 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
419 ; CHECK-GI-NEXT: ret
420 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
421 ret <4 x i32> %tmp1
422 }
424 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
425 ; CHECK-SD-LABEL: bicimm4s_lsl124:
426 ; CHECK-SD: // %bb.0:
427 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #24
428 ; CHECK-SD-NEXT: ret
429 ;
430 ; CHECK-GI-LABEL: bicimm4s_lsl124:
431 ; CHECK-GI: // %bb.0:
432 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #24
433 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
434 ; CHECK-GI-NEXT: ret
435 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
436 ret <4 x i32> %tmp1
437 }
439 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
440 ; CHECK-SD-LABEL: bicimm4h_lsl0_a:
441 ; CHECK-SD: // %bb.0:
442 ; CHECK-SD-NEXT: bic v0.4h, #16
443 ; CHECK-SD-NEXT: ret
444 ;
445 ; CHECK-GI-LABEL: bicimm4h_lsl0_a:
446 ; CHECK-GI: // %bb.0:
447 ; CHECK-GI-NEXT: mvni v1.4h, #16
448 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
449 ; CHECK-GI-NEXT: ret
450 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
451 ret <4 x i16> %tmp1
452 }
454 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
455 ; CHECK-SD-LABEL: bicimm4h_lsl0_b:
456 ; CHECK-SD: // %bb.0:
457 ; CHECK-SD-NEXT: bic v0.4h, #255
458 ; CHECK-SD-NEXT: ret
459 ;
460 ; CHECK-GI-LABEL: bicimm4h_lsl0_b:
461 ; CHECK-GI: // %bb.0:
462 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
463 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
464 ; CHECK-GI-NEXT: ret
465 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
466 ret <4 x i16> %tmp1
467 }
469 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
470 ; CHECK-SD-LABEL: bicimm4h_lsl8_a:
471 ; CHECK-SD: // %bb.0:
472 ; CHECK-SD-NEXT: bic v0.4h, #16, lsl #8
473 ; CHECK-SD-NEXT: ret
474 ;
475 ; CHECK-GI-LABEL: bicimm4h_lsl8_a:
476 ; CHECK-GI: // %bb.0:
477 ; CHECK-GI-NEXT: mvni v1.4h, #16, lsl #8
478 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
479 ; CHECK-GI-NEXT: ret
480 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
481 ret <4 x i16> %tmp1
482 }
484 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
485 ; CHECK-SD-LABEL: bicimm4h_lsl8_b:
486 ; CHECK-SD: // %bb.0:
487 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
488 ; CHECK-SD-NEXT: ret
489 ;
490 ; CHECK-GI-LABEL: bicimm4h_lsl8_b:
491 ; CHECK-GI: // %bb.0:
492 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
493 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
494 ; CHECK-GI-NEXT: ret
495 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
496 ret <4 x i16> %tmp1
497 }
499 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
500 ; CHECK-SD-LABEL: bicimm8h_lsl0_a:
501 ; CHECK-SD: // %bb.0:
502 ; CHECK-SD-NEXT: bic v0.8h, #16
503 ; CHECK-SD-NEXT: ret
504 ;
505 ; CHECK-GI-LABEL: bicimm8h_lsl0_a:
506 ; CHECK-GI: // %bb.0:
507 ; CHECK-GI-NEXT: mvni v1.8h, #16
508 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
509 ; CHECK-GI-NEXT: ret
510 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
511 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
512 ret <8 x i16> %tmp1
513 }
515 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
516 ; CHECK-SD-LABEL: bicimm8h_lsl0_b:
517 ; CHECK-SD: // %bb.0:
518 ; CHECK-SD-NEXT: bic v0.8h, #255
519 ; CHECK-SD-NEXT: ret
520 ;
521 ; CHECK-GI-LABEL: bicimm8h_lsl0_b:
522 ; CHECK-GI: // %bb.0:
523 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
524 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
525 ; CHECK-GI-NEXT: ret
526 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
527 ret <8 x i16> %tmp1
528 }
530 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
531 ; CHECK-SD-LABEL: bicimm8h_lsl8_a:
532 ; CHECK-SD: // %bb.0:
533 ; CHECK-SD-NEXT: bic v0.8h, #16, lsl #8
534 ; CHECK-SD-NEXT: ret
535 ;
536 ; CHECK-GI-LABEL: bicimm8h_lsl8_a:
537 ; CHECK-GI: // %bb.0:
538 ; CHECK-GI-NEXT: mvni v1.8h, #16, lsl #8
539 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
540 ; CHECK-GI-NEXT: ret
541 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
542 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
543 ret <8 x i16> %tmp1
544 }
546 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
547 ; CHECK-SD-LABEL: bicimm8h_lsl8_b:
548 ; CHECK-SD: // %bb.0:
549 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
550 ; CHECK-SD-NEXT: ret
551 ;
552 ; CHECK-GI-LABEL: bicimm8h_lsl8_b:
553 ; CHECK-GI: // %bb.0:
554 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
555 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
556 ; CHECK-GI-NEXT: ret
557 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
558 ret <8 x i16> %tmp1
559 }
561 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
562 ; CHECK-LABEL: and2xi32:
563 ; CHECK: // %bb.0:
564 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
565 ; CHECK-NEXT: ret
566 %tmp1 = and <2 x i32> %a, %b;
567 ret <2 x i32> %tmp1
568 }
570 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
571 ; CHECK-LABEL: and4xi16:
572 ; CHECK: // %bb.0:
573 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
574 ; CHECK-NEXT: ret
575 %tmp1 = and <4 x i16> %a, %b;
576 ret <4 x i16> %tmp1
577 }
579 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
580 ; CHECK-SD-LABEL: and1xi64:
581 ; CHECK-SD: // %bb.0:
582 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
583 ; CHECK-SD-NEXT: ret
584 ;
585 ; CHECK-GI-LABEL: and1xi64:
586 ; CHECK-GI: // %bb.0:
587 ; CHECK-GI-NEXT: fmov x8, d0
588 ; CHECK-GI-NEXT: fmov x9, d1
589 ; CHECK-GI-NEXT: and x8, x8, x9
590 ; CHECK-GI-NEXT: fmov d0, x8
591 ; CHECK-GI-NEXT: ret
592 %tmp1 = and <1 x i64> %a, %b;
593 ret <1 x i64> %tmp1
594 }
596 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
597 ; CHECK-LABEL: and4xi32:
598 ; CHECK: // %bb.0:
599 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
600 ; CHECK-NEXT: ret
601 %tmp1 = and <4 x i32> %a, %b;
602 ret <4 x i32> %tmp1
603 }
605 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
606 ; CHECK-LABEL: and8xi16:
607 ; CHECK: // %bb.0:
608 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
609 ; CHECK-NEXT: ret
610 %tmp1 = and <8 x i16> %a, %b;
611 ret <8 x i16> %tmp1
612 }
614 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
615 ; CHECK-LABEL: and2xi64:
616 ; CHECK: // %bb.0:
617 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
618 ; CHECK-NEXT: ret
619 %tmp1 = and <2 x i64> %a, %b;
620 ret <2 x i64> %tmp1
621 }
623 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
624 ; CHECK-LABEL: orr2xi32:
625 ; CHECK: // %bb.0:
626 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
627 ; CHECK-NEXT: ret
628 %tmp1 = or <2 x i32> %a, %b;
629 ret <2 x i32> %tmp1
630 }
632 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
633 ; CHECK-LABEL: orr4xi16:
634 ; CHECK: // %bb.0:
635 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
636 ; CHECK-NEXT: ret
637 %tmp1 = or <4 x i16> %a, %b;
638 ret <4 x i16> %tmp1
639 }
641 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
642 ; CHECK-SD-LABEL: orr1xi64:
643 ; CHECK-SD: // %bb.0:
644 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
645 ; CHECK-SD-NEXT: ret
646 ;
647 ; CHECK-GI-LABEL: orr1xi64:
648 ; CHECK-GI: // %bb.0:
649 ; CHECK-GI-NEXT: fmov x8, d0
650 ; CHECK-GI-NEXT: fmov x9, d1
651 ; CHECK-GI-NEXT: orr x8, x8, x9
652 ; CHECK-GI-NEXT: fmov d0, x8
653 ; CHECK-GI-NEXT: ret
654 %tmp1 = or <1 x i64> %a, %b;
655 ret <1 x i64> %tmp1
656 }
658 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
659 ; CHECK-LABEL: orr4xi32:
660 ; CHECK: // %bb.0:
661 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
662 ; CHECK-NEXT: ret
663 %tmp1 = or <4 x i32> %a, %b;
664 ret <4 x i32> %tmp1
665 }
667 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
668 ; CHECK-LABEL: orr8xi16:
669 ; CHECK: // %bb.0:
670 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
671 ; CHECK-NEXT: ret
672 %tmp1 = or <8 x i16> %a, %b;
673 ret <8 x i16> %tmp1
674 }
676 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
677 ; CHECK-LABEL: orr2xi64:
678 ; CHECK: // %bb.0:
679 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
680 ; CHECK-NEXT: ret
681 %tmp1 = or <2 x i64> %a, %b;
682 ret <2 x i64> %tmp1
683 }
685 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
686 ; CHECK-LABEL: eor2xi32:
687 ; CHECK: // %bb.0:
688 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
689 ; CHECK-NEXT: ret
690 %tmp1 = xor <2 x i32> %a, %b;
691 ret <2 x i32> %tmp1
692 }
694 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
695 ; CHECK-LABEL: eor4xi16:
696 ; CHECK: // %bb.0:
697 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
698 ; CHECK-NEXT: ret
699 %tmp1 = xor <4 x i16> %a, %b;
700 ret <4 x i16> %tmp1
701 }
703 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
704 ; CHECK-SD-LABEL: eor1xi64:
705 ; CHECK-SD: // %bb.0:
706 ; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
707 ; CHECK-SD-NEXT: ret
708 ;
709 ; CHECK-GI-LABEL: eor1xi64:
710 ; CHECK-GI: // %bb.0:
711 ; CHECK-GI-NEXT: fmov x8, d0
712 ; CHECK-GI-NEXT: fmov x9, d1
713 ; CHECK-GI-NEXT: eor x8, x8, x9
714 ; CHECK-GI-NEXT: fmov d0, x8
715 ; CHECK-GI-NEXT: ret
716 %tmp1 = xor <1 x i64> %a, %b;
717 ret <1 x i64> %tmp1
718 }
720 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
721 ; CHECK-LABEL: eor4xi32:
722 ; CHECK: // %bb.0:
723 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
724 ; CHECK-NEXT: ret
725 %tmp1 = xor <4 x i32> %a, %b;
726 ret <4 x i32> %tmp1
727 }
729 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
730 ; CHECK-LABEL: eor8xi16:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
733 ; CHECK-NEXT: ret
734 %tmp1 = xor <8 x i16> %a, %b;
735 ret <8 x i16> %tmp1
736 }
738 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
739 ; CHECK-LABEL: eor2xi64:
740 ; CHECK: // %bb.0:
741 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
742 ; CHECK-NEXT: ret
743 %tmp1 = xor <2 x i64> %a, %b;
744 ret <2 x i64> %tmp1
745 }
748 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
749 ; CHECK-LABEL: bic2xi32:
750 ; CHECK: // %bb.0:
751 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
752 ; CHECK-NEXT: ret
753 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
754 %tmp2 = and <2 x i32> %a, %tmp1
755 ret <2 x i32> %tmp2
756 }
758 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
759 ; CHECK-LABEL: bic4xi16:
760 ; CHECK: // %bb.0:
761 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
762 ; CHECK-NEXT: ret
763 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
764 %tmp2 = and <4 x i16> %a, %tmp1
765 ret <4 x i16> %tmp2
766 }
768 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
769 ; CHECK-SD-LABEL: bic1xi64:
770 ; CHECK-SD: // %bb.0:
771 ; CHECK-SD-NEXT: bic v0.8b, v0.8b, v1.8b
772 ; CHECK-SD-NEXT: ret
773 ;
774 ; CHECK-GI-LABEL: bic1xi64:
775 ; CHECK-GI: // %bb.0:
776 ; CHECK-GI-NEXT: fmov x8, d1
777 ; CHECK-GI-NEXT: fmov x9, d0
778 ; CHECK-GI-NEXT: bic x8, x9, x8
779 ; CHECK-GI-NEXT: fmov d0, x8
780 ; CHECK-GI-NEXT: ret
781 %tmp1 = xor <1 x i64> %b, < i64 -1>
782 %tmp2 = and <1 x i64> %a, %tmp1
783 ret <1 x i64> %tmp2
784 }
786 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
787 ; CHECK-LABEL: bic4xi32:
788 ; CHECK: // %bb.0:
789 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
790 ; CHECK-NEXT: ret
791 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
792 %tmp2 = and <4 x i32> %a, %tmp1
793 ret <4 x i32> %tmp2
794 }
796 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
797 ; CHECK-LABEL: bic8xi16:
798 ; CHECK: // %bb.0:
799 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
800 ; CHECK-NEXT: ret
801 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
802 %tmp2 = and <8 x i16> %a, %tmp1
803 ret <8 x i16> %tmp2
804 }
806 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
807 ; CHECK-LABEL: bic2xi64:
808 ; CHECK: // %bb.0:
809 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
810 ; CHECK-NEXT: ret
811 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
812 %tmp2 = and <2 x i64> %a, %tmp1
813 ret <2 x i64> %tmp2
814 }
816 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
817 ; CHECK-LABEL: orn2xi32:
818 ; CHECK: // %bb.0:
819 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
820 ; CHECK-NEXT: ret
821 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
822 %tmp2 = or <2 x i32> %a, %tmp1
823 ret <2 x i32> %tmp2
824 }
826 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
827 ; CHECK-LABEL: orn4xi16:
828 ; CHECK: // %bb.0:
829 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
830 ; CHECK-NEXT: ret
831 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
832 %tmp2 = or <4 x i16> %a, %tmp1
833 ret <4 x i16> %tmp2
834 }
836 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
837 ; CHECK-SD-LABEL: orn1xi64:
838 ; CHECK-SD: // %bb.0:
839 ; CHECK-SD-NEXT: orn v0.8b, v0.8b, v1.8b
840 ; CHECK-SD-NEXT: ret
841 ;
842 ; CHECK-GI-LABEL: orn1xi64:
843 ; CHECK-GI: // %bb.0:
844 ; CHECK-GI-NEXT: fmov x8, d1
845 ; CHECK-GI-NEXT: fmov x9, d0
846 ; CHECK-GI-NEXT: orn x8, x9, x8
847 ; CHECK-GI-NEXT: fmov d0, x8
848 ; CHECK-GI-NEXT: ret
849 %tmp1 = xor <1 x i64> %b, < i64 -1>
850 %tmp2 = or <1 x i64> %a, %tmp1
851 ret <1 x i64> %tmp2
852 }
854 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
855 ; CHECK-LABEL: orn4xi32:
856 ; CHECK: // %bb.0:
857 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
858 ; CHECK-NEXT: ret
859 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
860 %tmp2 = or <4 x i32> %a, %tmp1
861 ret <4 x i32> %tmp2
862 }
864 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
865 ; CHECK-LABEL: orn8xi16:
866 ; CHECK: // %bb.0:
867 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
868 ; CHECK-NEXT: ret
869 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
870 %tmp2 = or <8 x i16> %a, %tmp1
871 ret <8 x i16> %tmp2
872 }
874 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
875 ; CHECK-LABEL: orn2xi64:
876 ; CHECK: // %bb.0:
877 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
878 ; CHECK-NEXT: ret
879 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
880 %tmp2 = or <2 x i64> %a, %tmp1
881 ret <2 x i64> %tmp2
882 }
884 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
885 ; CHECK-SD-LABEL: bsl2xi32_const:
886 ; CHECK-SD: // %bb.0:
887 ; CHECK-SD-NEXT: movi d2, #0x000000ffffffff
888 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
889 ; CHECK-SD-NEXT: ret
890 ;
891 ; CHECK-GI-LABEL: bsl2xi32_const:
892 ; CHECK-GI: // %bb.0:
893 ; CHECK-GI-NEXT: adrp x8, .LCPI70_0
894 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI70_0]
895 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
896 ; CHECK-GI-NEXT: ret
897 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
898 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
899 %tmp3 = or <2 x i32> %tmp1, %tmp2
900 ret <2 x i32> %tmp3
901 }
904 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
905 ; CHECK-SD-LABEL: bsl4xi16_const:
906 ; CHECK-SD: // %bb.0:
907 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
908 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
909 ; CHECK-SD-NEXT: ret
910 ;
911 ; CHECK-GI-LABEL: bsl4xi16_const:
912 ; CHECK-GI: // %bb.0:
913 ; CHECK-GI-NEXT: adrp x8, .LCPI71_0
914 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI71_0]
915 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
916 ; CHECK-GI-NEXT: ret
917 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
918 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
919 %tmp3 = or <4 x i16> %tmp1, %tmp2
920 ret <4 x i16> %tmp3
921 }
923 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
924 ; CHECK-SD-LABEL: bsl1xi64_const:
925 ; CHECK-SD: // %bb.0:
926 ; CHECK-SD-NEXT: movi d2, #0xffffffffffffff00
927 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
928 ; CHECK-SD-NEXT: ret
929 ;
930 ; CHECK-GI-LABEL: bsl1xi64_const:
931 ; CHECK-GI: // %bb.0:
932 ; CHECK-GI-NEXT: fmov x8, d0
933 ; CHECK-GI-NEXT: fmov x9, d1
934 ; CHECK-GI-NEXT: and x8, x8, #0xffffffffffffff00
935 ; CHECK-GI-NEXT: and x9, x9, #0xff
936 ; CHECK-GI-NEXT: orr x8, x8, x9
937 ; CHECK-GI-NEXT: fmov d0, x8
938 ; CHECK-GI-NEXT: ret
939 %tmp1 = and <1 x i64> %a, < i64 -256 >
940 %tmp2 = and <1 x i64> %b, < i64 255 >
941 %tmp3 = or <1 x i64> %tmp1, %tmp2
942 ret <1 x i64> %tmp3
943 }
945 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
946 ; CHECK-SD-LABEL: bsl4xi32_const:
947 ; CHECK-SD: // %bb.0:
948 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
949 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
950 ; CHECK-SD-NEXT: ret
951 ;
952 ; CHECK-GI-LABEL: bsl4xi32_const:
953 ; CHECK-GI: // %bb.0:
954 ; CHECK-GI-NEXT: adrp x8, .LCPI73_0
955 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI73_0]
956 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
957 ; CHECK-GI-NEXT: ret
958 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
959 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
960 %tmp3 = or <4 x i32> %tmp1, %tmp2
961 ret <4 x i32> %tmp3
962 }
964 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
965 ; CHECK-SD-LABEL: bsl8xi16_const:
966 ; CHECK-SD: // %bb.0:
967 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
968 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
969 ; CHECK-SD-NEXT: ret
970 ;
971 ; CHECK-GI-LABEL: bsl8xi16_const:
972 ; CHECK-GI: // %bb.0:
973 ; CHECK-GI-NEXT: adrp x8, .LCPI74_0
974 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI74_0]
975 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
976 ; CHECK-GI-NEXT: ret
977 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
978 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
979 %tmp3 = or <8 x i16> %tmp1, %tmp2
980 ret <8 x i16> %tmp3
981 }
983 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
984 ; CHECK-LABEL: bsl2xi64_const:
985 ; CHECK: // %bb.0:
986 ; CHECK-NEXT: adrp x8, .LCPI75_0
987 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]
988 ; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
989 ; CHECK-NEXT: ret
990 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
991 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
992 %tmp3 = or <2 x i64> %tmp1, %tmp2
993 ret <2 x i64> %tmp3
994 }
997 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
998 ; CHECK-LABEL: bsl8xi8:
999 ; CHECK: // %bb.0:
1000 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1001 ; CHECK-NEXT: ret
1002 %1 = and <8 x i8> %v1, %v2
1003 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1004 %3 = and <8 x i8> %2, %v3
1005 %4 = or <8 x i8> %1, %3
1006 ret <8 x i8> %4
1007 }
1009 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
1010 ; CHECK-LABEL: bsl4xi16:
1011 ; CHECK: // %bb.0:
1012 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1013 ; CHECK-NEXT: ret
1014 %1 = and <4 x i16> %v1, %v2
1015 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
1016 %3 = and <4 x i16> %2, %v3
1017 %4 = or <4 x i16> %1, %3
1018 ret <4 x i16> %4
1019 }
1021 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
1022 ; CHECK-LABEL: bsl2xi32:
1023 ; CHECK: // %bb.0:
1024 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1025 ; CHECK-NEXT: ret
1026 %1 = and <2 x i32> %v1, %v2
1027 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
1028 %3 = and <2 x i32> %2, %v3
1029 %4 = or <2 x i32> %1, %3
1030 ret <2 x i32> %4
1031 }
1033 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
1034 ; CHECK-SD-LABEL: bsl1xi64:
1035 ; CHECK-SD: // %bb.0:
1036 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1037 ; CHECK-SD-NEXT: ret
1038 ;
1039 ; CHECK-GI-LABEL: bsl1xi64:
1040 ; CHECK-GI: // %bb.0:
1041 ; CHECK-GI-NEXT: fmov x8, d0
1042 ; CHECK-GI-NEXT: fmov x9, d1
1043 ; CHECK-GI-NEXT: fmov x10, d2
1044 ; CHECK-GI-NEXT: and x9, x8, x9
1045 ; CHECK-GI-NEXT: bic x8, x10, x8
1046 ; CHECK-GI-NEXT: orr x8, x9, x8
1047 ; CHECK-GI-NEXT: fmov d0, x8
1048 ; CHECK-GI-NEXT: ret
1049 %1 = and <1 x i64> %v1, %v2
1050 %2 = xor <1 x i64> %v1, <i64 -1>
1051 %3 = and <1 x i64> %2, %v3
1052 %4 = or <1 x i64> %1, %3
1053 ret <1 x i64> %4
1054 }
1056 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
1057 ; CHECK-LABEL: bsl16xi8:
1058 ; CHECK: // %bb.0:
1059 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1060 ; CHECK-NEXT: ret
1061 %1 = and <16 x i8> %v1, %v2
1062 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1063 %3 = and <16 x i8> %2, %v3
1064 %4 = or <16 x i8> %1, %3
1065 ret <16 x i8> %4
1066 }
1068 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
1069 ; CHECK-LABEL: bsl8xi16:
1070 ; CHECK: // %bb.0:
1071 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1072 ; CHECK-NEXT: ret
1073 %1 = and <8 x i16> %v1, %v2
1074 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
1075 %3 = and <8 x i16> %2, %v3
1076 %4 = or <8 x i16> %1, %3
1077 ret <8 x i16> %4
1078 }
1080 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
1081 ; CHECK-LABEL: bsl4xi32:
1082 ; CHECK: // %bb.0:
1083 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1084 ; CHECK-NEXT: ret
1085 %1 = and <4 x i32> %v1, %v2
1086 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
1087 %3 = and <4 x i32> %2, %v3
1088 %4 = or <4 x i32> %1, %3
1089 ret <4 x i32> %4
1090 }
1092 define <8 x i8> @vselect_constant_cond_zero_v8i8(<8 x i8> %a) {
1093 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v8i8:
1094 ; CHECK-SD: // %bb.0:
1095 ; CHECK-SD-NEXT: movi d1, #0x00000000ff00ff
1096 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1097 ; CHECK-SD-NEXT: ret
1098 ;
1099 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v8i8:
1100 ; CHECK-GI: // %bb.0:
1101 ; CHECK-GI-NEXT: adrp x8, .LCPI83_0
1102 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI83_0]
1103 ; CHECK-GI-NEXT: shl v1.8b, v1.8b, #7
1104 ; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #7
1105 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1106 ; CHECK-GI-NEXT: ret
1107 %b = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> zeroinitializer
1108 ret <8 x i8> %b
1109 }
1111 define <4 x i16> @vselect_constant_cond_zero_v4i16(<4 x i16> %a) {
1112 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i16:
1113 ; CHECK-SD: // %bb.0:
1114 ; CHECK-SD-NEXT: movi d1, #0xffff00000000ffff
1115 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1116 ; CHECK-SD-NEXT: ret
1117 ;
1118 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i16:
1119 ; CHECK-GI: // %bb.0:
1120 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1121 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1122 ; CHECK-GI-NEXT: fmov s1, w8
1123 ; CHECK-GI-NEXT: fmov s2, w9
1124 ; CHECK-GI-NEXT: mov v3.16b, v1.16b
1125 ; CHECK-GI-NEXT: mov v3.b[1], v2.b[0]
1126 ; CHECK-GI-NEXT: mov v3.b[2], v2.b[0]
1127 ; CHECK-GI-NEXT: mov v3.b[3], v1.b[0]
1128 ; CHECK-GI-NEXT: ushll v1.8h, v3.8b, #0
1129 ; CHECK-GI-NEXT: shl v1.4h, v1.4h, #15
1130 ; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #15
1131 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1132 ; CHECK-GI-NEXT: ret
1133 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> zeroinitializer
1134 ret <4 x i16> %b
1135 }
1137 define <4 x i32> @vselect_constant_cond_zero_v4i32(<4 x i32> %a) {
1138 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i32:
1139 ; CHECK-SD: // %bb.0:
1140 ; CHECK-SD-NEXT: adrp x8, .LCPI85_0
1141 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]
1142 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1143 ; CHECK-SD-NEXT: ret
1144 ;
1145 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i32:
1146 ; CHECK-GI: // %bb.0:
1147 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1148 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1149 ; CHECK-GI-NEXT: fmov s1, w8
1150 ; CHECK-GI-NEXT: fmov s2, w9
1151 ; CHECK-GI-NEXT: mov v3.16b, v1.16b
1152 ; CHECK-GI-NEXT: mov v3.h[1], v2.h[0]
1153 ; CHECK-GI-NEXT: mov v2.h[1], v1.h[0]
1154 ; CHECK-GI-NEXT: ushll v1.4s, v3.4h, #0
1155 ; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
1156 ; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
1157 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
1158 ; CHECK-GI-NEXT: sshr v1.4s, v1.4s, #31
1159 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1160 ; CHECK-GI-NEXT: ret
1161 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> zeroinitializer
1162 ret <4 x i32> %b
1163 }
1165 define <8 x i8> @vselect_constant_cond_v8i8(<8 x i8> %a, <8 x i8> %b) {
1166 ; CHECK-SD-LABEL: vselect_constant_cond_v8i8:
1167 ; CHECK-SD: // %bb.0:
1168 ; CHECK-SD-NEXT: movi d2, #0xffffffffff00ff00
1169 ; CHECK-SD-NEXT: movi d3, #0x00000000ff00ff
1170 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1171 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1172 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1173 ; CHECK-SD-NEXT: ret
1174 ;
1175 ; CHECK-GI-LABEL: vselect_constant_cond_v8i8:
1176 ; CHECK-GI: // %bb.0:
1177 ; CHECK-GI-NEXT: adrp x8, .LCPI86_0
1178 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI86_0]
1179 ; CHECK-GI-NEXT: shl v2.8b, v2.8b, #7
1180 ; CHECK-GI-NEXT: sshr v2.8b, v2.8b, #7
1181 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1182 ; CHECK-GI-NEXT: ret
1183 %c = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> %b
1184 ret <8 x i8> %c
1185 }
1187 define <4 x i16> @vselect_constant_cond_v4i16(<4 x i16> %a, <4 x i16> %b) {
1188 ; CHECK-SD-LABEL: vselect_constant_cond_v4i16:
1189 ; CHECK-SD: // %bb.0:
1190 ; CHECK-SD-NEXT: movi d2, #0x00ffffffff0000
1191 ; CHECK-SD-NEXT: movi d3, #0xffff00000000ffff
1192 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1193 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1194 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1195 ; CHECK-SD-NEXT: ret
1196 ;
1197 ; CHECK-GI-LABEL: vselect_constant_cond_v4i16:
1198 ; CHECK-GI: // %bb.0:
1199 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1200 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1201 ; CHECK-GI-NEXT: fmov s2, w8
1202 ; CHECK-GI-NEXT: fmov s3, w9
1203 ; CHECK-GI-NEXT: mov v4.16b, v2.16b
1204 ; CHECK-GI-NEXT: mov v4.b[1], v3.b[0]
1205 ; CHECK-GI-NEXT: mov v4.b[2], v3.b[0]
1206 ; CHECK-GI-NEXT: mov v4.b[3], v2.b[0]
1207 ; CHECK-GI-NEXT: ushll v2.8h, v4.8b, #0
1208 ; CHECK-GI-NEXT: shl v2.4h, v2.4h, #15
1209 ; CHECK-GI-NEXT: sshr v2.4h, v2.4h, #15
1210 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1211 ; CHECK-GI-NEXT: ret
1212 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> %b
1213 ret <4 x i16> %c
1214 }
1216 define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {
1217 ; CHECK-SD-LABEL: vselect_constant_cond_v4i32:
1218 ; CHECK-SD: // %bb.0:
1219 ; CHECK-SD-NEXT: adrp x8, .LCPI88_0
1220 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI88_0]
1221 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1222 ; CHECK-SD-NEXT: ret
1223 ;
1224 ; CHECK-GI-LABEL: vselect_constant_cond_v4i32:
1225 ; CHECK-GI: // %bb.0:
1226 ; CHECK-GI-NEXT: mov w8, #1 // =0x1
1227 ; CHECK-GI-NEXT: mov w9, #0 // =0x0
1228 ; CHECK-GI-NEXT: fmov s2, w8
1229 ; CHECK-GI-NEXT: fmov s3, w9
1230 ; CHECK-GI-NEXT: mov v4.16b, v2.16b
1231 ; CHECK-GI-NEXT: mov v4.h[1], v3.h[0]
1232 ; CHECK-GI-NEXT: mov v3.h[1], v2.h[0]
1233 ; CHECK-GI-NEXT: ushll v2.4s, v4.4h, #0
1234 ; CHECK-GI-NEXT: ushll v3.4s, v3.4h, #0
1235 ; CHECK-GI-NEXT: mov v2.d[1], v3.d[0]
1236 ; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
1237 ; CHECK-GI-NEXT: sshr v2.4s, v2.4s, #31
1238 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
1239 ; CHECK-GI-NEXT: ret
1240 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b
1241 ret <4 x i32> %c
1242 }
1244 ; CHECK-SD: .byte 0
1245 ; CHECK-SD: .byte 8
1246 ; CHECK-SD: .byte 2
1247 ; CHECK-SD: .byte 9
1248 ; CHECK-SD: .byte 4
1249 ; CHECK-SD: .byte 5
1250 ; CHECK-SD: .byte 6
1251 ; CHECK-SD: .byte 7
1252 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
1253 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8:
1254 ; CHECK-SD: // %bb.0:
1255 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1256 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1257 ; CHECK-SD-NEXT: adrp x8, .LCPI89_0
1258 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
1259 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1260 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1261 ; CHECK-SD-NEXT: ret
1262 ;
1263 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8:
1264 ; CHECK-GI: // %bb.0:
1265 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1266 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1267 ; CHECK-GI-NEXT: adrp x8, .LCPI89_0
1268 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1269 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1270 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1271 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1272 ; CHECK-GI-NEXT: ret
1273 %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1274 ret <8 x i8> %c
1275 }
1277 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
1278 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1279 ; CHECK-SD: // %bb.0:
1280 ; CHECK-SD-NEXT: movi d1, #0xffffffff00ff00ff
1281 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1282 ; CHECK-SD-NEXT: ret
1283 ;
1284 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1285 ; CHECK-GI: // %bb.0:
1286 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1287 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1288 ; CHECK-GI-NEXT: adrp x8, .LCPI90_0
1289 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1290 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI90_0]
1291 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1292 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1293 ; CHECK-GI-NEXT: ret
1294 %c = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1295 ret <8 x i8> %c
1296 }
1298 ; CHECK-SD-LABEL: .LCPI91_0:
1299 ; CHECK-SD-NEXT: .byte 0
1300 ; CHECK-SD-NEXT: .byte 255
1301 ; CHECK-SD-NEXT: .byte 2
1302 ; CHECK-SD-NEXT: .byte 255
1303 ; CHECK-SD-NEXT: .byte 4
1304 ; CHECK-SD-NEXT: .byte 5
1305 ; CHECK-SD-NEXT: .byte 6
1306 ; CHECK-SD-NEXT: .byte 7
1307 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {
1308 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1309 ; CHECK-SD: // %bb.0:
1310 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1311 ; CHECK-SD-NEXT: adrp x8, .LCPI91_0
1312 ; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
1313 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI91_0]
1314 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1315 ; CHECK-SD-NEXT: ret
1316 ;
1317 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1318 ; CHECK-GI: // %bb.0:
1319 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1320 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1321 ; CHECK-GI-NEXT: adrp x8, .LCPI91_0
1322 ; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
1323 ; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI91_0]
1324 ; CHECK-GI-NEXT: tbl v0.16b, { v1.16b }, v0.16b
1325 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1326 ; CHECK-GI-NEXT: ret
1327 %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1328 ret <8 x i8> %c
1329 }
1331 ; CHECK-SD-LABEL: .LCPI92_0:
1332 ; CHECK-SD-NEXT: .byte 0
1333 ; CHECK-SD-NEXT: .byte 1
1334 ; CHECK-SD-NEXT: .byte 16
1335 ; CHECK-SD-NEXT: .byte 17
1336 ; CHECK-SD-NEXT: .byte 4
1337 ; CHECK-SD-NEXT: .byte 5
1338 ; CHECK-SD-NEXT: .byte 18
1339 ; CHECK-SD-NEXT: .byte 19
1340 ; CHECK-SD-NEXT: .byte 8
1341 ; CHECK-SD-NEXT: .byte 9
1342 ; CHECK-SD-NEXT: .byte 10
1343 ; CHECK-SD-NEXT: .byte 11
1344 ; CHECK-SD-NEXT: .byte 12
1345 ; CHECK-SD-NEXT: .byte 13
1346 ; CHECK-SD-NEXT: .byte 14
1347 ; CHECK-SD-NEXT: .byte 15
1348 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
1349 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16:
1350 ; CHECK-SD: // %bb.0:
1351 ; CHECK-SD-NEXT: adrp x8, .LCPI92_0
1352 ; CHECK-SD-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1353 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1354 ; CHECK-SD-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1355 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1356 ; CHECK-SD-NEXT: ret
1357 ;
1358 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16:
1359 ; CHECK-GI: // %bb.0:
1360 ; CHECK-GI-NEXT: adrp x8, .LCPI92_0
1361 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1362 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1363 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1364 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1365 ; CHECK-GI-NEXT: ret
1366 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1367 ret <8 x i16> %c
1368 }
1370 ; CHECK-SD-LABEL: .LCPI93_0:
1371 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1372 ; CHECK-SD-NEXT: .hword 0 // 0x0
1373 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1374 ; CHECK-SD-NEXT: .hword 0 // 0x0
1375 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1376 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1377 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1378 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1379 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {
1380 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1381 ; CHECK-SD: // %bb.0:
1382 ; CHECK-SD-NEXT: adrp x8, .LCPI93_0
1383 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI93_0]
1384 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1385 ; CHECK-SD-NEXT: ret
1386 ;
1387 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1388 ; CHECK-GI: // %bb.0:
1389 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
1390 ; CHECK-GI-NEXT: adrp x8, .LCPI93_0
1391 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1392 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI93_0]
1393 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1394 ; CHECK-GI-NEXT: ret
1395 %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1396 ret <8 x i16> %c
1397 }
1399 ; CHECK-SD: .byte 0
1400 ; CHECK-SD: .byte 1
1401 ; CHECK-SD: .byte 255
1402 ; CHECK-SD: .byte 255
1403 ; CHECK-SD: .byte 4
1404 ; CHECK-SD: .byte 5
1405 ; CHECK-SD: .byte 255
1406 ; CHECK-SD: .byte 255
1407 ; CHECK-SD: .byte 8
1408 ; CHECK-SD: .byte 9
1409 ; CHECK-SD: .byte 10
1410 ; CHECK-SD: .byte 11
1411 ; CHECK-SD: .byte 12
1412 ; CHECK-SD: .byte 13
1413 ; CHECK-SD: .byte 14
1414 ; CHECK-SD: .byte 15
1415 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {
1416 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1417 ; CHECK-SD: // %bb.0:
1418 ; CHECK-SD-NEXT: adrp x8, .LCPI94_0
1419 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1420 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1421 ; CHECK-SD-NEXT: ret
1422 ;
1423 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1424 ; CHECK-GI: // %bb.0:
1425 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q31_q0
1426 ; CHECK-GI-NEXT: adrp x8, .LCPI94_0
1427 ; CHECK-GI-NEXT: movi v31.2d, #0000000000000000
1428 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1429 ; CHECK-GI-NEXT: tbl v0.16b, { v31.16b, v0.16b }, v1.16b
1430 ; CHECK-GI-NEXT: ret
1431 %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1432 ret <8 x i16> %c
1433 }
1435 define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {
1436 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i16:
1437 ; CHECK-SD: // %bb.0:
1438 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1439 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1440 ; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]
1441 ; CHECK-SD-NEXT: mov v0.h[2], v1.h[1]
1442 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
1443 ; CHECK-SD-NEXT: ret
1444 ;
1445 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i16:
1446 ; CHECK-GI: // %bb.0:
1447 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1448 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1449 ; CHECK-GI-NEXT: adrp x8, .LCPI95_0
1450 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1451 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI95_0]
1452 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1453 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1454 ; CHECK-GI-NEXT: ret
1455 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1456 ret <4 x i16> %c
1457 }
1459 define <4 x i32> @vselect_equivalent_shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
1460 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i32:
1461 ; CHECK-SD: // %bb.0:
1462 ; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]
1463 ; CHECK-SD-NEXT: mov v0.s[2], v1.s[1]
1464 ; CHECK-SD-NEXT: ret
1465 ;
1466 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i32:
1467 ; CHECK-GI: // %bb.0:
1468 ; CHECK-GI-NEXT: adrp x8, .LCPI96_0
1469 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1470 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI96_0]
1471 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1472 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1473 ; CHECK-GI-NEXT: ret
1474 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1475 ret <4 x i32> %c
1476 }
1478 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1479 ; CHECK-SD-LABEL: vselect_cmp_ne:
1480 ; CHECK-SD: // %bb.0:
1481 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
1482 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1483 ; CHECK-SD-NEXT: ret
1484 ;
1485 ; CHECK-GI-LABEL: vselect_cmp_ne:
1486 ; CHECK-GI: // %bb.0:
1487 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
1488 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1489 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1490 ; CHECK-GI-NEXT: ret
1491 %cmp = icmp ne <8 x i8> %a, %b
1492 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1493 ret <8 x i8> %d
1494 }
1496 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1497 ; CHECK-LABEL: vselect_cmp_eq:
1498 ; CHECK: // %bb.0:
1499 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
1500 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1501 ; CHECK-NEXT: ret
1502 %cmp = icmp eq <8 x i8> %a, %b
1503 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1504 ret <8 x i8> %d
1505 }
1507 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1508 ; CHECK-SD-LABEL: vselect_cmpz_ne:
1509 ; CHECK-SD: // %bb.0:
1510 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1511 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1512 ; CHECK-SD-NEXT: ret
1513 ;
1514 ; CHECK-GI-LABEL: vselect_cmpz_ne:
1515 ; CHECK-GI: // %bb.0:
1516 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1517 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1518 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1519 ; CHECK-GI-NEXT: ret
1520 %cmp = icmp ne <8 x i8> %a, zeroinitializer
1521 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1522 ret <8 x i8> %d
1523 }
1525 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1526 ; CHECK-LABEL: vselect_cmpz_eq:
1527 ; CHECK: // %bb.0:
1528 ; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
1529 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1530 ; CHECK-NEXT: ret
1531 %cmp = icmp eq <8 x i8> %a, zeroinitializer
1532 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1533 ret <8 x i8> %d
1534 }
1536 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1537 ; CHECK-LABEL: vselect_tst:
1538 ; CHECK: // %bb.0:
1539 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
1540 ; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
1541 ; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
1542 ; CHECK-NEXT: ret
1543 %tmp3 = and <8 x i8> %a, %b
1544 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
1545 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
1546 ret <8 x i8> %d
1547 }
1549 define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1550 ; CHECK-SD-LABEL: sext_tst:
1551 ; CHECK-SD: // %bb.0:
1552 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
1553 ; CHECK-SD-NEXT: ret
1554 ;
1555 ; CHECK-GI-LABEL: sext_tst:
1556 ; CHECK-GI: // %bb.0:
1557 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1558 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
1559 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1560 ; CHECK-GI-NEXT: ret
1561 %tmp3 = and <8 x i8> %a, %b
1562 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
1563 %d = sext <8 x i1> %tmp4 to <8 x i8>
1564 ret <8 x i8> %d
1565 }
1567 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
1568 ; CHECK-LABEL: bsl2xi64:
1569 ; CHECK: // %bb.0:
1570 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1571 ; CHECK-NEXT: ret
1572 %1 = and <2 x i64> %v1, %v2
1573 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
1574 %3 = and <2 x i64> %2, %v3
1575 %4 = or <2 x i64> %1, %3
1576 ret <2 x i64> %4
1577 }
1579 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
1580 ; CHECK-SD-LABEL: orrimm8b_as_orrimm4h_lsl0:
1581 ; CHECK-SD: // %bb.0:
1582 ; CHECK-SD-NEXT: orr v0.4h, #255
1583 ; CHECK-SD-NEXT: ret
1584 ;
1585 ; CHECK-GI-LABEL: orrimm8b_as_orrimm4h_lsl0:
1586 ; CHECK-GI: // %bb.0:
1587 ; CHECK-GI-NEXT: adrp x8, .LCPI104_0
1588 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI104_0]
1589 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1590 ; CHECK-GI-NEXT: ret
1591 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1592 ret <8 x i8> %val
1593 }
1595 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
1596 ; CHECK-SD-LABEL: orrimm8b_as_orimm4h_lsl8:
1597 ; CHECK-SD: // %bb.0:
1598 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
1599 ; CHECK-SD-NEXT: ret
1600 ;
1601 ; CHECK-GI-LABEL: orrimm8b_as_orimm4h_lsl8:
1602 ; CHECK-GI: // %bb.0:
1603 ; CHECK-GI-NEXT: adrp x8, .LCPI105_0
1604 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI105_0]
1605 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1606 ; CHECK-GI-NEXT: ret
1607 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1608 ret <8 x i8> %val
1609 }
1611 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
1612 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl0:
1613 ; CHECK-SD: // %bb.0:
1614 ; CHECK-SD-NEXT: orr v0.8h, #255
1615 ; CHECK-SD-NEXT: ret
1616 ;
1617 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl0:
1618 ; CHECK-GI: // %bb.0:
1619 ; CHECK-GI-NEXT: adrp x8, .LCPI106_0
1620 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI106_0]
1621 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1622 ; CHECK-GI-NEXT: ret
1623 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1624 ret <16 x i8> %val
1625 }
1627 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
1628 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl8:
1629 ; CHECK-SD: // %bb.0:
1630 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
1631 ; CHECK-SD-NEXT: ret
1632 ;
1633 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl8:
1634 ; CHECK-GI: // %bb.0:
1635 ; CHECK-GI-NEXT: adrp x8, .LCPI107_0
1636 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI107_0]
1637 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1638 ; CHECK-GI-NEXT: ret
1639 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1640 ret <16 x i8> %val
1641 }
1643 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
1644 ; CHECK-SD-LABEL: and8imm2s_lsl0:
1645 ; CHECK-SD: // %bb.0:
1646 ; CHECK-SD-NEXT: bic v0.2s, #255
1647 ; CHECK-SD-NEXT: ret
1648 ;
1649 ; CHECK-GI-LABEL: and8imm2s_lsl0:
1650 ; CHECK-GI: // %bb.0:
1651 ; CHECK-GI-NEXT: adrp x8, .LCPI108_0
1652 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI108_0]
1653 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1654 ; CHECK-GI-NEXT: ret
1655 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1656 ret <8 x i8> %tmp1
1657 }
1659 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
1660 ; CHECK-SD-LABEL: and8imm2s_lsl8:
1661 ; CHECK-SD: // %bb.0:
1662 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1663 ; CHECK-SD-NEXT: ret
1664 ;
1665 ; CHECK-GI-LABEL: and8imm2s_lsl8:
1666 ; CHECK-GI: // %bb.0:
1667 ; CHECK-GI-NEXT: adrp x8, .LCPI109_0
1668 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI109_0]
1669 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1670 ; CHECK-GI-NEXT: ret
1671 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1672 ret <8 x i8> %tmp1
1673 }
1675 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
1676 ; CHECK-SD-LABEL: and8imm2s_lsl16:
1677 ; CHECK-SD: // %bb.0:
1678 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1679 ; CHECK-SD-NEXT: ret
1680 ;
1681 ; CHECK-GI-LABEL: and8imm2s_lsl16:
1682 ; CHECK-GI: // %bb.0:
1683 ; CHECK-GI-NEXT: adrp x8, .LCPI110_0
1684 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI110_0]
1685 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1686 ; CHECK-GI-NEXT: ret
1687 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1688 ret <8 x i8> %tmp1
1689 }
1691 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
1692 ; CHECK-SD-LABEL: and8imm2s_lsl24:
1693 ; CHECK-SD: // %bb.0:
1694 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1695 ; CHECK-SD-NEXT: ret
1696 ;
1697 ; CHECK-GI-LABEL: and8imm2s_lsl24:
1698 ; CHECK-GI: // %bb.0:
1699 ; CHECK-GI-NEXT: adrp x8, .LCPI111_0
1700 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI111_0]
1701 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1702 ; CHECK-GI-NEXT: ret
1703 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1704 ret <8 x i8> %tmp1
1705 }
1707 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
1708 ; CHECK-SD-LABEL: and16imm2s_lsl0:
1709 ; CHECK-SD: // %bb.0:
1710 ; CHECK-SD-NEXT: bic v0.2s, #255
1711 ; CHECK-SD-NEXT: ret
1712 ;
1713 ; CHECK-GI-LABEL: and16imm2s_lsl0:
1714 ; CHECK-GI: // %bb.0:
1715 ; CHECK-GI-NEXT: adrp x8, .LCPI112_0
1716 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI112_0]
1717 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1718 ; CHECK-GI-NEXT: ret
1719 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
1720 ret <4 x i16> %tmp1
1721 }
1723 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
1724 ; CHECK-SD-LABEL: and16imm2s_lsl8:
1725 ; CHECK-SD: // %bb.0:
1726 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1727 ; CHECK-SD-NEXT: ret
1728 ;
1729 ; CHECK-GI-LABEL: and16imm2s_lsl8:
1730 ; CHECK-GI: // %bb.0:
1731 ; CHECK-GI-NEXT: adrp x8, .LCPI113_0
1732 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI113_0]
1733 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1734 ; CHECK-GI-NEXT: ret
1735 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
1736 ret <4 x i16> %tmp1
1737 }
1739 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
1740 ; CHECK-SD-LABEL: and16imm2s_lsl16:
1741 ; CHECK-SD: // %bb.0:
1742 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1743 ; CHECK-SD-NEXT: ret
1744 ;
1745 ; CHECK-GI-LABEL: and16imm2s_lsl16:
1746 ; CHECK-GI: // %bb.0:
1747 ; CHECK-GI-NEXT: adrp x8, .LCPI114_0
1748 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI114_0]
1749 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1750 ; CHECK-GI-NEXT: ret
1751 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
1752 ret <4 x i16> %tmp1
1753 }
1755 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
1756 ; CHECK-SD-LABEL: and16imm2s_lsl24:
1757 ; CHECK-SD: // %bb.0:
1758 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1759 ; CHECK-SD-NEXT: ret
1760 ;
1761 ; CHECK-GI-LABEL: and16imm2s_lsl24:
1762 ; CHECK-GI: // %bb.0:
1763 ; CHECK-GI-NEXT: adrp x8, .LCPI115_0
1764 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI115_0]
1765 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1766 ; CHECK-GI-NEXT: ret
1767 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
1768 ret <4 x i16> %tmp1
1769 }
1772 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
1773 ; CHECK-SD-LABEL: and64imm2s_lsl0:
1774 ; CHECK-SD: // %bb.0:
1775 ; CHECK-SD-NEXT: bic v0.2s, #255
1776 ; CHECK-SD-NEXT: ret
1777 ;
1778 ; CHECK-GI-LABEL: and64imm2s_lsl0:
1779 ; CHECK-GI: // %bb.0:
1780 ; CHECK-GI-NEXT: fmov x8, d0
1781 ; CHECK-GI-NEXT: and x8, x8, #0xffffff00ffffff00
1782 ; CHECK-GI-NEXT: fmov d0, x8
1783 ; CHECK-GI-NEXT: ret
1784 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
1785 ret <1 x i64> %tmp1
1786 }
1788 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
1789 ; CHECK-SD-LABEL: and64imm2s_lsl8:
1790 ; CHECK-SD: // %bb.0:
1791 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1792 ; CHECK-SD-NEXT: ret
1793 ;
1794 ; CHECK-GI-LABEL: and64imm2s_lsl8:
1795 ; CHECK-GI: // %bb.0:
1796 ; CHECK-GI-NEXT: fmov x8, d0
1797 ; CHECK-GI-NEXT: and x8, x8, #0xffff00ffffff00ff
1798 ; CHECK-GI-NEXT: fmov d0, x8
1799 ; CHECK-GI-NEXT: ret
1800 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
1801 ret <1 x i64> %tmp1
1802 }
1804 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
1805 ; CHECK-SD-LABEL: and64imm2s_lsl16:
1806 ; CHECK-SD: // %bb.0:
1807 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1808 ; CHECK-SD-NEXT: ret
1809 ;
1810 ; CHECK-GI-LABEL: and64imm2s_lsl16:
1811 ; CHECK-GI: // %bb.0:
1812 ; CHECK-GI-NEXT: fmov x8, d0
1813 ; CHECK-GI-NEXT: and x8, x8, #0xff00ffffff00ffff
1814 ; CHECK-GI-NEXT: fmov d0, x8
1815 ; CHECK-GI-NEXT: ret
1816 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
1817 ret <1 x i64> %tmp1
1818 }
1820 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
1821 ; CHECK-SD-LABEL: and64imm2s_lsl24:
1822 ; CHECK-SD: // %bb.0:
1823 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1824 ; CHECK-SD-NEXT: ret
1825 ;
1826 ; CHECK-GI-LABEL: and64imm2s_lsl24:
1827 ; CHECK-GI: // %bb.0:
1828 ; CHECK-GI-NEXT: fmov x8, d0
1829 ; CHECK-GI-NEXT: and x8, x8, #0x1ffffff01ffffff
1830 ; CHECK-GI-NEXT: fmov d0, x8
1831 ; CHECK-GI-NEXT: ret
1832 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
1833 ret <1 x i64> %tmp1
1834 }
1836 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
1837 ; CHECK-SD-LABEL: and8imm4s_lsl0:
1838 ; CHECK-SD: // %bb.0:
1839 ; CHECK-SD-NEXT: bic v0.4s, #255
1840 ; CHECK-SD-NEXT: ret
1841 ;
1842 ; CHECK-GI-LABEL: and8imm4s_lsl0:
1843 ; CHECK-GI: // %bb.0:
1844 ; CHECK-GI-NEXT: adrp x8, .LCPI120_0
1845 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI120_0]
1846 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1847 ; CHECK-GI-NEXT: ret
1848 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1849 ret <16 x i8> %tmp1
1850 }
1852 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
1853 ; CHECK-SD-LABEL: and8imm4s_lsl8:
1854 ; CHECK-SD: // %bb.0:
1855 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1856 ; CHECK-SD-NEXT: ret
1857 ;
1858 ; CHECK-GI-LABEL: and8imm4s_lsl8:
1859 ; CHECK-GI: // %bb.0:
1860 ; CHECK-GI-NEXT: adrp x8, .LCPI121_0
1861 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI121_0]
1862 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1863 ; CHECK-GI-NEXT: ret
1864 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1865 ret <16 x i8> %tmp1
1866 }
1868 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
1869 ; CHECK-SD-LABEL: and8imm4s_lsl16:
1870 ; CHECK-SD: // %bb.0:
1871 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1872 ; CHECK-SD-NEXT: ret
1873 ;
1874 ; CHECK-GI-LABEL: and8imm4s_lsl16:
1875 ; CHECK-GI: // %bb.0:
1876 ; CHECK-GI-NEXT: adrp x8, .LCPI122_0
1877 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI122_0]
1878 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1879 ; CHECK-GI-NEXT: ret
1880 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1881 ret <16 x i8> %tmp1
1882 }
1884 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
1885 ; CHECK-SD-LABEL: and8imm4s_lsl24:
1886 ; CHECK-SD: // %bb.0:
1887 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1888 ; CHECK-SD-NEXT: ret
1889 ;
1890 ; CHECK-GI-LABEL: and8imm4s_lsl24:
1891 ; CHECK-GI: // %bb.0:
1892 ; CHECK-GI-NEXT: adrp x8, .LCPI123_0
1893 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI123_0]
1894 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1895 ; CHECK-GI-NEXT: ret
1896 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1897 ret <16 x i8> %tmp1
1898 }
1900 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
1901 ; CHECK-SD-LABEL: and16imm4s_lsl0:
1902 ; CHECK-SD: // %bb.0:
1903 ; CHECK-SD-NEXT: bic v0.4s, #255
1904 ; CHECK-SD-NEXT: ret
1905 ;
1906 ; CHECK-GI-LABEL: and16imm4s_lsl0:
1907 ; CHECK-GI: // %bb.0:
1908 ; CHECK-GI-NEXT: adrp x8, .LCPI124_0
1909 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI124_0]
1910 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1911 ; CHECK-GI-NEXT: ret
1912 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
1913 ret <8 x i16> %tmp1
1914 }
1916 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
1917 ; CHECK-SD-LABEL: and16imm4s_lsl8:
1918 ; CHECK-SD: // %bb.0:
1919 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1920 ; CHECK-SD-NEXT: ret
1921 ;
1922 ; CHECK-GI-LABEL: and16imm4s_lsl8:
1923 ; CHECK-GI: // %bb.0:
1924 ; CHECK-GI-NEXT: adrp x8, .LCPI125_0
1925 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0]
1926 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1927 ; CHECK-GI-NEXT: ret
1928 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
1929 ret <8 x i16> %tmp1
1930 }
1932 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
1933 ; CHECK-SD-LABEL: and16imm4s_lsl16:
1934 ; CHECK-SD: // %bb.0:
1935 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1936 ; CHECK-SD-NEXT: ret
1937 ;
1938 ; CHECK-GI-LABEL: and16imm4s_lsl16:
1939 ; CHECK-GI: // %bb.0:
1940 ; CHECK-GI-NEXT: adrp x8, .LCPI126_0
1941 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI126_0]
1942 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1943 ; CHECK-GI-NEXT: ret
1944 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
1945 ret <8 x i16> %tmp1
1946 }
1948 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
1949 ; CHECK-SD-LABEL: and16imm4s_lsl24:
1950 ; CHECK-SD: // %bb.0:
1951 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1952 ; CHECK-SD-NEXT: ret
1953 ;
1954 ; CHECK-GI-LABEL: and16imm4s_lsl24:
1955 ; CHECK-GI: // %bb.0:
1956 ; CHECK-GI-NEXT: adrp x8, .LCPI127_0
1957 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]
1958 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1959 ; CHECK-GI-NEXT: ret
1960 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
1961 ret <8 x i16> %tmp1
1962 }
1964 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
1965 ; CHECK-SD-LABEL: and64imm4s_lsl0:
1966 ; CHECK-SD: // %bb.0:
1967 ; CHECK-SD-NEXT: bic v0.4s, #255
1968 ; CHECK-SD-NEXT: ret
1969 ;
1970 ; CHECK-GI-LABEL: and64imm4s_lsl0:
1971 ; CHECK-GI: // %bb.0:
1972 ; CHECK-GI-NEXT: movi v1.2d, #0xffffff00ffffff00
1973 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1974 ; CHECK-GI-NEXT: ret
1975 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
1976 ret <2 x i64> %tmp1
1977 }
1979 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
1980 ; CHECK-SD-LABEL: and64imm4s_lsl8:
1981 ; CHECK-SD: // %bb.0:
1982 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1983 ; CHECK-SD-NEXT: ret
1984 ;
1985 ; CHECK-GI-LABEL: and64imm4s_lsl8:
1986 ; CHECK-GI: // %bb.0:
1987 ; CHECK-GI-NEXT: movi v1.2d, #0xffff00ffffff00ff
1988 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1989 ; CHECK-GI-NEXT: ret
1990 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
1991 ret <2 x i64> %tmp1
1992 }
1994 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
1995 ; CHECK-SD-LABEL: and64imm4s_lsl16:
1996 ; CHECK-SD: // %bb.0:
1997 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1998 ; CHECK-SD-NEXT: ret
1999 ;
2000 ; CHECK-GI-LABEL: and64imm4s_lsl16:
2001 ; CHECK-GI: // %bb.0:
2002 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ffffff00ffff
2003 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2004 ; CHECK-GI-NEXT: ret
2005 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
2006 ret <2 x i64> %tmp1
2007 }
2009 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
2010 ; CHECK-SD-LABEL: and64imm4s_lsl24:
2011 ; CHECK-SD: // %bb.0:
2012 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
2013 ; CHECK-SD-NEXT: ret
2014 ;
2015 ; CHECK-GI-LABEL: and64imm4s_lsl24:
2016 ; CHECK-GI: // %bb.0:
2017 ; CHECK-GI-NEXT: mvni v1.4s, #254, lsl #24
2018 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2019 ; CHECK-GI-NEXT: ret
2020 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
2021 ret <2 x i64> %tmp1
2022 }
2024 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
2025 ; CHECK-SD-LABEL: and8imm4h_lsl0:
2026 ; CHECK-SD: // %bb.0:
2027 ; CHECK-SD-NEXT: bic v0.4h, #255
2028 ; CHECK-SD-NEXT: ret
2029 ;
2030 ; CHECK-GI-LABEL: and8imm4h_lsl0:
2031 ; CHECK-GI: // %bb.0:
2032 ; CHECK-GI-NEXT: adrp x8, .LCPI132_0
2033 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI132_0]
2034 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2035 ; CHECK-GI-NEXT: ret
2036 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2037 ret <8 x i8> %tmp1
2038 }
2040 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
2041 ; CHECK-SD-LABEL: and8imm4h_lsl8:
2042 ; CHECK-SD: // %bb.0:
2043 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2044 ; CHECK-SD-NEXT: ret
2045 ;
2046 ; CHECK-GI-LABEL: and8imm4h_lsl8:
2047 ; CHECK-GI: // %bb.0:
2048 ; CHECK-GI-NEXT: adrp x8, .LCPI133_0
2049 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]
2050 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2051 ; CHECK-GI-NEXT: ret
2052 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2053 ret <8 x i8> %tmp1
2054 }
2056 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
2057 ; CHECK-SD-LABEL: and16imm4h_lsl0:
2058 ; CHECK-SD: // %bb.0:
2059 ; CHECK-SD-NEXT: bic v0.4h, #255
2060 ; CHECK-SD-NEXT: ret
2061 ;
2062 ; CHECK-GI-LABEL: and16imm4h_lsl0:
2063 ; CHECK-GI: // %bb.0:
2064 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2065 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2066 ; CHECK-GI-NEXT: ret
2067 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
2068 ret <2 x i32> %tmp1
2069 }
2071 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
2072 ; CHECK-SD-LABEL: and16imm4h_lsl8:
2073 ; CHECK-SD: // %bb.0:
2074 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2075 ; CHECK-SD-NEXT: ret
2076 ;
2077 ; CHECK-GI-LABEL: and16imm4h_lsl8:
2078 ; CHECK-GI: // %bb.0:
2079 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2080 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2081 ; CHECK-GI-NEXT: ret
2082 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
2083 ret <2 x i32> %tmp1
2084 }
2086 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
2087 ; CHECK-SD-LABEL: and64imm4h_lsl0:
2088 ; CHECK-SD: // %bb.0:
2089 ; CHECK-SD-NEXT: bic v0.4h, #255
2090 ; CHECK-SD-NEXT: ret
2091 ;
2092 ; CHECK-GI-LABEL: and64imm4h_lsl0:
2093 ; CHECK-GI: // %bb.0:
2094 ; CHECK-GI-NEXT: fmov x8, d0
2095 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff00
2096 ; CHECK-GI-NEXT: fmov d0, x8
2097 ; CHECK-GI-NEXT: ret
2098 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
2099 ret <1 x i64> %tmp1
2100 }
2102 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
2103 ; CHECK-SD-LABEL: and64imm4h_lsl8:
2104 ; CHECK-SD: // %bb.0:
2105 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2106 ; CHECK-SD-NEXT: ret
2107 ;
2108 ; CHECK-GI-LABEL: and64imm4h_lsl8:
2109 ; CHECK-GI: // %bb.0:
2110 ; CHECK-GI-NEXT: fmov x8, d0
2111 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff
2112 ; CHECK-GI-NEXT: fmov d0, x8
2113 ; CHECK-GI-NEXT: ret
2114 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
2115 ret <1 x i64> %tmp1
2116 }
2118 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
2119 ; CHECK-SD-LABEL: and8imm8h_lsl0:
2120 ; CHECK-SD: // %bb.0:
2121 ; CHECK-SD-NEXT: bic v0.8h, #255
2122 ; CHECK-SD-NEXT: ret
2123 ;
2124 ; CHECK-GI-LABEL: and8imm8h_lsl0:
2125 ; CHECK-GI: // %bb.0:
2126 ; CHECK-GI-NEXT: adrp x8, .LCPI138_0
2127 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]
2128 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2129 ; CHECK-GI-NEXT: ret
2130 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
2131 ret <16 x i8> %tmp1
2132 }
2134 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
2135 ; CHECK-SD-LABEL: and8imm8h_lsl8:
2136 ; CHECK-SD: // %bb.0:
2137 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2138 ; CHECK-SD-NEXT: ret
2139 ;
2140 ; CHECK-GI-LABEL: and8imm8h_lsl8:
2141 ; CHECK-GI: // %bb.0:
2142 ; CHECK-GI-NEXT: adrp x8, .LCPI139_0
2143 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
2144 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2145 ; CHECK-GI-NEXT: ret
2146 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
2147 ret <16 x i8> %tmp1
2148 }
2150 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
2151 ; CHECK-SD-LABEL: and16imm8h_lsl0:
2152 ; CHECK-SD: // %bb.0:
2153 ; CHECK-SD-NEXT: bic v0.8h, #255
2154 ; CHECK-SD-NEXT: ret
2155 ;
2156 ; CHECK-GI-LABEL: and16imm8h_lsl0:
2157 ; CHECK-GI: // %bb.0:
2158 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2159 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2160 ; CHECK-GI-NEXT: ret
2161 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2162 ret <4 x i32> %tmp1
2163 }
2165 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
2166 ; CHECK-SD-LABEL: and16imm8h_lsl8:
2167 ; CHECK-SD: // %bb.0:
2168 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2169 ; CHECK-SD-NEXT: ret
2170 ;
2171 ; CHECK-GI-LABEL: and16imm8h_lsl8:
2172 ; CHECK-GI: // %bb.0:
2173 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2174 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2175 ; CHECK-GI-NEXT: ret
2176 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2177 ret <4 x i32> %tmp1
2178 }
2180 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
2181 ; CHECK-SD-LABEL: and64imm8h_lsl0:
2182 ; CHECK-SD: // %bb.0:
2183 ; CHECK-SD-NEXT: bic v0.8h, #255
2184 ; CHECK-SD-NEXT: ret
2185 ;
2186 ; CHECK-GI-LABEL: and64imm8h_lsl0:
2187 ; CHECK-GI: // %bb.0:
2188 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2189 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2190 ; CHECK-GI-NEXT: ret
2191 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2192 ret <2 x i64> %tmp1
2193 }
2195 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
2196 ; CHECK-SD-LABEL: and64imm8h_lsl8:
2197 ; CHECK-SD: // %bb.0:
2198 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2199 ; CHECK-SD-NEXT: ret
2200 ;
2201 ; CHECK-GI-LABEL: and64imm8h_lsl8:
2202 ; CHECK-GI: // %bb.0:
2203 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2204 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2205 ; CHECK-GI-NEXT: ret
2206 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2207 ret <2 x i64> %tmp1
2208 }
2210 define <8 x i16> @bic_shifted_knownbits(<8 x i16> %v) {
2211 ; CHECK-SD-LABEL: bic_shifted_knownbits:
2212 ; CHECK-SD: // %bb.0: // %entry
2213 ; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #9
2214 ; CHECK-SD-NEXT: bic v0.8h, #126
2215 ; CHECK-SD-NEXT: ret
2216 ;
2217 ; CHECK-GI-LABEL: bic_shifted_knownbits:
2218 ; CHECK-GI: // %bb.0: // %entry
2219 ; CHECK-GI-NEXT: movi v1.8h, #1
2220 ; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #9
2221 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2222 ; CHECK-GI-NEXT: ret
2223 entry:
2224 %vshr_n = lshr <8 x i16> %v, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
2225 %and.i = and <8 x i16> %vshr_n, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2226 ret <8 x i16> %and.i
2227 }
2229 define <8 x i32> @bic_shifted_knownbits2(<8 x i16> %v) {
2230 ; CHECK-SD-LABEL: bic_shifted_knownbits2:
2231 ; CHECK-SD: // %bb.0: // %entry
2232 ; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0
2233 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2234 ; CHECK-SD-NEXT: bic v2.4s, #255, lsl #8
2235 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2236 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
2237 ; CHECK-SD-NEXT: ret
2238 ;
2239 ; CHECK-GI-LABEL: bic_shifted_knownbits2:
2240 ; CHECK-GI: // %bb.0: // %entry
2241 ; CHECK-GI-NEXT: adrp x8, .LCPI145_0
2242 ; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
2243 ; CHECK-GI-NEXT: ushll2 v2.4s, v0.8h, #0
2244 ; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI145_0]
2245 ; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b
2246 ; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b
2247 ; CHECK-GI-NEXT: ret
2248 entry:
2249 %vshr_n = zext <8 x i16> %v to <8 x i32>
2250 %and.i = and <8 x i32> %vshr_n, <i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975>
2251 ret <8 x i32> %and.i
2252 }
2254 define <8 x i32> @bic_shifted_knownbits3(<8 x i16> %v) {
2255 ; CHECK-SD-LABEL: bic_shifted_knownbits3:
2256 ; CHECK-SD: // %bb.0:
2257 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2258 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2259 ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
2260 ; CHECK-SD-NEXT: ret
2261 ;
2262 ; CHECK-GI-LABEL: bic_shifted_knownbits3:
2263 ; CHECK-GI: // %bb.0:
2264 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2265 ; CHECK-GI-NEXT: and v1.16b, v0.16b, v1.16b
2266 ; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
2267 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
2268 ; CHECK-GI-NEXT: ret
2269 %a = and <8 x i16> %v, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
2270 %and.i = zext <8 x i16> %a to <8 x i32>
2271 ret <8 x i32> %and.i
2272 }
2275 define <8 x i32> @bic_shifted_knownbits4(<8 x i32> %v) {
2276 ; CHECK-SD-LABEL: bic_shifted_knownbits4:
2277 ; CHECK-SD: // %bb.0: // %entry
2278 ; CHECK-SD-NEXT: shl v1.4s, v1.4s, #8
2279 ; CHECK-SD-NEXT: shl v0.4s, v0.4s, #8
2280 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
2281 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2282 ; CHECK-SD-NEXT: ret
2283 ;
2284 ; CHECK-GI-LABEL: bic_shifted_knownbits4:
2285 ; CHECK-GI: // %bb.0: // %entry
2286 ; CHECK-GI-NEXT: movi v2.2d, #0xffff0000ffff0000
2287 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #8
2288 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #8
2289 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
2290 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
2291 ; CHECK-GI-NEXT: ret
2292 entry:
2293 %vshr_n = shl <8 x i32> %v, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
2294 %and.i = and <8 x i32> %vshr_n, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
2295 ret <8 x i32> %and.i
2296 }
2298 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
2299 ; CHECK-SD-LABEL: orr8imm2s_lsl0:
2300 ; CHECK-SD: // %bb.0:
2301 ; CHECK-SD-NEXT: orr v0.2s, #255
2302 ; CHECK-SD-NEXT: ret
2303 ;
2304 ; CHECK-GI-LABEL: orr8imm2s_lsl0:
2305 ; CHECK-GI: // %bb.0:
2306 ; CHECK-GI-NEXT: adrp x8, .LCPI148_0
2307 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI148_0]
2308 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2309 ; CHECK-GI-NEXT: ret
2310 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2311 ret <8 x i8> %tmp1
2312 }
2314 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
2315 ; CHECK-SD-LABEL: orr8imm2s_lsl8:
2316 ; CHECK-SD: // %bb.0:
2317 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2318 ; CHECK-SD-NEXT: ret
2319 ;
2320 ; CHECK-GI-LABEL: orr8imm2s_lsl8:
2321 ; CHECK-GI: // %bb.0:
2322 ; CHECK-GI-NEXT: adrp x8, .LCPI149_0
2323 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]
2324 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2325 ; CHECK-GI-NEXT: ret
2326 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2327 ret <8 x i8> %tmp1
2328 }
2330 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
2331 ; CHECK-SD-LABEL: orr8imm2s_lsl16:
2332 ; CHECK-SD: // %bb.0:
2333 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2334 ; CHECK-SD-NEXT: ret
2335 ;
2336 ; CHECK-GI-LABEL: orr8imm2s_lsl16:
2337 ; CHECK-GI: // %bb.0:
2338 ; CHECK-GI-NEXT: adrp x8, .LCPI150_0
2339 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI150_0]
2340 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2341 ; CHECK-GI-NEXT: ret
2342 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2343 ret <8 x i8> %tmp1
2344 }
2346 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
2347 ; CHECK-SD-LABEL: orr8imm2s_lsl24:
2348 ; CHECK-SD: // %bb.0:
2349 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2350 ; CHECK-SD-NEXT: ret
2351 ;
2352 ; CHECK-GI-LABEL: orr8imm2s_lsl24:
2353 ; CHECK-GI: // %bb.0:
2354 ; CHECK-GI-NEXT: adrp x8, .LCPI151_0
2355 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]
2356 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2357 ; CHECK-GI-NEXT: ret
2358 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2359 ret <8 x i8> %tmp1
2360 }
2362 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
2363 ; CHECK-SD-LABEL: orr16imm2s_lsl0:
2364 ; CHECK-SD: // %bb.0:
2365 ; CHECK-SD-NEXT: orr v0.2s, #255
2366 ; CHECK-SD-NEXT: ret
2367 ;
2368 ; CHECK-GI-LABEL: orr16imm2s_lsl0:
2369 ; CHECK-GI: // %bb.0:
2370 ; CHECK-GI-NEXT: adrp x8, .LCPI152_0
2371 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI152_0]
2372 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2373 ; CHECK-GI-NEXT: ret
2374 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
2375 ret <4 x i16> %tmp1
2376 }
2378 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
2379 ; CHECK-SD-LABEL: orr16imm2s_lsl8:
2380 ; CHECK-SD: // %bb.0:
2381 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2382 ; CHECK-SD-NEXT: ret
2383 ;
2384 ; CHECK-GI-LABEL: orr16imm2s_lsl8:
2385 ; CHECK-GI: // %bb.0:
2386 ; CHECK-GI-NEXT: adrp x8, .LCPI153_0
2387 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI153_0]
2388 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2389 ; CHECK-GI-NEXT: ret
2390 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
2391 ret <4 x i16> %tmp1
2392 }
2394 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
2395 ; CHECK-SD-LABEL: orr16imm2s_lsl16:
2396 ; CHECK-SD: // %bb.0:
2397 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2398 ; CHECK-SD-NEXT: ret
2399 ;
2400 ; CHECK-GI-LABEL: orr16imm2s_lsl16:
2401 ; CHECK-GI: // %bb.0:
2402 ; CHECK-GI-NEXT: adrp x8, .LCPI154_0
2403 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI154_0]
2404 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2405 ; CHECK-GI-NEXT: ret
2406 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
2407 ret <4 x i16> %tmp1
2408 }
2410 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
2411 ; CHECK-SD-LABEL: orr16imm2s_lsl24:
2412 ; CHECK-SD: // %bb.0:
2413 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2414 ; CHECK-SD-NEXT: ret
2415 ;
2416 ; CHECK-GI-LABEL: orr16imm2s_lsl24:
2417 ; CHECK-GI: // %bb.0:
2418 ; CHECK-GI-NEXT: adrp x8, .LCPI155_0
2419 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI155_0]
2420 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2421 ; CHECK-GI-NEXT: ret
2422 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
2423 ret <4 x i16> %tmp1
2424 }
2426 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
2427 ; CHECK-SD-LABEL: orr64imm2s_lsl0:
2428 ; CHECK-SD: // %bb.0:
2429 ; CHECK-SD-NEXT: orr v0.2s, #255
2430 ; CHECK-SD-NEXT: ret
2431 ;
2432 ; CHECK-GI-LABEL: orr64imm2s_lsl0:
2433 ; CHECK-GI: // %bb.0:
2434 ; CHECK-GI-NEXT: fmov x8, d0
2435 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff
2436 ; CHECK-GI-NEXT: fmov d0, x8
2437 ; CHECK-GI-NEXT: ret
2438 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
2439 ret <1 x i64> %tmp1
2440 }
2442 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
2443 ; CHECK-SD-LABEL: orr64imm2s_lsl8:
2444 ; CHECK-SD: // %bb.0:
2445 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2446 ; CHECK-SD-NEXT: ret
2447 ;
2448 ; CHECK-GI-LABEL: orr64imm2s_lsl8:
2449 ; CHECK-GI: // %bb.0:
2450 ; CHECK-GI-NEXT: fmov x8, d0
2451 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff00
2452 ; CHECK-GI-NEXT: fmov d0, x8
2453 ; CHECK-GI-NEXT: ret
2454 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
2455 ret <1 x i64> %tmp1
2456 }
2458 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
2459 ; CHECK-SD-LABEL: orr64imm2s_lsl16:
2460 ; CHECK-SD: // %bb.0:
2461 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2462 ; CHECK-SD-NEXT: ret
2463 ;
2464 ; CHECK-GI-LABEL: orr64imm2s_lsl16:
2465 ; CHECK-GI: // %bb.0:
2466 ; CHECK-GI-NEXT: fmov x8, d0
2467 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff0000
2468 ; CHECK-GI-NEXT: fmov d0, x8
2469 ; CHECK-GI-NEXT: ret
2470 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
2471 ret <1 x i64> %tmp1
2472 }
2474 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
2475 ; CHECK-SD-LABEL: orr64imm2s_lsl24:
2476 ; CHECK-SD: // %bb.0:
2477 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2478 ; CHECK-SD-NEXT: ret
2479 ;
2480 ; CHECK-GI-LABEL: orr64imm2s_lsl24:
2481 ; CHECK-GI: // %bb.0:
2482 ; CHECK-GI-NEXT: fmov x8, d0
2483 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff000000
2484 ; CHECK-GI-NEXT: fmov d0, x8
2485 ; CHECK-GI-NEXT: ret
2486 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
2487 ret <1 x i64> %tmp1
2488 }
2490 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
2491 ; CHECK-SD-LABEL: orr8imm4s_lsl0:
2492 ; CHECK-SD: // %bb.0:
2493 ; CHECK-SD-NEXT: orr v0.4s, #255
2494 ; CHECK-SD-NEXT: ret
2495 ;
2496 ; CHECK-GI-LABEL: orr8imm4s_lsl0:
2497 ; CHECK-GI: // %bb.0:
2498 ; CHECK-GI-NEXT: adrp x8, .LCPI160_0
2499 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI160_0]
2500 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2501 ; CHECK-GI-NEXT: ret
2502 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2503 ret <16 x i8> %tmp1
2504 }
2506 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
2507 ; CHECK-SD-LABEL: orr8imm4s_lsl8:
2508 ; CHECK-SD: // %bb.0:
2509 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2510 ; CHECK-SD-NEXT: ret
2511 ;
2512 ; CHECK-GI-LABEL: orr8imm4s_lsl8:
2513 ; CHECK-GI: // %bb.0:
2514 ; CHECK-GI-NEXT: adrp x8, .LCPI161_0
2515 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI161_0]
2516 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2517 ; CHECK-GI-NEXT: ret
2518 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2519 ret <16 x i8> %tmp1
2520 }
2522 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
2523 ; CHECK-SD-LABEL: orr8imm4s_lsl16:
2524 ; CHECK-SD: // %bb.0:
2525 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2526 ; CHECK-SD-NEXT: ret
2527 ;
2528 ; CHECK-GI-LABEL: orr8imm4s_lsl16:
2529 ; CHECK-GI: // %bb.0:
2530 ; CHECK-GI-NEXT: adrp x8, .LCPI162_0
2531 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0]
2532 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2533 ; CHECK-GI-NEXT: ret
2534 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2535 ret <16 x i8> %tmp1
2536 }
2538 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
2539 ; CHECK-SD-LABEL: orr8imm4s_lsl24:
2540 ; CHECK-SD: // %bb.0:
2541 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2542 ; CHECK-SD-NEXT: ret
2543 ;
2544 ; CHECK-GI-LABEL: orr8imm4s_lsl24:
2545 ; CHECK-GI: // %bb.0:
2546 ; CHECK-GI-NEXT: adrp x8, .LCPI163_0
2547 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI163_0]
2548 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2549 ; CHECK-GI-NEXT: ret
2550 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2551 ret <16 x i8> %tmp1
2552 }
2554 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
2555 ; CHECK-SD-LABEL: orr16imm4s_lsl0:
2556 ; CHECK-SD: // %bb.0:
2557 ; CHECK-SD-NEXT: orr v0.4s, #255
2558 ; CHECK-SD-NEXT: ret
2559 ;
2560 ; CHECK-GI-LABEL: orr16imm4s_lsl0:
2561 ; CHECK-GI: // %bb.0:
2562 ; CHECK-GI-NEXT: adrp x8, .LCPI164_0
2563 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI164_0]
2564 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2565 ; CHECK-GI-NEXT: ret
2566 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
2567 ret <8 x i16> %tmp1
2568 }
2570 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
2571 ; CHECK-SD-LABEL: orr16imm4s_lsl8:
2572 ; CHECK-SD: // %bb.0:
2573 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2574 ; CHECK-SD-NEXT: ret
2575 ;
2576 ; CHECK-GI-LABEL: orr16imm4s_lsl8:
2577 ; CHECK-GI: // %bb.0:
2578 ; CHECK-GI-NEXT: adrp x8, .LCPI165_0
2579 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI165_0]
2580 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2581 ; CHECK-GI-NEXT: ret
2582 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
2583 ret <8 x i16> %tmp1
2584 }
2586 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
2587 ; CHECK-SD-LABEL: orr16imm4s_lsl16:
2588 ; CHECK-SD: // %bb.0:
2589 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2590 ; CHECK-SD-NEXT: ret
2591 ;
2592 ; CHECK-GI-LABEL: orr16imm4s_lsl16:
2593 ; CHECK-GI: // %bb.0:
2594 ; CHECK-GI-NEXT: adrp x8, .LCPI166_0
2595 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI166_0]
2596 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2597 ; CHECK-GI-NEXT: ret
2598 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
2599 ret <8 x i16> %tmp1
2600 }
2602 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
2603 ; CHECK-SD-LABEL: orr16imm4s_lsl24:
2604 ; CHECK-SD: // %bb.0:
2605 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2606 ; CHECK-SD-NEXT: ret
2607 ;
2608 ; CHECK-GI-LABEL: orr16imm4s_lsl24:
2609 ; CHECK-GI: // %bb.0:
2610 ; CHECK-GI-NEXT: adrp x8, .LCPI167_0
2611 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]
2612 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2613 ; CHECK-GI-NEXT: ret
2614 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
2615 ret <8 x i16> %tmp1
2616 }
2618 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
2619 ; CHECK-SD-LABEL: orr64imm4s_lsl0:
2620 ; CHECK-SD: // %bb.0:
2621 ; CHECK-SD-NEXT: orr v0.4s, #255
2622 ; CHECK-SD-NEXT: ret
2623 ;
2624 ; CHECK-GI-LABEL: orr64imm4s_lsl0:
2625 ; CHECK-GI: // %bb.0:
2626 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
2627 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2628 ; CHECK-GI-NEXT: ret
2629 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
2630 ret <2 x i64> %tmp1
2631 }
2633 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
2634 ; CHECK-SD-LABEL: orr64imm4s_lsl8:
2635 ; CHECK-SD: // %bb.0:
2636 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2637 ; CHECK-SD-NEXT: ret
2638 ;
2639 ; CHECK-GI-LABEL: orr64imm4s_lsl8:
2640 ; CHECK-GI: // %bb.0:
2641 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
2642 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2643 ; CHECK-GI-NEXT: ret
2644 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
2645 ret <2 x i64> %tmp1
2646 }
2648 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
2649 ; CHECK-SD-LABEL: orr64imm4s_lsl16:
2650 ; CHECK-SD: // %bb.0:
2651 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2652 ; CHECK-SD-NEXT: ret
2653 ;
2654 ; CHECK-GI-LABEL: orr64imm4s_lsl16:
2655 ; CHECK-GI: // %bb.0:
2656 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
2657 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2658 ; CHECK-GI-NEXT: ret
2659 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
2660 ret <2 x i64> %tmp1
2661 }
2663 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
2664 ; CHECK-SD-LABEL: orr64imm4s_lsl24:
2665 ; CHECK-SD: // %bb.0:
2666 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2667 ; CHECK-SD-NEXT: ret
2668 ;
2669 ; CHECK-GI-LABEL: orr64imm4s_lsl24:
2670 ; CHECK-GI: // %bb.0:
2671 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
2672 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2673 ; CHECK-GI-NEXT: ret
2674 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
2675 ret <2 x i64> %tmp1
2676 }
2678 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
2679 ; CHECK-SD-LABEL: orr8imm4h_lsl0:
2680 ; CHECK-SD: // %bb.0:
2681 ; CHECK-SD-NEXT: orr v0.4h, #255
2682 ; CHECK-SD-NEXT: ret
2683 ;
2684 ; CHECK-GI-LABEL: orr8imm4h_lsl0:
2685 ; CHECK-GI: // %bb.0:
2686 ; CHECK-GI-NEXT: adrp x8, .LCPI172_0
2687 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI172_0]
2688 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2689 ; CHECK-GI-NEXT: ret
2690 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2691 ret <8 x i8> %tmp1
2692 }
2694 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
2695 ; CHECK-SD-LABEL: orr8imm4h_lsl8:
2696 ; CHECK-SD: // %bb.0:
2697 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2698 ; CHECK-SD-NEXT: ret
2699 ;
2700 ; CHECK-GI-LABEL: orr8imm4h_lsl8:
2701 ; CHECK-GI: // %bb.0:
2702 ; CHECK-GI-NEXT: adrp x8, .LCPI173_0
2703 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI173_0]
2704 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2705 ; CHECK-GI-NEXT: ret
2706 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2707 ret <8 x i8> %tmp1
2708 }
2710 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
2711 ; CHECK-SD-LABEL: orr16imm4h_lsl0:
2712 ; CHECK-SD: // %bb.0:
2713 ; CHECK-SD-NEXT: orr v0.4h, #255
2714 ; CHECK-SD-NEXT: ret
2715 ;
2716 ; CHECK-GI-LABEL: orr16imm4h_lsl0:
2717 ; CHECK-GI: // %bb.0:
2718 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2719 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2720 ; CHECK-GI-NEXT: ret
2721 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
2722 ret <2 x i32> %tmp1
2723 }
2725 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
2726 ; CHECK-SD-LABEL: orr16imm4h_lsl8:
2727 ; CHECK-SD: // %bb.0:
2728 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2729 ; CHECK-SD-NEXT: ret
2730 ;
2731 ; CHECK-GI-LABEL: orr16imm4h_lsl8:
2732 ; CHECK-GI: // %bb.0:
2733 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2734 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2735 ; CHECK-GI-NEXT: ret
2736 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
2737 ret <2 x i32> %tmp1
2738 }
2740 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
2741 ; CHECK-SD-LABEL: orr64imm4h_lsl0:
2742 ; CHECK-SD: // %bb.0:
2743 ; CHECK-SD-NEXT: orr v0.4h, #255
2744 ; CHECK-SD-NEXT: ret
2745 ;
2746 ; CHECK-GI-LABEL: orr64imm4h_lsl0:
2747 ; CHECK-GI: // %bb.0:
2748 ; CHECK-GI-NEXT: fmov x8, d0
2749 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff
2750 ; CHECK-GI-NEXT: fmov d0, x8
2751 ; CHECK-GI-NEXT: ret
2752 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
2753 ret <1 x i64> %tmp1
2754 }
2756 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
2757 ; CHECK-SD-LABEL: orr64imm4h_lsl8:
2758 ; CHECK-SD: // %bb.0:
2759 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2760 ; CHECK-SD-NEXT: ret
2761 ;
2762 ; CHECK-GI-LABEL: orr64imm4h_lsl8:
2763 ; CHECK-GI: // %bb.0:
2764 ; CHECK-GI-NEXT: fmov x8, d0
2765 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff00
2766 ; CHECK-GI-NEXT: fmov d0, x8
2767 ; CHECK-GI-NEXT: ret
2768 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
2769 ret <1 x i64> %tmp1
2770 }
2772 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
2773 ; CHECK-SD-LABEL: orr8imm8h_lsl0:
2774 ; CHECK-SD: // %bb.0:
2775 ; CHECK-SD-NEXT: orr v0.8h, #255
2776 ; CHECK-SD-NEXT: ret
2777 ;
2778 ; CHECK-GI-LABEL: orr8imm8h_lsl0:
2779 ; CHECK-GI: // %bb.0:
2780 ; CHECK-GI-NEXT: adrp x8, .LCPI178_0
2781 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI178_0]
2782 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2783 ; CHECK-GI-NEXT: ret
2784 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2785 ret <16 x i8> %tmp1
2786 }
2788 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
2789 ; CHECK-SD-LABEL: orr8imm8h_lsl8:
2790 ; CHECK-SD: // %bb.0:
2791 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2792 ; CHECK-SD-NEXT: ret
2793 ;
2794 ; CHECK-GI-LABEL: orr8imm8h_lsl8:
2795 ; CHECK-GI: // %bb.0:
2796 ; CHECK-GI-NEXT: adrp x8, .LCPI179_0
2797 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI179_0]
2798 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2799 ; CHECK-GI-NEXT: ret
2800 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2801 ret <16 x i8> %tmp1
2802 }
2804 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
2805 ; CHECK-SD-LABEL: orr16imm8h_lsl0:
2806 ; CHECK-SD: // %bb.0:
2807 ; CHECK-SD-NEXT: orr v0.8h, #255
2808 ; CHECK-SD-NEXT: ret
2809 ;
2810 ; CHECK-GI-LABEL: orr16imm8h_lsl0:
2811 ; CHECK-GI: // %bb.0:
2812 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2813 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2814 ; CHECK-GI-NEXT: ret
2815 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2816 ret <4 x i32> %tmp1
2817 }
2819 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
2820 ; CHECK-SD-LABEL: orr16imm8h_lsl8:
2821 ; CHECK-SD: // %bb.0:
2822 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2823 ; CHECK-SD-NEXT: ret
2824 ;
2825 ; CHECK-GI-LABEL: orr16imm8h_lsl8:
2826 ; CHECK-GI: // %bb.0:
2827 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2828 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2829 ; CHECK-GI-NEXT: ret
2830 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2831 ret <4 x i32> %tmp1
2832 }
2834 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
2835 ; CHECK-SD-LABEL: orr64imm8h_lsl0:
2836 ; CHECK-SD: // %bb.0:
2837 ; CHECK-SD-NEXT: orr v0.8h, #255
2838 ; CHECK-SD-NEXT: ret
2839 ;
2840 ; CHECK-GI-LABEL: orr64imm8h_lsl0:
2841 ; CHECK-GI: // %bb.0:
2842 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2843 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2844 ; CHECK-GI-NEXT: ret
2845 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2846 ret <2 x i64> %tmp1
2847 }
2849 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
2850 ; CHECK-SD-LABEL: orr64imm8h_lsl8:
2851 ; CHECK-SD: // %bb.0:
2852 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2853 ; CHECK-SD-NEXT: ret
2854 ;
2855 ; CHECK-GI-LABEL: orr64imm8h_lsl8:
2856 ; CHECK-GI: // %bb.0:
2857 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2858 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2859 ; CHECK-GI-NEXT: ret
2860 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2861 ret <2 x i64> %tmp1
2862 }