| blob | fa88024315211b849dcc8c9dea43f667efd8b5bc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM
4 declare i4 @llvm.umul.fix.sat.i4 (i4, i4, i32)
5 declare i32 @llvm.umul.fix.sat.i32 (i32, i32, i32)
6 declare i64 @llvm.umul.fix.sat.i64 (i64, i64, i32)
8 define i32 @func(i32 %x, i32 %y) nounwind {
9 ; ARM-LABEL: func:
10 ; ARM: @ %bb.0:
11 ; ARM-NEXT: .save {r4, lr}
12 ; ARM-NEXT: push {r4, lr}
13 ; ARM-NEXT: mov r2, r1
14 ; ARM-NEXT: movs r4, #0
15 ; ARM-NEXT: mov r1, r4
16 ; ARM-NEXT: mov r3, r4
17 ; ARM-NEXT: bl __aeabi_lmul
18 ; ARM-NEXT: cmp r1, #3
19 ; ARM-NEXT: bhi .LBB0_2
20 ; ARM-NEXT: @ %bb.1:
21 ; ARM-NEXT: lsrs r0, r0, #2
22 ; ARM-NEXT: lsls r1, r1, #30
23 ; ARM-NEXT: adds r0, r1, r0
24 ; ARM-NEXT: pop {r4, pc}
25 ; ARM-NEXT: .LBB0_2:
26 ; ARM-NEXT: mvns r0, r4
27 ; ARM-NEXT: pop {r4, pc}
28 %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 2)
29 ret i32 %tmp
30 }
32 define i64 @func2(i64 %x, i64 %y) nounwind {
33 ; ARM-LABEL: func2:
34 ; ARM: @ %bb.0:
35 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
36 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
37 ; ARM-NEXT: .pad #28
38 ; ARM-NEXT: sub sp, #28
39 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
40 ; ARM-NEXT: mov r5, r1
41 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
42 ; ARM-NEXT: movs r4, #0
43 ; ARM-NEXT: mov r6, r0
44 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
45 ; ARM-NEXT: mov r1, r4
46 ; ARM-NEXT: mov r7, r2
47 ; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
48 ; ARM-NEXT: mov r3, r4
49 ; ARM-NEXT: bl __aeabi_lmul
50 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
51 ; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill
52 ; ARM-NEXT: mov r0, r5
53 ; ARM-NEXT: mov r1, r4
54 ; ARM-NEXT: mov r2, r7
55 ; ARM-NEXT: mov r3, r4
56 ; ARM-NEXT: bl __aeabi_lmul
57 ; ARM-NEXT: mov r5, r1
58 ; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
59 ; ARM-NEXT: adds r0, r0, r1
60 ; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
61 ; ARM-NEXT: adcs r5, r4
62 ; ARM-NEXT: mov r0, r6
63 ; ARM-NEXT: mov r1, r4
64 ; ARM-NEXT: ldr r7, [sp, #24] @ 4-byte Reload
65 ; ARM-NEXT: mov r2, r7
66 ; ARM-NEXT: mov r3, r4
67 ; ARM-NEXT: bl __aeabi_lmul
68 ; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
69 ; ARM-NEXT: adds r0, r0, r2
70 ; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
71 ; ARM-NEXT: adcs r1, r4
72 ; ARM-NEXT: adds r0, r5, r1
73 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
74 ; ARM-NEXT: mov r6, r4
75 ; ARM-NEXT: adcs r6, r4
76 ; ARM-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
77 ; ARM-NEXT: mov r0, r5
78 ; ARM-NEXT: mov r1, r4
79 ; ARM-NEXT: mov r2, r7
80 ; ARM-NEXT: mov r3, r4
81 ; ARM-NEXT: bl __aeabi_lmul
82 ; ARM-NEXT: mov r7, r1
83 ; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
84 ; ARM-NEXT: adds r0, r0, r1
85 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
86 ; ARM-NEXT: adcs r7, r6
87 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
88 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
89 ; ARM-NEXT: mov r2, r4
90 ; ARM-NEXT: mov r3, r4
91 ; ARM-NEXT: bl __aeabi_lmul
92 ; ARM-NEXT: mov r6, r0
93 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
94 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
95 ; ARM-NEXT: mov r1, r5
96 ; ARM-NEXT: mov r2, r4
97 ; ARM-NEXT: mov r3, r4
98 ; ARM-NEXT: bl __aeabi_lmul
99 ; ARM-NEXT: adds r0, r0, r6
100 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
101 ; ARM-NEXT: adcs r1, r2
102 ; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
103 ; ARM-NEXT: adds r2, r2, r0
104 ; ARM-NEXT: adcs r1, r7
105 ; ARM-NEXT: lsrs r3, r2, #2
106 ; ARM-NEXT: orrs r3, r1
107 ; ARM-NEXT: mvns r1, r4
108 ; ARM-NEXT: cmp r3, #0
109 ; ARM-NEXT: mov r0, r1
110 ; ARM-NEXT: beq .LBB1_3
111 ; ARM-NEXT: @ %bb.1:
112 ; ARM-NEXT: cmp r3, #0
113 ; ARM-NEXT: beq .LBB1_4
114 ; ARM-NEXT: .LBB1_2:
115 ; ARM-NEXT: add sp, #28
116 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
117 ; ARM-NEXT: .LBB1_3:
118 ; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
119 ; ARM-NEXT: lsls r0, r0, #30
120 ; ARM-NEXT: ldr r4, [sp] @ 4-byte Reload
121 ; ARM-NEXT: lsrs r4, r4, #2
122 ; ARM-NEXT: adds r0, r0, r4
123 ; ARM-NEXT: cmp r3, #0
124 ; ARM-NEXT: bne .LBB1_2
125 ; ARM-NEXT: .LBB1_4:
126 ; ARM-NEXT: lsls r1, r2, #30
127 ; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
128 ; ARM-NEXT: lsrs r2, r2, #2
129 ; ARM-NEXT: adds r1, r1, r2
130 ; ARM-NEXT: add sp, #28
131 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
132 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 2)
133 ret i64 %tmp
134 }
136 define i4 @func3(i4 %x, i4 %y) nounwind {
137 ; ARM-LABEL: func3:
138 ; ARM: @ %bb.0:
139 ; ARM-NEXT: .save {r4, lr}
140 ; ARM-NEXT: push {r4, lr}
141 ; ARM-NEXT: movs r2, #15
142 ; ARM-NEXT: ands r2, r1
143 ; ARM-NEXT: lsls r0, r0, #28
144 ; ARM-NEXT: movs r4, #0
145 ; ARM-NEXT: mov r1, r4
146 ; ARM-NEXT: mov r3, r4
147 ; ARM-NEXT: bl __aeabi_lmul
148 ; ARM-NEXT: cmp r1, #3
149 ; ARM-NEXT: bhi .LBB2_2
150 ; ARM-NEXT: @ %bb.1:
151 ; ARM-NEXT: lsrs r0, r0, #2
152 ; ARM-NEXT: lsls r1, r1, #30
153 ; ARM-NEXT: adds r0, r1, r0
154 ; ARM-NEXT: lsrs r0, r0, #28
155 ; ARM-NEXT: pop {r4, pc}
156 ; ARM-NEXT: .LBB2_2:
157 ; ARM-NEXT: mvns r0, r4
158 ; ARM-NEXT: lsrs r0, r0, #28
159 ; ARM-NEXT: pop {r4, pc}
160 %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 2)
161 ret i4 %tmp
162 }
164 ;; These result in regular integer multiplication with a saturation check.
165 define i32 @func4(i32 %x, i32 %y) nounwind {
166 ; ARM-LABEL: func4:
167 ; ARM: @ %bb.0:
168 ; ARM-NEXT: .save {r4, lr}
169 ; ARM-NEXT: push {r4, lr}
170 ; ARM-NEXT: mov r2, r1
171 ; ARM-NEXT: movs r4, #0
172 ; ARM-NEXT: mov r1, r4
173 ; ARM-NEXT: mov r3, r4
174 ; ARM-NEXT: bl __aeabi_lmul
175 ; ARM-NEXT: cmp r1, #0
176 ; ARM-NEXT: bls .LBB3_2
177 ; ARM-NEXT: @ %bb.1:
178 ; ARM-NEXT: mvns r0, r4
179 ; ARM-NEXT: .LBB3_2:
180 ; ARM-NEXT: pop {r4, pc}
181 %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 0)
182 ret i32 %tmp
183 }
185 define i64 @func5(i64 %x, i64 %y) {
186 ; ARM-LABEL: func5:
187 ; ARM: @ %bb.0:
188 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
189 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
190 ; ARM-NEXT: .pad #12
191 ; ARM-NEXT: sub sp, #12
192 ; ARM-NEXT: mov r6, r3
193 ; ARM-NEXT: str r2, [sp, #8] @ 4-byte Spill
194 ; ARM-NEXT: mov r4, r1
195 ; ARM-NEXT: mov r2, r0
196 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
197 ; ARM-NEXT: movs r5, #0
198 ; ARM-NEXT: mov r0, r3
199 ; ARM-NEXT: mov r1, r5
200 ; ARM-NEXT: mov r3, r5
201 ; ARM-NEXT: bl __aeabi_lmul
202 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
203 ; ARM-NEXT: mov r7, r1
204 ; ARM-NEXT: subs r0, r1, #1
205 ; ARM-NEXT: sbcs r7, r0
206 ; ARM-NEXT: mov r0, r4
207 ; ARM-NEXT: mov r1, r5
208 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
209 ; ARM-NEXT: mov r3, r5
210 ; ARM-NEXT: bl __aeabi_lmul
211 ; ARM-NEXT: subs r2, r1, #1
212 ; ARM-NEXT: sbcs r1, r2
213 ; ARM-NEXT: subs r2, r6, #1
214 ; ARM-NEXT: sbcs r6, r2
215 ; ARM-NEXT: subs r2, r4, #1
216 ; ARM-NEXT: sbcs r4, r2
217 ; ARM-NEXT: ands r4, r6
218 ; ARM-NEXT: orrs r4, r1
219 ; ARM-NEXT: orrs r4, r7
220 ; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
221 ; ARM-NEXT: adds r6, r0, r1
222 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
223 ; ARM-NEXT: mov r1, r5
224 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
225 ; ARM-NEXT: mov r3, r5
226 ; ARM-NEXT: bl __aeabi_lmul
227 ; ARM-NEXT: adds r3, r1, r6
228 ; ARM-NEXT: mov r6, r5
229 ; ARM-NEXT: adcs r6, r5
230 ; ARM-NEXT: orrs r6, r4
231 ; ARM-NEXT: mvns r1, r5
232 ; ARM-NEXT: cmp r6, #0
233 ; ARM-NEXT: mov r2, r1
234 ; ARM-NEXT: bne .LBB4_2
235 ; ARM-NEXT: @ %bb.1:
236 ; ARM-NEXT: mov r2, r0
237 ; ARM-NEXT: .LBB4_2:
238 ; ARM-NEXT: cmp r6, #0
239 ; ARM-NEXT: bne .LBB4_4
240 ; ARM-NEXT: @ %bb.3:
241 ; ARM-NEXT: mov r1, r3
242 ; ARM-NEXT: .LBB4_4:
243 ; ARM-NEXT: mov r0, r2
244 ; ARM-NEXT: add sp, #12
245 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
246 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 0)
247 ret i64 %tmp
248 }
250 define i4 @func6(i4 %x, i4 %y) nounwind {
251 ; ARM-LABEL: func6:
252 ; ARM: @ %bb.0:
253 ; ARM-NEXT: .save {r4, lr}
254 ; ARM-NEXT: push {r4, lr}
255 ; ARM-NEXT: movs r2, #15
256 ; ARM-NEXT: ands r2, r1
257 ; ARM-NEXT: lsls r0, r0, #28
258 ; ARM-NEXT: movs r4, #0
259 ; ARM-NEXT: mov r1, r4
260 ; ARM-NEXT: mov r3, r4
261 ; ARM-NEXT: bl __aeabi_lmul
262 ; ARM-NEXT: cmp r1, #0
263 ; ARM-NEXT: bls .LBB5_2
264 ; ARM-NEXT: @ %bb.1:
265 ; ARM-NEXT: mvns r0, r4
266 ; ARM-NEXT: .LBB5_2:
267 ; ARM-NEXT: lsrs r0, r0, #28
268 ; ARM-NEXT: pop {r4, pc}
269 %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 0)
270 ret i4 %tmp
271 }
273 define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
274 ; ARM-LABEL: vec2:
275 ; ARM: @ %bb.0:
276 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
277 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
278 ; ARM-NEXT: .pad #12
279 ; ARM-NEXT: sub sp, #12
280 ; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
281 ; ARM-NEXT: mov r7, r2
282 ; ARM-NEXT: mov r5, r1
283 ; ARM-NEXT: ldr r2, [sp, #32]
284 ; ARM-NEXT: movs r6, #0
285 ; ARM-NEXT: mov r1, r6
286 ; ARM-NEXT: mov r3, r6
287 ; ARM-NEXT: bl __aeabi_lmul
288 ; ARM-NEXT: mvns r4, r6
289 ; ARM-NEXT: cmp r1, #0
290 ; ARM-NEXT: mov r1, r4
291 ; ARM-NEXT: bhi .LBB6_2
292 ; ARM-NEXT: @ %bb.1:
293 ; ARM-NEXT: mov r1, r0
294 ; ARM-NEXT: .LBB6_2:
295 ; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
296 ; ARM-NEXT: ldr r2, [sp, #36]
297 ; ARM-NEXT: mov r0, r5
298 ; ARM-NEXT: mov r1, r6
299 ; ARM-NEXT: mov r3, r6
300 ; ARM-NEXT: bl __aeabi_lmul
301 ; ARM-NEXT: cmp r1, #0
302 ; ARM-NEXT: mov r5, r4
303 ; ARM-NEXT: bhi .LBB6_4
304 ; ARM-NEXT: @ %bb.3:
305 ; ARM-NEXT: mov r5, r0
306 ; ARM-NEXT: .LBB6_4:
307 ; ARM-NEXT: ldr r2, [sp, #40]
308 ; ARM-NEXT: mov r0, r7
309 ; ARM-NEXT: mov r1, r6
310 ; ARM-NEXT: mov r3, r6
311 ; ARM-NEXT: bl __aeabi_lmul
312 ; ARM-NEXT: cmp r1, #0
313 ; ARM-NEXT: mov r7, r4
314 ; ARM-NEXT: bhi .LBB6_6
315 ; ARM-NEXT: @ %bb.5:
316 ; ARM-NEXT: mov r7, r0
317 ; ARM-NEXT: .LBB6_6:
318 ; ARM-NEXT: ldr r2, [sp, #44]
319 ; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
320 ; ARM-NEXT: mov r1, r6
321 ; ARM-NEXT: mov r3, r6
322 ; ARM-NEXT: bl __aeabi_lmul
323 ; ARM-NEXT: cmp r1, #0
324 ; ARM-NEXT: bhi .LBB6_8
325 ; ARM-NEXT: @ %bb.7:
326 ; ARM-NEXT: mov r4, r0
327 ; ARM-NEXT: .LBB6_8:
328 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
329 ; ARM-NEXT: mov r1, r5
330 ; ARM-NEXT: mov r2, r7
331 ; ARM-NEXT: mov r3, r4
332 ; ARM-NEXT: add sp, #12
333 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
334 %tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
335 ret <4 x i32> %tmp
336 }
338 define i64 @func7(i64 %x, i64 %y) nounwind {
339 ; ARM-LABEL: func7:
340 ; ARM: @ %bb.0:
341 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
342 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
343 ; ARM-NEXT: .pad #28
344 ; ARM-NEXT: sub sp, #28
345 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
346 ; ARM-NEXT: mov r7, r2
347 ; ARM-NEXT: str r2, [sp, #20] @ 4-byte Spill
348 ; ARM-NEXT: mov r5, r1
349 ; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill
350 ; ARM-NEXT: movs r4, #0
351 ; ARM-NEXT: mov r6, r0
352 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
353 ; ARM-NEXT: mov r1, r4
354 ; ARM-NEXT: mov r3, r4
355 ; ARM-NEXT: bl __aeabi_lmul
356 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
357 ; ARM-NEXT: mov r0, r5
358 ; ARM-NEXT: mov r1, r4
359 ; ARM-NEXT: mov r2, r7
360 ; ARM-NEXT: mov r3, r4
361 ; ARM-NEXT: bl __aeabi_lmul
362 ; ARM-NEXT: mov r7, r1
363 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
364 ; ARM-NEXT: adds r5, r0, r1
365 ; ARM-NEXT: adcs r7, r4
366 ; ARM-NEXT: mov r0, r6
367 ; ARM-NEXT: mov r1, r4
368 ; ARM-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
369 ; ARM-NEXT: mov r2, r6
370 ; ARM-NEXT: mov r3, r4
371 ; ARM-NEXT: bl __aeabi_lmul
372 ; ARM-NEXT: adds r0, r0, r5
373 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
374 ; ARM-NEXT: adcs r1, r4
375 ; ARM-NEXT: adds r0, r7, r1
376 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
377 ; ARM-NEXT: mov r5, r4
378 ; ARM-NEXT: adcs r5, r4
379 ; ARM-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
380 ; ARM-NEXT: mov r0, r7
381 ; ARM-NEXT: mov r1, r4
382 ; ARM-NEXT: mov r2, r6
383 ; ARM-NEXT: mov r3, r4
384 ; ARM-NEXT: bl __aeabi_lmul
385 ; ARM-NEXT: mov r6, r1
386 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
387 ; ARM-NEXT: adds r0, r0, r1
388 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
389 ; ARM-NEXT: adcs r6, r5
390 ; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
391 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
392 ; ARM-NEXT: mov r2, r4
393 ; ARM-NEXT: mov r3, r4
394 ; ARM-NEXT: bl __aeabi_lmul
395 ; ARM-NEXT: mov r5, r0
396 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
397 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
398 ; ARM-NEXT: mov r1, r7
399 ; ARM-NEXT: mov r2, r4
400 ; ARM-NEXT: mov r3, r4
401 ; ARM-NEXT: bl __aeabi_lmul
402 ; ARM-NEXT: adds r0, r0, r5
403 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
404 ; ARM-NEXT: adcs r1, r2
405 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
406 ; ARM-NEXT: adds r3, r2, r0
407 ; ARM-NEXT: adcs r1, r6
408 ; ARM-NEXT: mvns r2, r4
409 ; ARM-NEXT: cmp r1, #0
410 ; ARM-NEXT: mov r0, r2
411 ; ARM-NEXT: bne .LBB7_2
412 ; ARM-NEXT: @ %bb.1:
413 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
414 ; ARM-NEXT: .LBB7_2:
415 ; ARM-NEXT: cmp r1, #0
416 ; ARM-NEXT: bne .LBB7_4
417 ; ARM-NEXT: @ %bb.3:
418 ; ARM-NEXT: mov r2, r3
419 ; ARM-NEXT: .LBB7_4:
420 ; ARM-NEXT: mov r1, r2
421 ; ARM-NEXT: add sp, #28
422 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
423 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 32)
424 ret i64 %tmp
425 }
427 define i64 @func8(i64 %x, i64 %y) nounwind {
428 ; ARM-LABEL: func8:
429 ; ARM: @ %bb.0:
430 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
431 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
432 ; ARM-NEXT: .pad #28
433 ; ARM-NEXT: sub sp, #28
434 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
435 ; ARM-NEXT: mov r7, r2
436 ; ARM-NEXT: str r2, [sp, #20] @ 4-byte Spill
437 ; ARM-NEXT: mov r5, r1
438 ; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill
439 ; ARM-NEXT: movs r4, #0
440 ; ARM-NEXT: mov r6, r0
441 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
442 ; ARM-NEXT: mov r1, r4
443 ; ARM-NEXT: mov r3, r4
444 ; ARM-NEXT: bl __aeabi_lmul
445 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
446 ; ARM-NEXT: mov r0, r5
447 ; ARM-NEXT: mov r1, r4
448 ; ARM-NEXT: mov r2, r7
449 ; ARM-NEXT: mov r3, r4
450 ; ARM-NEXT: bl __aeabi_lmul
451 ; ARM-NEXT: mov r7, r1
452 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
453 ; ARM-NEXT: adds r5, r0, r1
454 ; ARM-NEXT: adcs r7, r4
455 ; ARM-NEXT: mov r0, r6
456 ; ARM-NEXT: mov r1, r4
457 ; ARM-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
458 ; ARM-NEXT: mov r2, r6
459 ; ARM-NEXT: mov r3, r4
460 ; ARM-NEXT: bl __aeabi_lmul
461 ; ARM-NEXT: adds r0, r0, r5
462 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
463 ; ARM-NEXT: adcs r1, r4
464 ; ARM-NEXT: adds r0, r7, r1
465 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
466 ; ARM-NEXT: mov r5, r4
467 ; ARM-NEXT: adcs r5, r4
468 ; ARM-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
469 ; ARM-NEXT: mov r0, r7
470 ; ARM-NEXT: mov r1, r4
471 ; ARM-NEXT: mov r2, r6
472 ; ARM-NEXT: mov r3, r4
473 ; ARM-NEXT: bl __aeabi_lmul
474 ; ARM-NEXT: mov r6, r1
475 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
476 ; ARM-NEXT: adds r0, r0, r1
477 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
478 ; ARM-NEXT: adcs r6, r5
479 ; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
480 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
481 ; ARM-NEXT: mov r2, r4
482 ; ARM-NEXT: mov r3, r4
483 ; ARM-NEXT: bl __aeabi_lmul
484 ; ARM-NEXT: mov r5, r0
485 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
486 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
487 ; ARM-NEXT: mov r1, r7
488 ; ARM-NEXT: mov r2, r4
489 ; ARM-NEXT: mov r3, r4
490 ; ARM-NEXT: bl __aeabi_lmul
491 ; ARM-NEXT: adds r0, r0, r5
492 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
493 ; ARM-NEXT: adcs r1, r2
494 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
495 ; ARM-NEXT: adds r5, r2, r0
496 ; ARM-NEXT: adcs r1, r6
497 ; ARM-NEXT: lsrs r3, r5, #31
498 ; ARM-NEXT: mvns r2, r4
499 ; ARM-NEXT: cmp r3, #0
500 ; ARM-NEXT: mov r0, r2
501 ; ARM-NEXT: bne .LBB8_2
502 ; ARM-NEXT: @ %bb.1:
503 ; ARM-NEXT: lsls r0, r5, #1
504 ; ARM-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
505 ; ARM-NEXT: lsrs r4, r4, #31
506 ; ARM-NEXT: adds r0, r0, r4
507 ; ARM-NEXT: .LBB8_2:
508 ; ARM-NEXT: cmp r3, #0
509 ; ARM-NEXT: bne .LBB8_4
510 ; ARM-NEXT: @ %bb.3:
511 ; ARM-NEXT: lsls r1, r1, #1
512 ; ARM-NEXT: adds r2, r1, r3
513 ; ARM-NEXT: .LBB8_4:
514 ; ARM-NEXT: mov r1, r2
515 ; ARM-NEXT: add sp, #28
516 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
517 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 63)
518 ret i64 %tmp
519 }