llvm/lib/Target/RISCV/RISCVISelLowering.h

   1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
  15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
  16
  17 #include "RISCV.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "llvm/CodeGen/TargetLowering.h"
  21 #include "llvm/TargetParser/RISCVTargetParser.h"
  22 #include <optional>
  23
  24 namespace llvm {
  25 class InstructionCost;
  26 class RISCVSubtarget;
  27 struct RISCVRegisterInfo;
  28 namespace RISCVISD {
  29 enum NodeType : unsigned {
  30   FIRST_NUMBER = ISD::BUILTIN_OP_END,
  31   RET_GLUE,
  32   SRET_GLUE,
  33   MRET_GLUE,
  34   CALL,
  35   /// Select with condition operator - This selects between a true value and
  36   /// a false value (ops #3 and #4) based on the boolean result of comparing
  37   /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
  38   /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
  39   /// The lhs and rhs are XLenVT integers. The true and false values can be
  40   /// integer or floating point.
  41   SELECT_CC,
  42   BR_CC,
  43   BuildPairF64,
  44   SplitF64,
  45   TAIL,
  46
  47   // Add the Lo 12 bits from an address. Selected to ADDI.
  48   ADD_LO,
  49   // Get the Hi 20 bits from an address. Selected to LUI.
  50   HI,
  51
  52   // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
  53   LLA,
  54
  55   // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
  56   ADD_TPREL,
  57
  58   // Multiply high for signedxunsigned.
  59   MULHSU,
  60   // RV64I shifts, directly matching the semantics of the named RISC-V
  61   // instructions.
  62   SLLW,
  63   SRAW,
  64   SRLW,
  65   // 32-bit operations from RV64M that can't be simply matched with a pattern
  66   // at instruction selection time. These have undefined behavior for division
  67   // by 0 or overflow (divw) like their target independent counterparts.
  68   DIVW,
  69   DIVUW,
  70   REMUW,
  71   // RV64IB rotates, directly matching the semantics of the named RISC-V
  72   // instructions.
  73   ROLW,
  74   RORW,
  75   // RV64IZbb bit counting instructions directly matching the semantics of the
  76   // named RISC-V instructions.
  77   CLZW,
  78   CTZW,
  79
  80   // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
  81   ABSW,
  82
  83   // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
  84   // XLEN is the only legal integer width.
  85   //
  86   // FMV_H_X matches the semantics of the FMV.H.X.
  87   // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
  88   // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
  89   // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
  90   // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
  91   //
  92   // This is a more convenient semantic for producing dagcombines that remove
  93   // unnecessary GPR->FPR->GPR moves.
  94   FMV_H_X,
  95   FMV_X_ANYEXTH,
  96   FMV_X_SIGNEXTH,
  97   FMV_W_X_RV64,
  98   FMV_X_ANYEXTW_RV64,
  99   // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
 100   // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
 101   // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
 102   // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
 103   FCVT_X,
 104   FCVT_XU,
 105   // FP to 32 bit int conversions for RV64. These are used to keep track of the
 106   // result being sign extended to 64 bit. These saturate out of range inputs.
 107   // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
 108   // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
 109   FCVT_W_RV64,
 110   FCVT_WU_RV64,
 111
 112   FP_ROUND_BF16,
 113   FP_EXTEND_BF16,
 114
 115   // Rounds an FP value to its corresponding integer in the same FP format.
 116   // First operand is the value to round, the second operand is the largest
 117   // integer that can be represented exactly in the FP format. This will be
 118   // expanded into multiple instructions and basic blocks with a custom
 119   // inserter.
 120   FROUND,
 121
 122   FPCLASS,
 123
 124   // Floating point fmax and fmin matching the RISC-V instruction semantics.
 125   FMAX, FMIN,
 126
 127   // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
 128   // (returns (Lo, Hi)). It takes a chain operand.
 129   READ_CYCLE_WIDE,
 130   // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
 131   // XLenVT.
 132   BREV8,
 133   ORC_B,
 134   ZIP,
 135   UNZIP,
 136
 137   // Scalar cryptography
 138   CLMUL, CLMULH, CLMULR,
 139   SHA256SIG0, SHA256SIG1, SHA256SUM0, SHA256SUM1,
 140   SM4KS, SM4ED,
 141   SM3P0, SM3P1,
 142
 143   // Vector Extension
 144   FIRST_VL_VECTOR_OP,
 145   // VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
 146   // for the VL value to be used for the operation. The first operand is
 147   // passthru operand.
 148   VMV_V_V_VL = FIRST_VL_VECTOR_OP,
 149   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
 150   // for the VL value to be used for the operation. The first operand is
 151   // passthru operand.
 152   VMV_V_X_VL,
 153   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
 154   // for the VL value to be used for the operation. The first operand is
 155   // passthru operand.
 156   VFMV_V_F_VL,
 157   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
 158   // extended from the vector element size.
 159   VMV_X_S,
 160   // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
 161   VMV_S_X_VL,
 162   // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
 163   VFMV_S_F_VL,
 164   // Splats an 64-bit value that has been split into two i32 parts. This is
 165   // expanded late to two scalar stores and a stride 0 vector load.
 166   // The first operand is passthru operand.
 167   SPLAT_VECTOR_SPLIT_I64_VL,
 168   // Truncates a RVV integer vector by one power-of-two. Carries both an extra
 169   // mask and VL operand.
 170   TRUNCATE_VECTOR_VL,
 171   // Matches the semantics of vslideup/vslidedown. The first operand is the
 172   // pass-thru operand, the second is the source vector, the third is the XLenVT
 173   // index (either constant or non-constant), the fourth is the mask, the fifth
 174   // is the VL and the sixth is the policy.
 175   VSLIDEUP_VL,
 176   VSLIDEDOWN_VL,
 177   // Matches the semantics of vslide1up/slide1down. The first operand is
 178   // passthru operand, the second is source vector, third is the XLenVT scalar
 179   // value. The fourth and fifth operands are the mask and VL operands.
 180   VSLIDE1UP_VL,
 181   VSLIDE1DOWN_VL,
 182   // Matches the semantics of vfslide1up/vfslide1down. The first operand is
 183   // passthru operand, the second is source vector, third is a scalar value
 184   // whose type matches the element type of the vectors.  The fourth and fifth
 185   // operands are the mask and VL operands.
 186   VFSLIDE1UP_VL,
 187   VFSLIDE1DOWN_VL,
 188   // Matches the semantics of the vid.v instruction, with a mask and VL
 189   // operand.
 190   VID_VL,
 191   // Matches the semantics of the vfcnvt.rod function (Convert double-width
 192   // float to single-width float, rounding towards odd). Takes a double-width
 193   // float vector and produces a single-width float vector. Also has a mask and
 194   // VL operand.
 195   VFNCVT_ROD_VL,
 196   // These nodes match the semantics of the corresponding RVV vector reduction
 197   // instructions. They produce a vector result which is the reduction
 198   // performed over the second vector operand plus the first element of the
 199   // third vector operand. The first operand is the pass-thru operand. The
 200   // second operand is an unconstrained vector type, and the result, first, and
 201   // third operand's types are expected to be the corresponding full-width
 202   // LMUL=1 type for the second operand:
 203   //   nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
 204   //   nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
 205   // The different in types does introduce extra vsetvli instructions but
 206   // similarly it reduces the number of registers consumed per reduction.
 207   // Also has a mask and VL operand.
 208   VECREDUCE_ADD_VL,
 209   VECREDUCE_UMAX_VL,
 210   VECREDUCE_SMAX_VL,
 211   VECREDUCE_UMIN_VL,
 212   VECREDUCE_SMIN_VL,
 213   VECREDUCE_AND_VL,
 214   VECREDUCE_OR_VL,
 215   VECREDUCE_XOR_VL,
 216   VECREDUCE_FADD_VL,
 217   VECREDUCE_SEQ_FADD_VL,
 218   VECREDUCE_FMIN_VL,
 219   VECREDUCE_FMAX_VL,
 220
 221   // Vector binary ops with a merge as a third operand, a mask as a fourth
 222   // operand, and VL as a fifth operand.
 223   ADD_VL,
 224   AND_VL,
 225   MUL_VL,
 226   OR_VL,
 227   SDIV_VL,
 228   SHL_VL,
 229   SREM_VL,
 230   SRA_VL,
 231   SRL_VL,
 232   ROTL_VL,
 233   ROTR_VL,
 234   SUB_VL,
 235   UDIV_VL,
 236   UREM_VL,
 237   XOR_VL,
 238   SMIN_VL,
 239   SMAX_VL,
 240   UMIN_VL,
 241   UMAX_VL,
 242
 243   BITREVERSE_VL,
 244   BSWAP_VL,
 245   CTLZ_VL,
 246   CTTZ_VL,
 247   CTPOP_VL,
 248
 249   SADDSAT_VL,
 250   UADDSAT_VL,
 251   SSUBSAT_VL,
 252   USUBSAT_VL,
 253
 254   MULHS_VL,
 255   MULHU_VL,
 256   FADD_VL,
 257   FSUB_VL,
 258   FMUL_VL,
 259   FDIV_VL,
 260   VFMIN_VL,
 261   VFMAX_VL,
 262
 263   // Vector unary ops with a mask as a second operand and VL as a third operand.
 264   FNEG_VL,
 265   FABS_VL,
 266   FSQRT_VL,
 267   FCLASS_VL,
 268   FCOPYSIGN_VL, // Has a merge operand
 269   VFCVT_RTZ_X_F_VL,
 270   VFCVT_RTZ_XU_F_VL,
 271   VFCVT_X_F_VL,
 272   VFCVT_XU_F_VL,
 273   VFROUND_NOEXCEPT_VL,
 274   VFCVT_RM_X_F_VL,  // Has a rounding mode operand.
 275   VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
 276   SINT_TO_FP_VL,
 277   UINT_TO_FP_VL,
 278   VFCVT_RM_F_X_VL,  // Has a rounding mode operand.
 279   VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
 280   FP_ROUND_VL,
 281   FP_EXTEND_VL,
 282
 283   // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
 284   VFMADD_VL,
 285   VFNMADD_VL,
 286   VFMSUB_VL,
 287   VFNMSUB_VL,
 288
 289   // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth
 290   // operand.
 291   VFWMADD_VL,
 292   VFWNMADD_VL,
 293   VFWMSUB_VL,
 294   VFWNMSUB_VL,
 295
 296   // Widening instructions with a merge value a third operand, a mask as a
 297   // fourth operand, and VL as a fifth operand.
 298   VWMUL_VL,
 299   VWMULU_VL,
 300   VWMULSU_VL,
 301   VWADD_VL,
 302   VWADDU_VL,
 303   VWSUB_VL,
 304   VWSUBU_VL,
 305   VWADD_W_VL,
 306   VWADDU_W_VL,
 307   VWSUB_W_VL,
 308   VWSUBU_W_VL,
 309   VWSLL_VL,
 310
 311   VFWMUL_VL,
 312   VFWADD_VL,
 313   VFWSUB_VL,
 314   VFWADD_W_VL,
 315   VFWSUB_W_VL,
 316
 317   // Widening ternary operations with a mask as the fourth operand and VL as the
 318   // fifth operand.
 319   VWMACC_VL,
 320   VWMACCU_VL,
 321   VWMACCSU_VL,
 322
 323   // Narrowing logical shift right.
 324   // Operands are (source, shift, passthru, mask, vl)
 325   VNSRL_VL,
 326
 327   // Vector compare producing a mask. Fourth operand is input mask. Fifth
 328   // operand is VL.
 329   SETCC_VL,
 330
 331   // Vector select with an additional VL operand. This operation is unmasked.
 332   VSELECT_VL,
 333   // Vector select with operand #2 (the value when the condition is false) tied
 334   // to the destination and an additional VL operand. This operation is
 335   // unmasked.
 336   VP_MERGE_VL,
 337
 338   // Mask binary operators.
 339   VMAND_VL,
 340   VMOR_VL,
 341   VMXOR_VL,
 342
 343   // Set mask vector to all zeros or ones.
 344   VMCLR_VL,
 345   VMSET_VL,
 346
 347   // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
 348   // for passthru and VL. Operands are (src, index, mask, passthru, vl).
 349   VRGATHER_VX_VL,
 350   VRGATHER_VV_VL,
 351   VRGATHEREI16_VV_VL,
 352
 353   // Vector sign/zero extend with additional mask & VL operands.
 354   VSEXT_VL,
 355   VZEXT_VL,
 356
 357   //  vcpop.m with additional mask and VL operands.
 358   VCPOP_VL,
 359
 360   //  vfirst.m with additional mask and VL operands.
 361   VFIRST_VL,
 362
 363   LAST_VL_VECTOR_OP = VFIRST_VL,
 364
 365   // Read VLENB CSR
 366   READ_VLENB,
 367   // Reads value of CSR.
 368   // The first operand is a chain pointer. The second specifies address of the
 369   // required CSR. Two results are produced, the read value and the new chain
 370   // pointer.
 371   READ_CSR,
 372   // Write value to CSR.
 373   // The first operand is a chain pointer, the second specifies address of the
 374   // required CSR and the third is the value to write. The result is the new
 375   // chain pointer.
 376   WRITE_CSR,
 377   // Read and write value of CSR.
 378   // The first operand is a chain pointer, the second specifies address of the
 379   // required CSR and the third is the value to write. Two results are produced,
 380   // the value read before the modification and the new chain pointer.
 381   SWAP_CSR,
 382
 383   // Branchless select operations, matching the semantics of the instructions
 384   // defined in Zicond or XVentanaCondOps.
 385   CZERO_EQZ, // vt.maskc for XVentanaCondOps.
 386   CZERO_NEZ, // vt.maskcn for XVentanaCondOps.
 387
 388   // FP to 32 bit int conversions for RV64. These are used to keep track of the
 389   // result being sign extended to 64 bit. These saturate out of range inputs.
 390   STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
 391   STRICT_FCVT_WU_RV64,
 392   STRICT_FADD_VL,
 393   STRICT_FSUB_VL,
 394   STRICT_FMUL_VL,
 395   STRICT_FDIV_VL,
 396   STRICT_FSQRT_VL,
 397   STRICT_VFMADD_VL,
 398   STRICT_VFNMADD_VL,
 399   STRICT_VFMSUB_VL,
 400   STRICT_VFNMSUB_VL,
 401   STRICT_FP_ROUND_VL,
 402   STRICT_FP_EXTEND_VL,
 403   STRICT_VFNCVT_ROD_VL,
 404   STRICT_SINT_TO_FP_VL,
 405   STRICT_UINT_TO_FP_VL,
 406   STRICT_VFCVT_RM_X_F_VL,
 407   STRICT_VFCVT_RTZ_X_F_VL,
 408   STRICT_VFCVT_RTZ_XU_F_VL,
 409   STRICT_FSETCC_VL,
 410   STRICT_FSETCCS_VL,
 411   STRICT_VFROUND_NOEXCEPT_VL,
 412   LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
 413
 414   // WARNING: Do not add anything in the end unless you want the node to
 415   // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
 416   // opcodes will be thought as target memory ops!
 417
 418   TH_LWD = ISD::FIRST_TARGET_MEMORY_OPCODE,
 419   TH_LWUD,
 420   TH_LDD,
 421   TH_SWD,
 422   TH_SDD,
 423 };
 424 } // namespace RISCVISD
 425
 426 class RISCVTargetLowering : public TargetLowering {
 427   const RISCVSubtarget &Subtarget;
 428
 429 public:
 430   explicit RISCVTargetLowering(const TargetMachine &TM,
 431                                const RISCVSubtarget &STI);
 432
 433   const RISCVSubtarget &getSubtarget() const { return Subtarget; }
 434
 435   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
 436                           MachineFunction &MF,
 437                           unsigned Intrinsic) const override;
 438   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
 439                              unsigned AS,
 440                              Instruction *I = nullptr) const override;
 441   bool isLegalICmpImmediate(int64_t Imm) const override;
 442   bool isLegalAddImmediate(int64_t Imm) const override;
 443   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
 444   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
 445   bool isZExtFree(SDValue Val, EVT VT2) const override;
 446   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
 447   bool signExtendConstant(const ConstantInt *CI) const override;
 448   bool isCheapToSpeculateCttz(Type *Ty) const override;
 449   bool isCheapToSpeculateCtlz(Type *Ty) const override;
 450   bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
 451   bool hasAndNotCompare(SDValue Y) const override;
 452   bool hasBitTest(SDValue X, SDValue Y) const override;
 453   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
 454       SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
 455       unsigned OldShiftOpcode, unsigned NewShiftOpcode,
 456       SelectionDAG &DAG) const override;
 457   /// Return true if the (vector) instruction I will be lowered to an instruction
 458   /// with a scalar splat operand for the given Operand number.
 459   bool canSplatOperand(Instruction *I, int Operand) const;
 460   /// Return true if a vector instruction will lower to a target instruction
 461   /// able to splat the given operand.
 462   bool canSplatOperand(unsigned Opcode, int Operand) const;
 463   bool shouldSinkOperands(Instruction *I,
 464                           SmallVectorImpl<Use *> &Ops) const override;
 465   bool shouldScalarizeBinop(SDValue VecOp) const override;
 466   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 467   std::pair<int, bool> getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
 468   bool isFPImmLegal(const APFloat &Imm, EVT VT,
 469                     bool ForCodeSize) const override;
 470   bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
 471                                unsigned Index) const override;
 472
 473   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
 474
 475   bool preferScalarizeSplat(SDNode *N) const override;
 476
 477   bool softPromoteHalfType() const override { return true; }
 478
 479   /// Return the register type for a given MVT, ensuring vectors are treated
 480   /// as a series of gpr sized integers.
 481   MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
 482                                     EVT VT) const override;
 483
 484   /// Return the number of registers for a given MVT, ensuring vectors are
 485   /// treated as a series of gpr sized integers.
 486   unsigned getNumRegistersForCallingConv(LLVMContext &Context,
 487                                          CallingConv::ID CC,
 488                                          EVT VT) const override;
 489
 490   unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
 491                                                 CallingConv::ID CC, EVT VT,
 492                                                 EVT &IntermediateVT,
 493                                                 unsigned &NumIntermediates,
 494                                                 MVT &RegisterVT) const override;
 495
 496   bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
 497                                             EVT VT) const override;
 498
 499   /// Return true if the given shuffle mask can be codegen'd directly, or if it
 500   /// should be stack expanded.
 501   bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 502
 503   bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
 504     // If the pair to store is a mixture of float and int values, we will
 505     // save two bitwise instructions and one float-to-int instruction and
 506     // increase one store instruction. There is potentially a more
 507     // significant benefit because it avoids the float->int domain switch
 508     // for input value. So It is more likely a win.
 509     if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
 510         (LTy.isInteger() && HTy.isFloatingPoint()))
 511       return true;
 512     // If the pair only contains int values, we will save two bitwise
 513     // instructions and increase one store instruction (costing one more
 514     // store buffer). Since the benefit is more blurred we leave such a pair
 515     // out until we get testcase to prove it is a win.
 516     return false;
 517   }
 518
 519   bool
 520   shouldExpandBuildVectorWithShuffles(EVT VT,
 521                                       unsigned DefinedValues) const override;
 522
 523   /// Return the cost of LMUL for linear operations.
 524   InstructionCost getLMULCost(MVT VT) const;
 525
 526   InstructionCost getVRGatherVVCost(MVT VT) const;
 527   InstructionCost getVRGatherVICost(MVT VT) const;
 528   InstructionCost getVSlideCost(MVT VT) const;
 529
 530   // Provide custom lowering hooks for some operations.
 531   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 532   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
 533                           SelectionDAG &DAG) const override;
 534
 535   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 536
 537   bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
 538                                     const APInt &DemandedElts,
 539                                     TargetLoweringOpt &TLO) const override;
 540
 541   void computeKnownBitsForTargetNode(const SDValue Op,
 542                                      KnownBits &Known,
 543                                      const APInt &DemandedElts,
 544                                      const SelectionDAG &DAG,
 545                                      unsigned Depth) const override;
 546   unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
 547                                            const APInt &DemandedElts,
 548                                            const SelectionDAG &DAG,
 549                                            unsigned Depth) const override;
 550
 551   const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
 552
 553   // This method returns the name of a target specific DAG node.
 554   const char *getTargetNodeName(unsigned Opcode) const override;
 555
 556   MachineMemOperand::Flags
 557   getTargetMMOFlags(const Instruction &I) const override;
 558
 559   MachineMemOperand::Flags
 560   getTargetMMOFlags(const MemSDNode &Node) const override;
 561
 562   bool
 563   areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX,
 564                                       const MemSDNode &NodeY) const override;
 565
 566   ConstraintType getConstraintType(StringRef Constraint) const override;
 567
 568   InlineAsm::ConstraintCode
 569   getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
 570
 571   std::pair<unsigned, const TargetRegisterClass *>
 572   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 573                                StringRef Constraint, MVT VT) const override;
 574
 575   void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
 576                                     std::vector<SDValue> &Ops,
 577                                     SelectionDAG &DAG) const override;
 578
 579   MachineBasicBlock *
 580   EmitInstrWithCustomInserter(MachineInstr &MI,
 581                               MachineBasicBlock *BB) const override;
 582
 583   void AdjustInstrPostInstrSelection(MachineInstr &MI,
 584                                      SDNode *Node) const override;
 585
 586   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 587                          EVT VT) const override;
 588
 589   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
 590                             bool MathUsed) const override {
 591     if (VT == MVT::i8 || VT == MVT::i16)
 592       return false;
 593
 594     return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
 595   }
 596
 597   bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
 598                                     unsigned AddrSpace) const override {
 599     // If we can replace 4 or more scalar stores, there will be a reduction
 600     // in instructions even after we add a vector constant load.
 601     return NumElem >= 4;
 602   }
 603
 604   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 605     return VT.isScalarInteger();
 606   }
 607   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 608
 609   bool isCtpopFast(EVT VT) const override;
 610
 611   unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
 612
 613   bool preferZeroCompareBranch() const override { return true; }
 614
 615   bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 616     return isa<LoadInst>(I) || isa<StoreInst>(I);
 617   }
 618   Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
 619                                 AtomicOrdering Ord) const override;
 620   Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
 621                                  AtomicOrdering Ord) const override;
 622
 623   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
 624                                   EVT VT) const override;
 625
 626   ISD::NodeType getExtendForAtomicOps() const override {
 627     return ISD::SIGN_EXTEND;
 628   }
 629
 630   ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
 631     return ISD::SIGN_EXTEND;
 632   }
 633
 634   bool shouldTransformSignedTruncationCheck(EVT XVT,
 635                                             unsigned KeptBits) const override;
 636
 637   TargetLowering::ShiftLegalizationStrategy
 638   preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
 639                                      unsigned ExpansionFactor) const override {
 640     if (DAG.getMachineFunction().getFunction().hasMinSize())
 641       return ShiftLegalizationStrategy::LowerToLibcall;
 642     return TargetLowering::preferredShiftLegalizationStrategy(DAG, N,
 643                                                               ExpansionFactor);
 644   }
 645
 646   bool isDesirableToCommuteWithShift(const SDNode *N,
 647                                      CombineLevel Level) const override;
 648
 649   /// If a physical register, this returns the register that receives the
 650   /// exception address on entry to an EH pad.
 651   Register
 652   getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 653
 654   /// If a physical register, this returns the register that receives the
 655   /// exception typeid on entry to a landing pad.
 656   Register
 657   getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 658
 659   bool shouldExtendTypeInLibCall(EVT Type) const override;
 660   bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
 661
 662   /// Returns the register with the specified architectural or ABI name. This
 663   /// method is necessary to lower the llvm.read_register.* and
 664   /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
 665   /// with the clang -ffixed-xX flag for access to be allowed.
 666   Register getRegisterByName(const char *RegName, LLT VT,
 667                              const MachineFunction &MF) const override;
 668
 669   // Lower incoming arguments, copy physregs into vregs
 670   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
 671                                bool IsVarArg,
 672                                const SmallVectorImpl<ISD::InputArg> &Ins,
 673                                const SDLoc &DL, SelectionDAG &DAG,
 674                                SmallVectorImpl<SDValue> &InVals) const override;
 675   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
 676                       bool IsVarArg,
 677                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 678                       LLVMContext &Context) const override;
 679   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
 680                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 681                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 682                       SelectionDAG &DAG) const override;
 683   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 684                     SmallVectorImpl<SDValue> &InVals) const override;
 685
 686   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 687                                          Type *Ty) const override;
 688   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 689   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 690   bool shouldConsiderGEPOffsetSplit() const override { return true; }
 691
 692   bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
 693                               SDValue C) const override;
 694
 695   bool isMulAddWithConstProfitable(SDValue AddNode,
 696                                    SDValue ConstNode) const override;
 697
 698   TargetLowering::AtomicExpansionKind
 699   shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 700   Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
 701                                       Value *AlignedAddr, Value *Incr,
 702                                       Value *Mask, Value *ShiftAmt,
 703                                       AtomicOrdering Ord) const override;
 704   TargetLowering::AtomicExpansionKind
 705   shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
 706   Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
 707                                           AtomicCmpXchgInst *CI,
 708                                           Value *AlignedAddr, Value *CmpVal,
 709                                           Value *NewVal, Value *Mask,
 710                                           AtomicOrdering Ord) const override;
 711
 712   /// Returns true if the target allows unaligned memory accesses of the
 713   /// specified type.
 714   bool allowsMisalignedMemoryAccesses(
 715       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
 716       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 717       unsigned *Fast = nullptr) const override;
 718
 719   EVT getOptimalMemOpType(const MemOp &Op,
 720                           const AttributeList &FuncAttributes) const override;
 721
 722   bool splitValueIntoRegisterParts(
 723       SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
 724       unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
 725       const override;
 726
 727   SDValue joinRegisterPartsIntoValue(
 728       SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
 729       unsigned NumParts, MVT PartVT, EVT ValueVT,
 730       std::optional<CallingConv::ID> CC) const override;
 731
 732   // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
 733   SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
 734
 735   static RISCVII::VLMUL getLMUL(MVT VT);
 736   inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
 737                                       unsigned MinSize) {
 738     // Original equation:
 739     //   VLMAX = (VectorBits / EltSize) * LMUL
 740     //   where LMUL = MinSize / RISCV::RVVBitsPerBlock
 741     // The following equations have been reordered to prevent loss of precision
 742     // when calculating fractional LMUL.
 743     return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
 744   };
 745   static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
 746   static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
 747   static unsigned getRegClassIDForVecVT(MVT VT);
 748   static std::pair<unsigned, unsigned>
 749   decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
 750                                            unsigned InsertExtractIdx,
 751                                            const RISCVRegisterInfo *TRI);
 752   MVT getContainerForFixedLengthVector(MVT VT) const;
 753
 754   bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
 755
 756   bool isLegalElementTypeForRVV(EVT ScalarTy) const;
 757
 758   bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
 759
 760   unsigned getJumpTableEncoding() const override;
 761
 762   const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
 763                                           const MachineBasicBlock *MBB,
 764                                           unsigned uid,
 765                                           MCContext &Ctx) const override;
 766
 767   bool isVScaleKnownToBeAPowerOfTwo() const override;
 768
 769   bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
 770                               ISD::MemIndexedMode &AM, bool &IsInc,
 771                               SelectionDAG &DAG) const;
 772   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
 773                                  ISD::MemIndexedMode &AM,
 774                                  SelectionDAG &DAG) const override;
 775   bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
 776                                   SDValue &Offset, ISD::MemIndexedMode &AM,
 777                                   SelectionDAG &DAG) const override;
 778
 779   bool isLegalScaleForGatherScatter(uint64_t Scale,
 780                                     uint64_t ElemSize) const override {
 781     // Scaled addressing not supported on indexed load/stores
 782     return Scale == 1;
 783   }
 784
 785   /// If the target has a standard location for the stack protector cookie,
 786   /// returns the address of that location. Otherwise, returns nullptr.
 787   Value *getIRStackGuard(IRBuilderBase &IRB) const override;
 788
 789   /// Returns whether or not generating a interleaved load/store intrinsic for
 790   /// this type will be legal.
 791   bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
 792                                     Align Alignment, unsigned AddrSpace,
 793                                     const DataLayout &) const;
 794
 795   /// Return true if a stride load store of the given result type and
 796   /// alignment is legal.
 797   bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
 798
 799   unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
 800
 801   bool fallBackToDAGISel(const Instruction &Inst) const override;
 802
 803   bool lowerInterleavedLoad(LoadInst *LI,
 804                             ArrayRef<ShuffleVectorInst *> Shuffles,
 805                             ArrayRef<unsigned> Indices,
 806                             unsigned Factor) const override;
 807
 808   bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
 809                              unsigned Factor) const override;
 810
 811   bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II,
 812                                         LoadInst *LI) const override;
 813
 814   bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
 815                                        StoreInst *SI) const override;
 816
 817   bool supportKCFIBundles() const override { return true; }
 818
 819   MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
 820                               MachineBasicBlock::instr_iterator &MBBI,
 821                               const TargetInstrInfo *TII) const override;
 822
 823   /// RISCVCCAssignFn - This target-specific function extends the default
 824   /// CCValAssign with additional information used to lower RISC-V calling
 825   /// conventions.
 826   typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
 827                                unsigned ValNo, MVT ValVT, MVT LocVT,
 828                                CCValAssign::LocInfo LocInfo,
 829                                ISD::ArgFlagsTy ArgFlags, CCState &State,
 830                                bool IsFixed, bool IsRet, Type *OrigTy,
 831                                const RISCVTargetLowering &TLI,
 832                                std::optional<unsigned> FirstMaskArgument);
 833
 834 private:
 835   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
 836                         const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
 837                         RISCVCCAssignFn Fn) const;
 838   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
 839                          const SmallVectorImpl<ISD::OutputArg> &Outs,
 840                          bool IsRet, CallLoweringInfo *CLI,
 841                          RISCVCCAssignFn Fn) const;
 842
 843   template <class NodeTy>
 844   SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
 845                   bool IsExternWeak = false) const;
 846   SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
 847                            bool UseGOT) const;
 848   SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
 849
 850   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 851   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 852   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 853   SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 854   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 855   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 856   SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 857   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 858   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 859   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 860   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
 861   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 862   SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
 863   SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
 864   SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
 865                              int64_t ExtTrueVal) const;
 866   SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
 867   SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
 868   SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
 869   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 870   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 871   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 872   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 873   SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
 874   SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
 875   SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
 876   SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
 877                                       bool IsVP) const;
 878   SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
 879   SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 880   SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 881   SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
 882   SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
 883   SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 884   SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
 885   SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
 886   SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
 887   SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
 888   SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
 889   SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
 890                                                SelectionDAG &DAG) const;
 891   SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
 892   SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
 893   SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
 894   SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
 895   SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
 896   SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
 897                                             SelectionDAG &DAG) const;
 898   SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
 899   SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
 900   SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
 901   SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
 902   SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
 903   SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
 904   SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
 905   SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
 906   SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
 907   SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
 908                                             unsigned ExtendOpc) const;
 909   SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 910   SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
 911
 912   SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
 913   SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
 914
 915   SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
 916
 917   SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
 918
 919   SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
 920   SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
 921
 922   bool isEligibleForTailCallOptimization(
 923       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
 924       const SmallVector<CCValAssign, 16> &ArgLocs) const;
 925
 926   /// Generate error diagnostics if any register used by CC has been marked
 927   /// reserved.
 928   void validateCCReservedRegs(
 929       const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
 930       MachineFunction &MF) const;
 931
 932   bool useRVVForFixedLengthVectorVT(MVT VT) const;
 933
 934   MVT getVPExplicitVectorLengthTy() const override;
 935
 936   bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
 937                                    bool IsScalable) const override;
 938
 939   /// RVV code generation for fixed length vectors does not lower all
 940   /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
 941   /// merge. However, merging them creates a BUILD_VECTOR that is just as
 942   /// illegal as the original, thus leading to an infinite legalisation loop.
 943   /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
 944   /// this override can be removed.
 945   bool mergeStoresAfterLegalization(EVT VT) const override;
 946
 947   /// Disable normalizing
 948   /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
 949   /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
 950   /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
 951   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
 952     return false;
 953   };
 954
 955   /// For available scheduling models FDIV + two independent FMULs are much
 956   /// faster than two FDIVs.
 957   unsigned combineRepeatedFPDivisors() const override;
 958 };
 959
 960 namespace RISCV {
 961
 962 bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
 963               MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
 964               ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
 965               bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
 966               std::optional<unsigned> FirstMaskArgument);
 967
 968 bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
 969                      MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
 970                      ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
 971                      bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
 972                      std::optional<unsigned> FirstMaskArgument);
 973
 974 bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
 975                   CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
 976                   CCState &State);
 977 } // end namespace RISCV
 978
 979 namespace RISCVVIntrinsicsTable {
 980
 981 struct RISCVVIntrinsicInfo {
 982   unsigned IntrinsicID;
 983   uint8_t ScalarOperand;
 984   uint8_t VLOperand;
 985   bool hasScalarOperand() const {
 986     // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
 987     return ScalarOperand != 0xF;
 988   }
 989   bool hasVLOperand() const {
 990     // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
 991     return VLOperand != 0x1F;
 992   }
 993 };
 994
 995 using namespace RISCV;
 996
 997 #define GET_RISCVVIntrinsicsTable_DECL
 998 #include "RISCVGenSearchableTables.inc"
 999 #undef GET_RISCVVIntrinsicsTable_DECL
1000
1001 } // end namespace RISCVVIntrinsicsTable
1002
1003 } // end namespace llvm
1004
1005 #endif