llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp

   1 //===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 // This file implements the machine function pass to insert read/write of CSR-s
   9 // of the RISC-V instructions.
  10 //
  11 // Currently the pass implements:
  12 // -Naive insertion of a write to vxrm before an RVV fixed-point instruction.
  13 // -Writing and saving frm before an RVV floating-point instruction with a
  14 //  static rounding mode and restores the value after.
  15 //
  16 //===----------------------------------------------------------------------===//
  17
  18 #include "MCTargetDesc/RISCVBaseInfo.h"
  19 #include "RISCV.h"
  20 #include "RISCVSubtarget.h"
  21 #include "llvm/CodeGen/MachineFunctionPass.h"
  22 using namespace llvm;
  23
  24 #define DEBUG_TYPE "riscv-insert-read-write-csr"
  25 #define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
  26
  27 namespace {
  28
  29 class RISCVInsertReadWriteCSR : public MachineFunctionPass {
  30   const TargetInstrInfo *TII;
  31
  32 public:
  33   static char ID;
  34
  35   RISCVInsertReadWriteCSR() : MachineFunctionPass(ID) {
  36     initializeRISCVInsertReadWriteCSRPass(*PassRegistry::getPassRegistry());
  37   }
  38
  39   bool runOnMachineFunction(MachineFunction &MF) override;
  40
  41   void getAnalysisUsage(AnalysisUsage &AU) const override {
  42     AU.setPreservesCFG();
  43     MachineFunctionPass::getAnalysisUsage(AU);
  44   }
  45
  46   StringRef getPassName() const override {
  47     return RISCV_INSERT_READ_WRITE_CSR_NAME;
  48   }
  49
  50 private:
  51   bool emitWriteRoundingMode(MachineBasicBlock &MBB);
  52 };
  53
  54 } // end anonymous namespace
  55
  56 char RISCVInsertReadWriteCSR::ID = 0;
  57
  58 INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
  59                 RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
  60
  61 // This function inserts a write to vxrm when encountering an RVV fixed-point
  62 // instruction. This function also swaps frm and restores it when encountering
  63 // an RVV floating point instruction with a static rounding mode.
  64 bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
  65   bool Changed = false;
  66   for (MachineInstr &MI : MBB) {
  67     int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
  68     if (VXRMIdx >= 0) {
  69       unsigned VXRMImm = MI.getOperand(VXRMIdx).getImm();
  70
  71       Changed = true;
  72
  73       BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
  74           .addImm(VXRMImm);
  75       MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
  76                                               /*IsImp*/ true));
  77       continue;
  78     }
  79
  80     int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc());
  81     if (FRMIdx < 0)
  82       continue;
  83
  84     unsigned FRMImm = MI.getOperand(FRMIdx).getImm();
  85
  86     // The value is a hint to this pass to not alter the frm value.
  87     if (FRMImm == RISCVFPRndMode::DYN)
  88       continue;
  89
  90     Changed = true;
  91
  92     // Save
  93     MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
  94     Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
  95     BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
  96             SavedFRM)
  97         .addImm(FRMImm);
  98     MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
  99                                             /*IsImp*/ true));
 100     // Restore
 101     MachineInstrBuilder MIB =
 102         BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
 103             .addReg(SavedFRM);
 104     MBB.insertAfter(MI, MIB);
 105   }
 106   return Changed;
 107 }
 108
 109 bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
 110   // Skip if the vector extension is not enabled.
 111   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
 112   if (!ST.hasVInstructions())
 113     return false;
 114
 115   TII = ST.getInstrInfo();
 116
 117   bool Changed = false;
 118
 119   for (MachineBasicBlock &MBB : MF)
 120     Changed |= emitWriteRoundingMode(MBB);
 121
 122   return Changed;
 123 }
 124
 125 FunctionPass *llvm::createRISCVInsertReadWriteCSRPass() {
 126   return new RISCVInsertReadWriteCSR();
 127 }