llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

   1 //===- RISCVOptWInstrs.cpp - MI W instruction optimizations ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===---------------------------------------------------------------------===//
   8 //
   9 // This pass does some optimizations for *W instructions at the MI level.
  10 //
  11 // First it removes unneeded sext.w instructions. Either because the sign
  12 // extended bits aren't consumed or because the input was already sign extended
  13 // by an earlier instruction.
  14 //
  15 // Then it removes the -w suffix from opw instructions whenever all users are
  16 // dependent only on the lower word of the result of the instruction.
  17 // The cases handled are:
  18 // * addw because c.add has a larger register encoding than c.addw.
  19 // * addiw because it helps reduce test differences between RV32 and RV64
  20 //   w/o being a pessimization.
  21 // * mulw because c.mulw doesn't exist but c.mul does (w/ zcb)
  22 // * slliw because c.slliw doesn't exist and c.slli does
  23 //
  24 //===---------------------------------------------------------------------===//
  25
  26 #include "RISCV.h"
  27 #include "RISCVMachineFunctionInfo.h"
  28 #include "RISCVSubtarget.h"
  29 #include "llvm/ADT/SmallSet.h"
  30 #include "llvm/ADT/Statistic.h"
  31 #include "llvm/CodeGen/MachineFunctionPass.h"
  32 #include "llvm/CodeGen/TargetInstrInfo.h"
  33
  34 using namespace llvm;
  35
  36 #define DEBUG_TYPE "riscv-opt-w-instrs"
  37 #define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions"
  38
  39 STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");
  40 STATISTIC(NumTransformedToWInstrs,
  41           "Number of instructions transformed to W-ops");
  42
  43 static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
  44                                          cl::desc("Disable removal of sext.w"),
  45                                          cl::init(false), cl::Hidden);
  46 static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
  47                                          cl::desc("Disable strip W suffix"),
  48                                          cl::init(false), cl::Hidden);
  49
  50 namespace {
  51
  52 class RISCVOptWInstrs : public MachineFunctionPass {
  53 public:
  54   static char ID;
  55
  56   RISCVOptWInstrs() : MachineFunctionPass(ID) {
  57     initializeRISCVOptWInstrsPass(*PassRegistry::getPassRegistry());
  58   }
  59
  60   bool runOnMachineFunction(MachineFunction &MF) override;
  61   bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII,
  62                          const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
  63   bool stripWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
  64                       const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
  65
  66   void getAnalysisUsage(AnalysisUsage &AU) const override {
  67     AU.setPreservesCFG();
  68     MachineFunctionPass::getAnalysisUsage(AU);
  69   }
  70
  71   StringRef getPassName() const override { return RISCV_OPT_W_INSTRS_NAME; }
  72 };
  73
  74 } // end anonymous namespace
  75
  76 char RISCVOptWInstrs::ID = 0;
  77 INITIALIZE_PASS(RISCVOptWInstrs, DEBUG_TYPE, RISCV_OPT_W_INSTRS_NAME, false,
  78                 false)
  79
  80 FunctionPass *llvm::createRISCVOptWInstrsPass() {
  81   return new RISCVOptWInstrs();
  82 }
  83
  84 static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
  85                                         unsigned Bits) {
  86   const MachineInstr &MI = *UserOp.getParent();
  87   unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode());
  88
  89   if (!MCOpcode)
  90     return false;
  91
  92   const MCInstrDesc &MCID = MI.getDesc();
  93   const uint64_t TSFlags = MCID.TSFlags;
  94   if (!RISCVII::hasSEWOp(TSFlags))
  95     return false;
  96   assert(RISCVII::hasVLOp(TSFlags));
  97   const unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MCID)).getImm();
  98
  99   if (UserOp.getOperandNo() == RISCVII::getVLOpNum(MCID))
 100     return false;
 101
 102   auto NumDemandedBits =
 103       RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW);
 104   return NumDemandedBits && Bits >= *NumDemandedBits;
 105 }
 106
 107 // Checks if all users only demand the lower \p OrigBits of the original
 108 // instruction's result.
 109 // TODO: handle multiple interdependent transformations
 110 static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 111                             const RISCVSubtarget &ST,
 112                             const MachineRegisterInfo &MRI, unsigned OrigBits) {
 113
 114   SmallSet<std::pair<const MachineInstr *, unsigned>, 4> Visited;
 115   SmallVector<std::pair<const MachineInstr *, unsigned>, 4> Worklist;
 116
 117   Worklist.push_back(std::make_pair(&OrigMI, OrigBits));
 118
 119   while (!Worklist.empty()) {
 120     auto P = Worklist.pop_back_val();
 121     const MachineInstr *MI = P.first;
 122     unsigned Bits = P.second;
 123
 124     if (!Visited.insert(P).second)
 125       continue;
 126
 127     // Only handle instructions with one def.
 128     if (MI->getNumExplicitDefs() != 1)
 129       return false;
 130
 131     for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
 132       const MachineInstr *UserMI = UserOp.getParent();
 133       unsigned OpIdx = UserOp.getOperandNo();
 134
 135       switch (UserMI->getOpcode()) {
 136       default:
 137         if (vectorPseudoHasAllNBitUsers(UserOp, Bits))
 138           break;
 139         return false;
 140
 141       case RISCV::ADDIW:
 142       case RISCV::ADDW:
 143       case RISCV::DIVUW:
 144       case RISCV::DIVW:
 145       case RISCV::MULW:
 146       case RISCV::REMUW:
 147       case RISCV::REMW:
 148       case RISCV::SLLIW:
 149       case RISCV::SLLW:
 150       case RISCV::SRAIW:
 151       case RISCV::SRAW:
 152       case RISCV::SRLIW:
 153       case RISCV::SRLW:
 154       case RISCV::SUBW:
 155       case RISCV::ROLW:
 156       case RISCV::RORW:
 157       case RISCV::RORIW:
 158       case RISCV::CLZW:
 159       case RISCV::CTZW:
 160       case RISCV::CPOPW:
 161       case RISCV::SLLI_UW:
 162       case RISCV::FMV_W_X:
 163       case RISCV::FCVT_H_W:
 164       case RISCV::FCVT_H_WU:
 165       case RISCV::FCVT_S_W:
 166       case RISCV::FCVT_S_WU:
 167       case RISCV::FCVT_D_W:
 168       case RISCV::FCVT_D_WU:
 169         if (Bits >= 32)
 170           break;
 171         return false;
 172       case RISCV::SEXT_B:
 173       case RISCV::PACKH:
 174         if (Bits >= 8)
 175           break;
 176         return false;
 177       case RISCV::SEXT_H:
 178       case RISCV::FMV_H_X:
 179       case RISCV::ZEXT_H_RV32:
 180       case RISCV::ZEXT_H_RV64:
 181       case RISCV::PACKW:
 182         if (Bits >= 16)
 183           break;
 184         return false;
 185
 186       case RISCV::PACK:
 187         if (Bits >= (ST.getXLen() / 2))
 188           break;
 189         return false;
 190
 191       case RISCV::SRLI: {
 192         // If we are shifting right by less than Bits, and users don't demand
 193         // any bits that were shifted into [Bits-1:0], then we can consider this
 194         // as an N-Bit user.
 195         unsigned ShAmt = UserMI->getOperand(2).getImm();
 196         if (Bits > ShAmt) {
 197           Worklist.push_back(std::make_pair(UserMI, Bits - ShAmt));
 198           break;
 199         }
 200         return false;
 201       }
 202
 203       // these overwrite higher input bits, otherwise the lower word of output
 204       // depends only on the lower word of input. So check their uses read W.
 205       case RISCV::SLLI:
 206         if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm()))
 207           break;
 208         Worklist.push_back(std::make_pair(UserMI, Bits));
 209         break;
 210       case RISCV::ANDI: {
 211         uint64_t Imm = UserMI->getOperand(2).getImm();
 212         if (Bits >= (unsigned)llvm::bit_width(Imm))
 213           break;
 214         Worklist.push_back(std::make_pair(UserMI, Bits));
 215         break;
 216       }
 217       case RISCV::ORI: {
 218         uint64_t Imm = UserMI->getOperand(2).getImm();
 219         if (Bits >= (unsigned)llvm::bit_width<uint64_t>(~Imm))
 220           break;
 221         Worklist.push_back(std::make_pair(UserMI, Bits));
 222         break;
 223       }
 224
 225       case RISCV::SLL:
 226       case RISCV::BSET:
 227       case RISCV::BCLR:
 228       case RISCV::BINV:
 229         // Operand 2 is the shift amount which uses log2(xlen) bits.
 230         if (OpIdx == 2) {
 231           if (Bits >= Log2_32(ST.getXLen()))
 232             break;
 233           return false;
 234         }
 235         Worklist.push_back(std::make_pair(UserMI, Bits));
 236         break;
 237
 238       case RISCV::SRA:
 239       case RISCV::SRL:
 240       case RISCV::ROL:
 241       case RISCV::ROR:
 242         // Operand 2 is the shift amount which uses 6 bits.
 243         if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen()))
 244           break;
 245         return false;
 246
 247       case RISCV::ADD_UW:
 248       case RISCV::SH1ADD_UW:
 249       case RISCV::SH2ADD_UW:
 250       case RISCV::SH3ADD_UW:
 251         // Operand 1 is implicitly zero extended.
 252         if (OpIdx == 1 && Bits >= 32)
 253           break;
 254         Worklist.push_back(std::make_pair(UserMI, Bits));
 255         break;
 256
 257       case RISCV::BEXTI:
 258         if (UserMI->getOperand(2).getImm() >= Bits)
 259           return false;
 260         break;
 261
 262       case RISCV::SB:
 263         // The first argument is the value to store.
 264         if (OpIdx == 0 && Bits >= 8)
 265           break;
 266         return false;
 267       case RISCV::SH:
 268         // The first argument is the value to store.
 269         if (OpIdx == 0 && Bits >= 16)
 270           break;
 271         return false;
 272       case RISCV::SW:
 273         // The first argument is the value to store.
 274         if (OpIdx == 0 && Bits >= 32)
 275           break;
 276         return false;
 277
 278       // For these, lower word of output in these operations, depends only on
 279       // the lower word of input. So, we check all uses only read lower word.
 280       case RISCV::COPY:
 281       case RISCV::PHI:
 282
 283       case RISCV::ADD:
 284       case RISCV::ADDI:
 285       case RISCV::AND:
 286       case RISCV::MUL:
 287       case RISCV::OR:
 288       case RISCV::SUB:
 289       case RISCV::XOR:
 290       case RISCV::XORI:
 291
 292       case RISCV::ANDN:
 293       case RISCV::BREV8:
 294       case RISCV::CLMUL:
 295       case RISCV::ORC_B:
 296       case RISCV::ORN:
 297       case RISCV::SH1ADD:
 298       case RISCV::SH2ADD:
 299       case RISCV::SH3ADD:
 300       case RISCV::XNOR:
 301       case RISCV::BSETI:
 302       case RISCV::BCLRI:
 303       case RISCV::BINVI:
 304         Worklist.push_back(std::make_pair(UserMI, Bits));
 305         break;
 306
 307       case RISCV::PseudoCCMOVGPR:
 308         // Either operand 4 or operand 5 is returned by this instruction. If
 309         // only the lower word of the result is used, then only the lower word
 310         // of operand 4 and 5 is used.
 311         if (OpIdx != 4 && OpIdx != 5)
 312           return false;
 313         Worklist.push_back(std::make_pair(UserMI, Bits));
 314         break;
 315
 316       case RISCV::CZERO_EQZ:
 317       case RISCV::CZERO_NEZ:
 318       case RISCV::VT_MASKC:
 319       case RISCV::VT_MASKCN:
 320         if (OpIdx != 1)
 321           return false;
 322         Worklist.push_back(std::make_pair(UserMI, Bits));
 323         break;
 324       }
 325     }
 326   }
 327
 328   return true;
 329 }
 330
 331 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST,
 332                          const MachineRegisterInfo &MRI) {
 333   return hasAllNBitUsers(OrigMI, ST, MRI, 32);
 334 }
 335
 336 // This function returns true if the machine instruction always outputs a value
 337 // where bits 63:32 match bit 31.
 338 static bool isSignExtendingOpW(const MachineInstr &MI,
 339                                const MachineRegisterInfo &MRI) {
 340   uint64_t TSFlags = MI.getDesc().TSFlags;
 341
 342   // Instructions that can be determined from opcode are marked in tablegen.
 343   if (TSFlags & RISCVII::IsSignExtendingOpWMask)
 344     return true;
 345
 346   // Special cases that require checking operands.
 347   switch (MI.getOpcode()) {
 348   // shifting right sufficiently makes the value 32-bit sign-extended
 349   case RISCV::SRAI:
 350     return MI.getOperand(2).getImm() >= 32;
 351   case RISCV::SRLI:
 352     return MI.getOperand(2).getImm() > 32;
 353   // The LI pattern ADDI rd, X0, imm is sign extended.
 354   case RISCV::ADDI:
 355     return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;
 356   // An ANDI with an 11 bit immediate will zero bits 63:11.
 357   case RISCV::ANDI:
 358     return isUInt<11>(MI.getOperand(2).getImm());
 359   // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
 360   case RISCV::ORI:
 361     return !isUInt<11>(MI.getOperand(2).getImm());
 362   // Copying from X0 produces zero.
 363   case RISCV::COPY:
 364     return MI.getOperand(1).getReg() == RISCV::X0;
 365   }
 366
 367   return false;
 368 }
 369
 370 static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
 371                             const MachineRegisterInfo &MRI,
 372                             SmallPtrSetImpl<MachineInstr *> &FixableDef) {
 373
 374   SmallPtrSet<const MachineInstr *, 4> Visited;
 375   SmallVector<MachineInstr *, 4> Worklist;
 376
 377   auto AddRegDefToWorkList = [&](Register SrcReg) {
 378     if (!SrcReg.isVirtual())
 379       return false;
 380     MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
 381     if (!SrcMI)
 382       return false;
 383     // Add SrcMI to the worklist.
 384     Worklist.push_back(SrcMI);
 385     return true;
 386   };
 387
 388   if (!AddRegDefToWorkList(SrcReg))
 389     return false;
 390
 391   while (!Worklist.empty()) {
 392     MachineInstr *MI = Worklist.pop_back_val();
 393
 394     // If we already visited this instruction, we don't need to check it again.
 395     if (!Visited.insert(MI).second)
 396       continue;
 397
 398     // If this is a sign extending operation we don't need to look any further.
 399     if (isSignExtendingOpW(*MI, MRI))
 400       continue;
 401
 402     // Is this an instruction that propagates sign extend?
 403     switch (MI->getOpcode()) {
 404     default:
 405       // Unknown opcode, give up.
 406       return false;
 407     case RISCV::COPY: {
 408       const MachineFunction *MF = MI->getMF();
 409       const RISCVMachineFunctionInfo *RVFI =
 410           MF->getInfo<RISCVMachineFunctionInfo>();
 411
 412       // If this is the entry block and the register is livein, see if we know
 413       // it is sign extended.
 414       if (MI->getParent() == &MF->front()) {
 415         Register VReg = MI->getOperand(0).getReg();
 416         if (MF->getRegInfo().isLiveIn(VReg) && RVFI->isSExt32Register(VReg))
 417           continue;
 418       }
 419
 420       Register CopySrcReg = MI->getOperand(1).getReg();
 421       if (CopySrcReg == RISCV::X10) {
 422         // For a method return value, we check the ZExt/SExt flags in attribute.
 423         // We assume the following code sequence for method call.
 424         // PseudoCALL @bar, ...
 425         // ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
 426         // %0:gpr = COPY $x10
 427         //
 428         // We use the PseudoCall to look up the IR function being called to find
 429         // its return attributes.
 430         const MachineBasicBlock *MBB = MI->getParent();
 431         auto II = MI->getIterator();
 432         if (II == MBB->instr_begin() ||
 433             (--II)->getOpcode() != RISCV::ADJCALLSTACKUP)
 434           return false;
 435
 436         const MachineInstr &CallMI = *(--II);
 437         if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
 438           return false;
 439
 440         auto *CalleeFn =
 441             dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
 442         if (!CalleeFn)
 443           return false;
 444
 445         auto *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
 446         if (!IntTy)
 447           return false;
 448
 449         const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
 450         unsigned BitWidth = IntTy->getBitWidth();
 451         if ((BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||
 452             (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))
 453           continue;
 454       }
 455
 456       if (!AddRegDefToWorkList(CopySrcReg))
 457         return false;
 458
 459       break;
 460     }
 461
 462     // For these, we just need to check if the 1st operand is sign extended.
 463     case RISCV::BCLRI:
 464     case RISCV::BINVI:
 465     case RISCV::BSETI:
 466       if (MI->getOperand(2).getImm() >= 31)
 467         return false;
 468       [[fallthrough]];
 469     case RISCV::REM:
 470     case RISCV::ANDI:
 471     case RISCV::ORI:
 472     case RISCV::XORI:
 473       // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
 474       // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
 475       // Logical operations use a sign extended 12-bit immediate.
 476       if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
 477         return false;
 478
 479       break;
 480     case RISCV::PseudoCCADDW:
 481     case RISCV::PseudoCCSUBW:
 482       // Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to
 483       // check if operand 4 is sign extended.
 484       if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
 485         return false;
 486       break;
 487     case RISCV::REMU:
 488     case RISCV::AND:
 489     case RISCV::OR:
 490     case RISCV::XOR:
 491     case RISCV::ANDN:
 492     case RISCV::ORN:
 493     case RISCV::XNOR:
 494     case RISCV::MAX:
 495     case RISCV::MAXU:
 496     case RISCV::MIN:
 497     case RISCV::MINU:
 498     case RISCV::PseudoCCMOVGPR:
 499     case RISCV::PseudoCCAND:
 500     case RISCV::PseudoCCOR:
 501     case RISCV::PseudoCCXOR:
 502     case RISCV::PHI: {
 503       // If all incoming values are sign-extended, the output of AND, OR, XOR,
 504       // MIN, MAX, or PHI is also sign-extended.
 505
 506       // The input registers for PHI are operand 1, 3, ...
 507       // The input registers for PseudoCCMOVGPR are 4 and 5.
 508       // The input registers for PseudoCCAND/OR/XOR are 4, 5, and 6.
 509       // The input registers for others are operand 1 and 2.
 510       unsigned B = 1, E = 3, D = 1;
 511       switch (MI->getOpcode()) {
 512       case RISCV::PHI:
 513         E = MI->getNumOperands();
 514         D = 2;
 515         break;
 516       case RISCV::PseudoCCMOVGPR:
 517         B = 4;
 518         E = 6;
 519         break;
 520       case RISCV::PseudoCCAND:
 521       case RISCV::PseudoCCOR:
 522       case RISCV::PseudoCCXOR:
 523         B = 4;
 524         E = 7;
 525         break;
 526        }
 527
 528       for (unsigned I = B; I != E; I += D) {
 529         if (!MI->getOperand(I).isReg())
 530           return false;
 531
 532         if (!AddRegDefToWorkList(MI->getOperand(I).getReg()))
 533           return false;
 534       }
 535
 536       break;
 537     }
 538
 539     case RISCV::CZERO_EQZ:
 540     case RISCV::CZERO_NEZ:
 541     case RISCV::VT_MASKC:
 542     case RISCV::VT_MASKCN:
 543       // Instructions return zero or operand 1. Result is sign extended if
 544       // operand 1 is sign extended.
 545       if (!AddRegDefToWorkList(MI->getOperand(1).getReg()))
 546         return false;
 547       break;
 548
 549     // With these opcode, we can "fix" them with the W-version
 550     // if we know all users of the result only rely on bits 31:0
 551     case RISCV::SLLI:
 552       // SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
 553       if (MI->getOperand(2).getImm() >= 32)
 554         return false;
 555       [[fallthrough]];
 556     case RISCV::ADDI:
 557     case RISCV::ADD:
 558     case RISCV::LD:
 559     case RISCV::LWU:
 560     case RISCV::MUL:
 561     case RISCV::SUB:
 562       if (hasAllWUsers(*MI, ST, MRI)) {
 563         FixableDef.insert(MI);
 564         break;
 565       }
 566       return false;
 567     }
 568   }
 569
 570   // If we get here, then every node we visited produces a sign extended value
 571   // or propagated sign extended values. So the result must be sign extended.
 572   return true;
 573 }
 574
 575 static unsigned getWOp(unsigned Opcode) {
 576   switch (Opcode) {
 577   case RISCV::ADDI:
 578     return RISCV::ADDIW;
 579   case RISCV::ADD:
 580     return RISCV::ADDW;
 581   case RISCV::LD:
 582   case RISCV::LWU:
 583     return RISCV::LW;
 584   case RISCV::MUL:
 585     return RISCV::MULW;
 586   case RISCV::SLLI:
 587     return RISCV::SLLIW;
 588   case RISCV::SUB:
 589     return RISCV::SUBW;
 590   default:
 591     llvm_unreachable("Unexpected opcode for replacement with W variant");
 592   }
 593 }
 594
 595 bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
 596                                         const RISCVInstrInfo &TII,
 597                                         const RISCVSubtarget &ST,
 598                                         MachineRegisterInfo &MRI) {
 599   if (DisableSExtWRemoval)
 600     return false;
 601
 602   bool MadeChange = false;
 603   for (MachineBasicBlock &MBB : MF) {
 604     for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
 605       // We're looking for the sext.w pattern ADDIW rd, rs1, 0.
 606       if (!RISCV::isSEXT_W(MI))
 607         continue;
 608
 609       Register SrcReg = MI.getOperand(1).getReg();
 610
 611       SmallPtrSet<MachineInstr *, 4> FixableDefs;
 612
 613       // If all users only use the lower bits, this sext.w is redundant.
 614       // Or if all definitions reaching MI sign-extend their output,
 615       // then sext.w is redundant.
 616       if (!hasAllWUsers(MI, ST, MRI) &&
 617           !isSignExtendedW(SrcReg, ST, MRI, FixableDefs))
 618         continue;
 619
 620       Register DstReg = MI.getOperand(0).getReg();
 621       if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
 622         continue;
 623
 624       // Convert Fixable instructions to their W versions.
 625       for (MachineInstr *Fixable : FixableDefs) {
 626         LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
 627         Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
 628         Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
 629         Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
 630         Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
 631         LLVM_DEBUG(dbgs() << "     with " << *Fixable);
 632         ++NumTransformedToWInstrs;
 633       }
 634
 635       LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
 636       MRI.replaceRegWith(DstReg, SrcReg);
 637       MRI.clearKillFlags(SrcReg);
 638       MI.eraseFromParent();
 639       ++NumRemovedSExtW;
 640       MadeChange = true;
 641     }
 642   }
 643
 644   return MadeChange;
 645 }
 646
 647 bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
 648                                      const RISCVInstrInfo &TII,
 649                                      const RISCVSubtarget &ST,
 650                                      MachineRegisterInfo &MRI) {
 651   if (DisableStripWSuffix)
 652     return false;
 653
 654   bool MadeChange = false;
 655   for (MachineBasicBlock &MBB : MF) {
 656     for (MachineInstr &MI : MBB) {
 657       unsigned Opc;
 658       switch (MI.getOpcode()) {
 659       default:
 660         continue;
 661       case RISCV::ADDW:  Opc = RISCV::ADD;  break;
 662       case RISCV::ADDIW: Opc = RISCV::ADDI; break;
 663       case RISCV::MULW:  Opc = RISCV::MUL;  break;
 664       case RISCV::SLLIW: Opc = RISCV::SLLI; break;
 665       }
 666
 667       if (hasAllWUsers(MI, ST, MRI)) {
 668         MI.setDesc(TII.get(Opc));
 669         MadeChange = true;
 670       }
 671     }
 672   }
 673
 674   return MadeChange;
 675 }
 676
 677 bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
 678   if (skipFunction(MF.getFunction()))
 679     return false;
 680
 681   MachineRegisterInfo &MRI = MF.getRegInfo();
 682   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
 683   const RISCVInstrInfo &TII = *ST.getInstrInfo();
 684
 685   if (!ST.is64Bit())
 686     return false;
 687
 688   bool MadeChange = false;
 689   MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);
 690   MadeChange |= stripWSuffixes(MF, TII, ST, MRI);
 691
 692   return MadeChange;
 693 }