llvm/lib/Target/RISCV/RISCVSchedRocket.td

   1 //==- RISCVSchedRocket.td - Rocket Scheduling Definitions ----*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 // ===---------------------------------------------------------------------===//
  10 // The following definitions describe the simpler per-operand machine model.
  11 // This works with MachineScheduler. See MCSchedule.h for details.
  12
  13 // Rocket machine model for scheduling and other instruction cost heuristics.
  14 def RocketModel : SchedMachineModel {
  15   let MicroOpBufferSize = 0; // Rocket is in-order.
  16   let IssueWidth = 1;        // 1 micro-op is dispatched per cycle.
  17   let LoadLatency = 3;
  18   let MispredictPenalty = 3;
  19   let CompleteModel = false;
  20   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
  21                              HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
  22                              HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
  23                              HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
  24 }
  25
  26 //===----------------------------------------------------------------------===//
  27 // Define each kind of processor resource and number available.
  28
  29 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
  30 // Rocket is in-order.
  31
  32 let BufferSize = 0 in {
  33 def RocketUnitALU        : ProcResource<1>; // Int ALU
  34 def RocketUnitIMul       : ProcResource<1>; // Int Multiply
  35 def RocketUnitMem        : ProcResource<1>; // Load/Store
  36 def RocketUnitB          : ProcResource<1>; // Branch
  37
  38 def RocketUnitFPALU      : ProcResource<1>; // FP ALU
  39 }
  40
  41 let BufferSize = 1 in {
  42 def RocketUnitIDiv       : ProcResource<1>; // Int Division
  43 def RocketUnitFPDivSqrt  : ProcResource<1>; // FP Divide/Sqrt
  44 }
  45
  46 //===----------------------------------------------------------------------===//
  47
  48 let SchedModel = RocketModel in {
  49
  50 // Branching
  51 def : WriteRes<WriteJmp, [RocketUnitB]>;
  52 def : WriteRes<WriteJal, [RocketUnitB]>;
  53 def : WriteRes<WriteJalr, [RocketUnitB]>;
  54
  55 // Integer arithmetic and logic
  56 def : WriteRes<WriteIALU32, [RocketUnitALU]>;
  57 def : WriteRes<WriteIALU, [RocketUnitALU]>;
  58 def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
  59 def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
  60 def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
  61 def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
  62
  63 // Integer multiplication
  64 let Latency = 4 in {
  65 def : WriteRes<WriteIMul, [RocketUnitIMul]>;
  66 def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
  67 }
  68
  69 // Integer division
  70 // Worst case latency is used.
  71 def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
  72   let Latency = 34;
  73   let ReleaseAtCycles = [34];
  74 }
  75 def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
  76   let Latency = 33;
  77   let ReleaseAtCycles = [33];
  78 }
  79
  80 // Memory
  81 def : WriteRes<WriteSTB, [RocketUnitMem]>;
  82 def : WriteRes<WriteSTH, [RocketUnitMem]>;
  83 def : WriteRes<WriteSTW, [RocketUnitMem]>;
  84 def : WriteRes<WriteSTD, [RocketUnitMem]>;
  85 def : WriteRes<WriteFST32, [RocketUnitMem]>;
  86 def : WriteRes<WriteFST64, [RocketUnitMem]>;
  87
  88 let Latency = 3 in {
  89 def : WriteRes<WriteLDB, [RocketUnitMem]>;
  90 def : WriteRes<WriteLDH, [RocketUnitMem]>;
  91 }
  92
  93 let Latency = 2 in {
  94 def : WriteRes<WriteLDW, [RocketUnitMem]>;
  95 def : WriteRes<WriteLDD, [RocketUnitMem]>;
  96 def : WriteRes<WriteFLD32, [RocketUnitMem]>;
  97 def : WriteRes<WriteFLD64, [RocketUnitMem]>;
  98
  99 // Atomic memory
 100 def : WriteRes<WriteAtomicW, [RocketUnitMem]>;
 101 def : WriteRes<WriteAtomicD, [RocketUnitMem]>;
 102
 103 def : WriteRes<WriteAtomicLDW, [RocketUnitMem]>;
 104 def : WriteRes<WriteAtomicLDD, [RocketUnitMem]>;
 105 }
 106
 107 def : WriteRes<WriteAtomicSTW, [RocketUnitMem]>;
 108 def : WriteRes<WriteAtomicSTD, [RocketUnitMem]>;
 109
 110 // Single precision.
 111 let Latency = 4 in {
 112 def : WriteRes<WriteFAdd32, [RocketUnitFPALU]>;
 113 def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
 114 def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
 115 }
 116
 117 // Double precision
 118 let Latency = 6 in {
 119 def : WriteRes<WriteFAdd64, [RocketUnitFPALU]>;
 120 def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
 121 def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
 122 }
 123
 124 // Conversions
 125 let Latency = 2 in {
 126 def : WriteRes<WriteFCvtI32ToF32, [RocketUnitFPALU]>;
 127 def : WriteRes<WriteFCvtI32ToF64, [RocketUnitFPALU]>;
 128 def : WriteRes<WriteFCvtI64ToF32, [RocketUnitFPALU]>;
 129 def : WriteRes<WriteFCvtI64ToF64, [RocketUnitFPALU]>;
 130 def : WriteRes<WriteFCvtF32ToI32, [RocketUnitFPALU]>;
 131 def : WriteRes<WriteFCvtF32ToI64, [RocketUnitFPALU]>;
 132 def : WriteRes<WriteFCvtF64ToI32, [RocketUnitFPALU]>;
 133 def : WriteRes<WriteFCvtF64ToI64, [RocketUnitFPALU]>;
 134 def : WriteRes<WriteFCvtF32ToF64, [RocketUnitFPALU]>;
 135 def : WriteRes<WriteFCvtF64ToF32, [RocketUnitFPALU]>;
 136
 137 def : WriteRes<WriteFClass32, [RocketUnitFPALU]>;
 138 def : WriteRes<WriteFClass64, [RocketUnitFPALU]>;
 139 def : WriteRes<WriteFCmp32, [RocketUnitFPALU]>;
 140 def : WriteRes<WriteFCmp64, [RocketUnitFPALU]>;
 141 def : WriteRes<WriteFMovF32ToI32, [RocketUnitFPALU]>;
 142 def : WriteRes<WriteFMovI32ToF32, [RocketUnitFPALU]>;
 143 def : WriteRes<WriteFMovF64ToI64, [RocketUnitFPALU]>;
 144 def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
 145 }
 146
 147 // FP multiplication
 148 let Latency = 5 in {
 149 def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
 150 def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
 151 }
 152
 153 let Latency = 7 in {
 154 def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
 155 def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
 156 }
 157
 158 // FP division
 159 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
 160 let Latency = 20, ReleaseAtCycles = [20] in {
 161 def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
 162 def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
 163 }
 164
 165 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
 166 def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
 167                                                       let ReleaseAtCycles = [20]; }
 168 def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
 169                                                       let ReleaseAtCycles = [25]; }
 170
 171 // Others
 172 def : WriteRes<WriteCSR, []>;
 173 def : WriteRes<WriteNop, []>;
 174
 175 def : InstRW<[WriteIALU], (instrs COPY)>;
 176
 177 //===----------------------------------------------------------------------===//
 178 // Bypass and advance
 179 def : ReadAdvance<ReadJmp, 0>;
 180 def : ReadAdvance<ReadJalr, 0>;
 181 def : ReadAdvance<ReadCSR, 0>;
 182 def : ReadAdvance<ReadStoreData, 0>;
 183 def : ReadAdvance<ReadMemBase, 0>;
 184 def : ReadAdvance<ReadIALU, 0>;
 185 def : ReadAdvance<ReadIALU32, 0>;
 186 def : ReadAdvance<ReadShiftImm, 0>;
 187 def : ReadAdvance<ReadShiftImm32, 0>;
 188 def : ReadAdvance<ReadShiftReg, 0>;
 189 def : ReadAdvance<ReadShiftReg32, 0>;
 190 def : ReadAdvance<ReadIDiv, 0>;
 191 def : ReadAdvance<ReadIDiv32, 0>;
 192 def : ReadAdvance<ReadIMul, 0>;
 193 def : ReadAdvance<ReadIMul32, 0>;
 194 def : ReadAdvance<ReadAtomicWA, 0>;
 195 def : ReadAdvance<ReadAtomicWD, 0>;
 196 def : ReadAdvance<ReadAtomicDA, 0>;
 197 def : ReadAdvance<ReadAtomicDD, 0>;
 198 def : ReadAdvance<ReadAtomicLDW, 0>;
 199 def : ReadAdvance<ReadAtomicLDD, 0>;
 200 def : ReadAdvance<ReadAtomicSTW, 0>;
 201 def : ReadAdvance<ReadAtomicSTD, 0>;
 202 def : ReadAdvance<ReadFStoreData, 0>;
 203 def : ReadAdvance<ReadFMemBase, 0>;
 204 def : ReadAdvance<ReadFAdd32, 0>;
 205 def : ReadAdvance<ReadFAdd64, 0>;
 206 def : ReadAdvance<ReadFMul32, 0>;
 207 def : ReadAdvance<ReadFMul64, 0>;
 208 def : ReadAdvance<ReadFMA32, 0>;
 209 def : ReadAdvance<ReadFMA32Addend, 0>;
 210 def : ReadAdvance<ReadFMA64, 0>;
 211 def : ReadAdvance<ReadFMA64Addend, 0>;
 212 def : ReadAdvance<ReadFDiv32, 0>;
 213 def : ReadAdvance<ReadFDiv64, 0>;
 214 def : ReadAdvance<ReadFSqrt32, 0>;
 215 def : ReadAdvance<ReadFSqrt64, 0>;
 216 def : ReadAdvance<ReadFCmp32, 0>;
 217 def : ReadAdvance<ReadFCmp64, 0>;
 218 def : ReadAdvance<ReadFSGNJ32, 0>;
 219 def : ReadAdvance<ReadFSGNJ64, 0>;
 220 def : ReadAdvance<ReadFMinMax32, 0>;
 221 def : ReadAdvance<ReadFMinMax64, 0>;
 222 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 223 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 224 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 225 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
 226 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 227 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
 228 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 229 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 230 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 231 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
 232 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 233 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 234 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 235 def : ReadAdvance<ReadFMovI64ToF64, 0>;
 236 def : ReadAdvance<ReadFClass32, 0>;
 237 def : ReadAdvance<ReadFClass64, 0>;
 238
 239 //===----------------------------------------------------------------------===//
 240 // Unsupported extensions
 241 defm : UnsupportedSchedV;
 242 defm : UnsupportedSchedZba;
 243 defm : UnsupportedSchedZbb;
 244 defm : UnsupportedSchedZbc;
 245 defm : UnsupportedSchedZbs;
 246 defm : UnsupportedSchedZbkb;
 247 defm : UnsupportedSchedZbkx;
 248 defm : UnsupportedSchedZfa;
 249 defm : UnsupportedSchedZfh;
 250 defm : UnsupportedSchedSFB;
 251 }