| blob | 98a73bdd93203450cf74ab6afa058a23f9e1f30b |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
4 # Main intention is to verify machine instructions have valid register classes.
5 # Use of UBFM[W|X]ri is used as an arbitrary instruction that requires GPR[32|64]RegClass.
6 # If the ADD/SUB optimization generates invalid register classes, this test will fail.
7 ---
8 name: addi
9 body: |
10 bb.0.entry:
11 liveins: $w0
12 ; CHECK-LABEL: name: addi
13 ; CHECK: liveins: $w0
14 ; CHECK-NEXT: {{ $}}
15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
16 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 273, 12
17 ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32common = ADDWri [[ADDWri]], 3549, 0
18 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[ADDWri1]], 28, 31
19 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
20 ; CHECK-NEXT: RET_ReallyLR implicit $w0
21 %0:gpr32 = COPY $w0
22 %1:gpr32 = MOVi32imm 1121757
23 %2:gpr32 = ADDWrr %0, %1
24 %3:gpr32 = UBFMWri %2, 28, 31
25 $w0 = COPY %3
26 RET_ReallyLR implicit $w0
27 ...
28 ---
29 name: addl
30 body: |
31 bb.0.entry:
32 liveins: $x0
33 ; CHECK-LABEL: name: addl
34 ; CHECK: liveins: $x0
35 ; CHECK-NEXT: {{ $}}
36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
37 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 273, 12
38 ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 0
39 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[ADDXri1]], 28, 31
40 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
41 ; CHECK-NEXT: RET_ReallyLR implicit $x0
42 %0:gpr64 = COPY $x0
43 %1:gpr32 = MOVi32imm 1121757
44 %2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_32
45 %3:gpr64 = ADDXrr %0, killed %2
46 %4:gpr64 = UBFMXri %3, 28, 31
47 $x0 = COPY %4
48 RET_ReallyLR implicit $x0
49 ...
50 ---
51 name: addl_negate
52 body: |
53 bb.0.entry:
54 liveins: $x0
55 ; CHECK-LABEL: name: addl_negate
56 ; CHECK: liveins: $x0
57 ; CHECK-NEXT: {{ $}}
58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
59 ; CHECK-NEXT: [[SUBXri:%[0-9]+]]:gpr64sp = SUBXri [[COPY]], 273, 12
60 ; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 0
61 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBXri1]], 28, 31
62 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
63 ; CHECK-NEXT: RET_ReallyLR implicit $x0
64 %0:gpr64 = COPY $x0
65 %1:gpr64 = MOVi64imm -1121757
66 %2:gpr64 = ADDXrr %0, killed %1
67 %3:gpr64 = UBFMXri %2, 28, 31
68 $x0 = COPY %3
69 RET_ReallyLR implicit $x0
70 ...
71 ---
72 name: add_xzr
73 body: |
74 bb.0.entry:
75 liveins: $x0
76 ; CHECK-LABEL: name: add_xzr
77 ; CHECK: liveins: $x0
78 ; CHECK-NEXT: {{ $}}
79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
80 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
81 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr $xzr, [[MOVi64imm]]
82 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDXrr]]
83 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
84 ; CHECK-NEXT: RET_ReallyLR implicit $x0
85 %0:gpr64 = COPY $x0
86 %2:gpr64 = MOVi64imm -2105098
87 %4:gpr64common = ADDXrr $xzr, %2
88 %3:gpr64 = MADDXrrr %0, %0, %4
89 $x0 = COPY %3
90 RET_ReallyLR implicit $x0
91 ...
92 ---
93 name: sub_xzr
94 body: |
95 bb.0.entry:
96 liveins: $x0
97 ; CHECK-LABEL: name: sub_xzr
98 ; CHECK: liveins: $x0
99 ; CHECK-NEXT: {{ $}}
100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
101 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
102 ; CHECK-NEXT: [[SUBXrr:%[0-9]+]]:gpr64common = SUBXrr $xzr, [[MOVi64imm]]
103 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBXrr]]
104 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
105 ; CHECK-NEXT: RET_ReallyLR implicit $x0
106 %0:gpr64 = COPY $x0
107 %2:gpr64 = MOVi64imm -2105098
108 %4:gpr64common = SUBXrr $xzr, %2
109 %3:gpr64 = MADDXrrr %0, %0, %4
110 $x0 = COPY %3
111 RET_ReallyLR implicit $x0
112 ...
113 ---
114 name: adds_xzr
115 body: |
116 bb.0.entry:
117 liveins: $x0
118 ; CHECK-LABEL: name: adds_xzr
119 ; CHECK: liveins: $x0
120 ; CHECK-NEXT: {{ $}}
121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
122 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
123 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64common = ADDSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv
124 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDSXrr]]
125 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
126 ; CHECK-NEXT: RET_ReallyLR implicit $x0
127 %0:gpr64 = COPY $x0
128 %2:gpr64 = MOVi64imm -2105098
129 %4:gpr64common = ADDSXrr $xzr, %2, implicit-def $nzcv
130 %3:gpr64 = MADDXrrr %0, %0, %4
131 $x0 = COPY %3
132 RET_ReallyLR implicit $x0
133 ...
134 ---
135 name: subs_xzr
136 body: |
137 bb.0.entry:
138 liveins: $x0
139 ; CHECK-LABEL: name: subs_xzr
140 ; CHECK: liveins: $x0
141 ; CHECK-NEXT: {{ $}}
142 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
143 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
144 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64common = SUBSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv
145 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBSXrr]]
146 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
147 ; CHECK-NEXT: RET_ReallyLR implicit $x0
148 %0:gpr64 = COPY $x0
149 %2:gpr64 = MOVi64imm -2105098
150 %4:gpr64common = SUBSXrr $xzr, %2, implicit-def $nzcv
151 %3:gpr64 = MADDXrrr %0, %0, %4
152 $x0 = COPY %3
153 RET_ReallyLR implicit $x0