llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
   3 # RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs %s -o /dev/null 2>&1
   4 ---
   5 name: test_subregs_composition_vreg_1024
   6 tracksRegLiveness: true
   7 body:             |
   8   bb.0:
   9     ; CHECK-LABEL: name: test_subregs_composition_vreg_1024
  10     ; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
  11     ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
  12     ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1
  13     ; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2
  14     ; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
  15     ; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
  16     ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2
  17     ; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3
  18     ; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
  19     ; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
  20     ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3
  21     ; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4
  22     ; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
  23     ; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
  24     ; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4
  25     ; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5
  26     ; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
  27     ; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
  28     ; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5
  29     ; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7
  30     undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
  31     %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
  32     S_NOP 0, implicit %0.sub1_sub2
  33     S_NOP 0, implicit %0.sub2_sub3
  34
  35     undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
  36     %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
  37     S_NOP 0, implicit %1.sub1_sub2_sub3
  38     S_NOP 0, implicit %1.sub2_sub3_sub4
  39
  40     undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec
  41     %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec
  42     S_NOP 0, implicit %2.sub1_sub2_sub3_sub4
  43     S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
  44
  45     undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec
  46     %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec
  47     S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5
  48     S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
  49
  50     undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec
  51     %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec
  52     S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6
  53     S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8
  54 ...
  55 ---
  56 name: test_subregs_unknown_regclass_from_instructions
  57 tracksRegLiveness: true
  58 body:             |
  59   bb.0:
  60     ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions
  61     ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 1
  62     ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 2
  63     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY %2
  64     undef %0.sub4:sgpr_1024 = S_MOV_B32 01
  65     %0.sub5:sgpr_1024 = S_MOV_B32 02
  66     %1:vreg_64 = COPY %0.sub4_sub5
  67 ...
  68 ---
  69 name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
  70 tracksRegLiveness: true
  71 registers:
  72   - { id: 0, class: sgpr_1024 }
  73 body:             |
  74   bb.0:
  75     ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
  76     ; CHECK: dead [[COPY:%[0-9]+]]:vreg_64 = COPY undef %2:sgpr_64
  77     %1:vreg_64 = COPY undef %0.sub4_sub5
  78 ...
  79 ---
  80 name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
  81 tracksRegLiveness: true
  82 body:             |
  83   bb.0:
  84     ; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
  85     ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
  86     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
  87     undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
  88     %2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
  89 ...
  90