| blob | 5fb5a8b1b0350aba1c3661475c12638211dd6ab7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1150 -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx1150 -global-isel -verify-machineinstrs < %s | FileCheck %s
5 define amdgpu_vs float @sitofp_i32_to_f32(i32 inreg %val) {
6 ; CHECK-LABEL: sitofp_i32_to_f32:
7 ; CHECK: ; %bb.0:
8 ; CHECK-NEXT: s_cvt_f32_i32 s0, s0
9 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
10 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
11 ; CHECK-NEXT: ; return to shader part epilog
12 %res = sitofp i32 %val to float
13 ret float %res
14 }
16 define amdgpu_vs float @uitofp_u32_to_f32(i32 inreg %val) {
17 ; CHECK-LABEL: uitofp_u32_to_f32:
18 ; CHECK: ; %bb.0:
19 ; CHECK-NEXT: s_cvt_f32_u32 s0, s0
20 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
21 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
22 ; CHECK-NEXT: ; return to shader part epilog
23 %res = uitofp i32 %val to float
24 ret float %res
25 }
27 define amdgpu_vs i32 @fptosi_f32_to_i32(float inreg %val) {
28 ; CHECK-LABEL: fptosi_f32_to_i32:
29 ; CHECK: ; %bb.0:
30 ; CHECK-NEXT: s_cvt_i32_f32 s0, s0
31 ; CHECK-NEXT: ; return to shader part epilog
32 %res = fptosi float %val to i32
33 ret i32 %res
34 }
36 define amdgpu_vs i32 @fptoui_f32_to_u32(float inreg %val) {
37 ; CHECK-LABEL: fptoui_f32_to_u32:
38 ; CHECK: ; %bb.0:
39 ; CHECK-NEXT: s_cvt_u32_f32 s0, s0
40 ; CHECK-NEXT: ; return to shader part epilog
41 %res = fptoui float %val to i32
42 ret i32 %res
43 }
45 define amdgpu_vs float @fpext_f16_to_f32(half inreg %val) {
46 ; CHECK-LABEL: fpext_f16_to_f32:
47 ; CHECK: ; %bb.0:
48 ; CHECK-NEXT: s_cvt_f32_f16 s0, s0
49 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
50 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
51 ; CHECK-NEXT: ; return to shader part epilog
52 %res = fpext half %val to float
53 ret float %res
54 }
56 define amdgpu_vs float @fpext_hif16_to_32(<2 x half> inreg %val) {
57 ; CHECK-LABEL: fpext_hif16_to_32:
58 ; CHECK: ; %bb.0:
59 ; CHECK-NEXT: s_cvt_hi_f32_f16 s0, s0
60 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
61 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
62 ; CHECK-NEXT: ; return to shader part epilog
63 %hielt = extractelement <2 x half> %val, i32 1
64 %res = fpext half %hielt to float
65 ret float %res
66 }
68 define amdgpu_vs half @fptrunc_f32_to_f16(float inreg %val) {
69 ; CHECK-LABEL: fptrunc_f32_to_f16:
70 ; CHECK: ; %bb.0:
71 ; CHECK-NEXT: s_cvt_f16_f32 s0, s0
72 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
73 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
74 ; CHECK-NEXT: ; return to shader part epilog
75 %res = fptrunc float %val to half
76 ret half %res
77 }
79 define amdgpu_vs float @fceil_f32(float inreg %val) {
80 ; CHECK-LABEL: fceil_f32:
81 ; CHECK: ; %bb.0:
82 ; CHECK-NEXT: s_ceil_f32 s0, s0
83 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
84 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
85 ; CHECK-NEXT: ; return to shader part epilog
86 %res = call float @llvm.ceil.f32(float %val)
87 ret float %res
88 }
90 define amdgpu_vs float @ffloor_f32(float inreg %val) {
91 ; CHECK-LABEL: ffloor_f32:
92 ; CHECK: ; %bb.0:
93 ; CHECK-NEXT: s_floor_f32 s0, s0
94 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
95 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
96 ; CHECK-NEXT: ; return to shader part epilog
97 %res = call float @llvm.floor.f32(float %val)
98 ret float %res
99 }
101 define amdgpu_vs float @ftrunc_f32(float inreg %val) {
102 ; CHECK-LABEL: ftrunc_f32:
103 ; CHECK: ; %bb.0:
104 ; CHECK-NEXT: s_trunc_f32 s0, s0
105 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
106 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
107 ; CHECK-NEXT: ; return to shader part epilog
108 %res = call float @llvm.trunc.f32(float %val)
109 ret float %res
110 }
112 define amdgpu_vs float @frint_f32(float inreg %val) {
113 ; CHECK-LABEL: frint_f32:
114 ; CHECK: ; %bb.0:
115 ; CHECK-NEXT: s_rndne_f32 s0, s0
116 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
117 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
118 ; CHECK-NEXT: ; return to shader part epilog
119 %res = call float @llvm.rint.f32(float %val)
120 ret float %res
121 }
123 define amdgpu_vs half @fceil_f16(half inreg %val) {
124 ; CHECK-LABEL: fceil_f16:
125 ; CHECK: ; %bb.0:
126 ; CHECK-NEXT: s_ceil_f16 s0, s0
127 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
128 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
129 ; CHECK-NEXT: ; return to shader part epilog
130 %res = call half @llvm.ceil.f16(half %val)
131 ret half %res
132 }
134 define amdgpu_vs half @ffloor_f16(half inreg %val) {
135 ; CHECK-LABEL: ffloor_f16:
136 ; CHECK: ; %bb.0:
137 ; CHECK-NEXT: s_floor_f16 s0, s0
138 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
139 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
140 ; CHECK-NEXT: ; return to shader part epilog
141 %res = call half @llvm.floor.f16(half %val)
142 ret half %res
143 }
145 define amdgpu_vs half @ftrunc_f16(half inreg %val) {
146 ; CHECK-LABEL: ftrunc_f16:
147 ; CHECK: ; %bb.0:
148 ; CHECK-NEXT: s_trunc_f16 s0, s0
149 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
150 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
151 ; CHECK-NEXT: ; return to shader part epilog
152 %res = call half @llvm.trunc.f16(half %val)
153 ret half %res
154 }
156 define amdgpu_vs half @frint_f16(half inreg %val) {
157 ; CHECK-LABEL: frint_f16:
158 ; CHECK: ; %bb.0:
159 ; CHECK-NEXT: s_rndne_f16 s0, s0
160 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
161 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
162 ; CHECK-NEXT: ; return to shader part epilog
163 %res = call half @llvm.rint.f16(half %val)
164 ret half %res
165 }
167 declare float @llvm.ceil.f32(float)
168 declare float @llvm.floor.f32(float)
169 declare float @llvm.trunc.f32(float)
170 declare float @llvm.rint.f32(float)
171 declare half @llvm.ceil.f16(half)
172 declare half @llvm.floor.f16(half)
173 declare half @llvm.trunc.f16(half)
174 declare half @llvm.rint.f16(half)