| blob | 7a6640fea2d1e42bacd57485d2806340c8205a1b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-LE
3 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-BE
4 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR8 -implicit-check-not vabsdu
5 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR7 -implicit-check-not vmaxsd
7 define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
8 ; CHECK-PWR9-LABEL: simple_absv_32:
9 ; CHECK-PWR9: # %bb.0: # %entry
10 ; CHECK-PWR9-NEXT: vnegw v3, v2
11 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
12 ; CHECK-PWR9-NEXT: blr
13 ;
14 ; CHECK-PWR78-LABEL: simple_absv_32:
15 ; CHECK-PWR78: # %bb.0: # %entry
16 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
17 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
18 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
19 ; CHECK-PWR78-NEXT: blr
20 entry:
21 %sub.i = sub <4 x i32> zeroinitializer, %a
22 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
23 ret <4 x i32> %0
24 }
26 define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {
27 ; CHECK-PWR9-LABEL: simple_absv_32_swap:
28 ; CHECK-PWR9: # %bb.0: # %entry
29 ; CHECK-PWR9-NEXT: vnegw v3, v2
30 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
31 ; CHECK-PWR9-NEXT: blr
32 ;
33 ; CHECK-PWR78-LABEL: simple_absv_32_swap:
34 ; CHECK-PWR78: # %bb.0: # %entry
35 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
36 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
37 ; CHECK-PWR78-NEXT: vmaxsw v2, v3, v2
38 ; CHECK-PWR78-NEXT: blr
39 entry:
40 %sub.i = sub <4 x i32> zeroinitializer, %a
41 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
42 ret <4 x i32> %0
43 }
45 define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr {
46 ; CHECK-LABEL: simple_absv_16:
47 ; CHECK: # %bb.0: # %entry
48 ; CHECK-NEXT: xxlxor v3, v3, v3
49 ; CHECK-NEXT: vsubuhm v3, v3, v2
50 ; CHECK-NEXT: vmaxsh v2, v2, v3
51 ; CHECK-NEXT: blr
52 entry:
53 %sub.i = sub <8 x i16> zeroinitializer, %a
54 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
55 ret <8 x i16> %0
56 }
58 define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {
59 ; CHECK-LABEL: simple_absv_8:
60 ; CHECK: # %bb.0: # %entry
61 ; CHECK-NEXT: xxlxor v3, v3, v3
62 ; CHECK-NEXT: vsububm v3, v3, v2
63 ; CHECK-NEXT: vmaxsb v2, v2, v3
64 ; CHECK-NEXT: blr
65 entry:
66 %sub.i = sub <16 x i8> zeroinitializer, %a
67 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)
68 ret <16 x i8> %0
69 }
71 ; v2i64 vmax isn't avaiable on pwr7
72 define <2 x i64> @sub_absv_64(<2 x i64> %a, <2 x i64> %b) local_unnamed_addr {
73 ; CHECK-PWR9-LABEL: sub_absv_64:
74 ; CHECK-PWR9: # %bb.0: # %entry
75 ; CHECK-PWR9-NEXT: vsubudm v2, v2, v3
76 ; CHECK-PWR9-NEXT: vnegd v3, v2
77 ; CHECK-PWR9-NEXT: vmaxsd v2, v2, v3
78 ; CHECK-PWR9-NEXT: blr
79 ;
80 ; CHECK-PWR8-LABEL: sub_absv_64:
81 ; CHECK-PWR8: # %bb.0: # %entry
82 ; CHECK-PWR8-NEXT: vsubudm v2, v2, v3
83 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
84 ; CHECK-PWR8-NEXT: vsubudm v3, v3, v2
85 ; CHECK-PWR8-NEXT: vmaxsd v2, v2, v3
86 ; CHECK-PWR8-NEXT: blr
87 ;
88 ; CHECK-PWR7-LABEL: sub_absv_64:
89 ; CHECK-PWR7: # %bb.0: # %entry
90 ; CHECK-PWR7-NEXT: addi r3, r1, -48
91 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r3
92 ; CHECK-PWR7-NEXT: addi r3, r1, -32
93 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r3
94 ; CHECK-PWR7-NEXT: ld r4, -40(r1)
95 ; CHECK-PWR7-NEXT: ld r5, -24(r1)
96 ; CHECK-PWR7-NEXT: ld r3, -48(r1)
97 ; CHECK-PWR7-NEXT: sub r4, r4, r5
98 ; CHECK-PWR7-NEXT: sradi r5, r4, 63
99 ; CHECK-PWR7-NEXT: xor r4, r4, r5
100 ; CHECK-PWR7-NEXT: sub r4, r4, r5
101 ; CHECK-PWR7-NEXT: ld r5, -32(r1)
102 ; CHECK-PWR7-NEXT: std r4, -8(r1)
103 ; CHECK-PWR7-NEXT: sub r3, r3, r5
104 ; CHECK-PWR7-NEXT: sradi r4, r3, 63
105 ; CHECK-PWR7-NEXT: xor r3, r3, r4
106 ; CHECK-PWR7-NEXT: sub r3, r3, r4
107 ; CHECK-PWR7-NEXT: std r3, -16(r1)
108 ; CHECK-PWR7-NEXT: addi r3, r1, -16
109 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r3
110 ; CHECK-PWR7-NEXT: blr
111 entry:
112 %0 = sub nsw <2 x i64> %a, %b
113 %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>
114 %2 = sub <2 x i64> zeroinitializer, %0
115 %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2
116 ret <2 x i64> %3
117 }
119 ; The select pattern can only be detected for v4i32.
120 define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
121 ; CHECK-PWR9-LABEL: sub_absv_32:
122 ; CHECK-PWR9: # %bb.0: # %entry
123 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
124 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
125 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
126 ; CHECK-PWR9-NEXT: blr
127 ;
128 ; CHECK-PWR78-LABEL: sub_absv_32:
129 ; CHECK-PWR78: # %bb.0: # %entry
130 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3
131 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
132 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
133 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
134 ; CHECK-PWR78-NEXT: blr
135 entry:
136 %0 = sub nsw <4 x i32> %a, %b
137 %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>
138 %2 = sub <4 x i32> zeroinitializer, %0
139 %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
140 ret <4 x i32> %3
141 }
143 define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
144 ; CHECK-LABEL: sub_absv_16:
145 ; CHECK: # %bb.0: # %entry
146 ; CHECK-NEXT: vsubuhm v2, v2, v3
147 ; CHECK-NEXT: xxlxor v3, v3, v3
148 ; CHECK-NEXT: vsubuhm v3, v3, v2
149 ; CHECK-NEXT: vmaxsh v2, v2, v3
150 ; CHECK-NEXT: blr
151 entry:
152 %0 = sub nsw <8 x i16> %a, %b
153 %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
154 %2 = sub <8 x i16> zeroinitializer, %0
155 %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2
156 ret <8 x i16> %3
157 }
159 define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
160 ; CHECK-LABEL: sub_absv_8:
161 ; CHECK: # %bb.0: # %entry
162 ; CHECK-NEXT: vsububm v2, v2, v3
163 ; CHECK-NEXT: xxlxor v3, v3, v3
164 ; CHECK-NEXT: vsububm v3, v3, v2
165 ; CHECK-NEXT: vmaxsb v2, v2, v3
166 ; CHECK-NEXT: blr
167 entry:
168 %0 = sub nsw <16 x i8> %a, %b
169 %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
170 %2 = sub <16 x i8> zeroinitializer, %0
171 %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2
172 ret <16 x i8> %3
173 }
175 ; FIXME: This does not produce the ISD::ABS that we are looking for.
176 ; We should fix the missing canonicalization.
177 ; We do manage to find the word version of ABS but not the halfword.
178 ; Threfore, we end up doing more work than is required with a pair of abs for word
179 ; instead of just one for the halfword.
180 define <8 x i16> @sub_absv_16_ext(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
181 ; CHECK-PWR9-LABEL: sub_absv_16_ext:
182 ; CHECK-PWR9: # %bb.0: # %entry
183 ; CHECK-PWR9-NEXT: vmrghh v4, v2, v2
184 ; CHECK-PWR9-NEXT: vmrglh v2, v2, v2
185 ; CHECK-PWR9-NEXT: vmrghh v5, v3, v3
186 ; CHECK-PWR9-NEXT: vmrglh v3, v3, v3
187 ; CHECK-PWR9-NEXT: vextsh2w v2, v2
188 ; CHECK-PWR9-NEXT: vextsh2w v3, v3
189 ; CHECK-PWR9-NEXT: vextsh2w v4, v4
190 ; CHECK-PWR9-NEXT: vextsh2w v5, v5
191 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
192 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
193 ; CHECK-PWR9-NEXT: xvnegsp v4, v4
194 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
195 ; CHECK-PWR9-NEXT: xvnegsp v3, v5
196 ; CHECK-PWR9-NEXT: vabsduw v3, v4, v3
197 ; CHECK-PWR9-NEXT: vpkuwum v2, v3, v2
198 ; CHECK-PWR9-NEXT: blr
199 ;
200 ; CHECK-PWR8-LABEL: sub_absv_16_ext:
201 ; CHECK-PWR8: # %bb.0: # %entry
202 ; CHECK-PWR8-NEXT: vspltisw v4, 8
203 ; CHECK-PWR8-NEXT: vmrglh v5, v2, v2
204 ; CHECK-PWR8-NEXT: vadduwm v4, v4, v4
205 ; CHECK-PWR8-NEXT: vmrghh v2, v2, v2
206 ; CHECK-PWR8-NEXT: vmrglh v0, v3, v3
207 ; CHECK-PWR8-NEXT: vmrghh v3, v3, v3
208 ; CHECK-PWR8-NEXT: vslw v5, v5, v4
209 ; CHECK-PWR8-NEXT: vslw v2, v2, v4
210 ; CHECK-PWR8-NEXT: vslw v0, v0, v4
211 ; CHECK-PWR8-NEXT: vslw v3, v3, v4
212 ; CHECK-PWR8-NEXT: vsraw v5, v5, v4
213 ; CHECK-PWR8-NEXT: vsraw v2, v2, v4
214 ; CHECK-PWR8-NEXT: vsraw v0, v0, v4
215 ; CHECK-PWR8-NEXT: vsraw v3, v3, v4
216 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
217 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
218 ; CHECK-PWR8-NEXT: vsubuwm v3, v5, v0
219 ; CHECK-PWR8-NEXT: vsubuwm v5, v4, v3
220 ; CHECK-PWR8-NEXT: vsubuwm v4, v4, v2
221 ; CHECK-PWR8-NEXT: vmaxsw v3, v3, v5
222 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v4
223 ; CHECK-PWR8-NEXT: vpkuwum v2, v2, v3
224 ; CHECK-PWR8-NEXT: blr
225 ;
226 ; CHECK-PWR7-LABEL: sub_absv_16_ext:
227 ; CHECK-PWR7: # %bb.0: # %entry
228 ; CHECK-PWR7-NEXT: vspltisw v4, 8
229 ; CHECK-PWR7-NEXT: vmrglh v5, v2, v2
230 ; CHECK-PWR7-NEXT: vmrghh v2, v2, v2
231 ; CHECK-PWR7-NEXT: vmrglh v0, v3, v3
232 ; CHECK-PWR7-NEXT: vmrghh v3, v3, v3
233 ; CHECK-PWR7-NEXT: vadduwm v4, v4, v4
234 ; CHECK-PWR7-NEXT: vslw v5, v5, v4
235 ; CHECK-PWR7-NEXT: vslw v2, v2, v4
236 ; CHECK-PWR7-NEXT: vslw v0, v0, v4
237 ; CHECK-PWR7-NEXT: vslw v3, v3, v4
238 ; CHECK-PWR7-NEXT: vsraw v5, v5, v4
239 ; CHECK-PWR7-NEXT: vsraw v2, v2, v4
240 ; CHECK-PWR7-NEXT: vsraw v0, v0, v4
241 ; CHECK-PWR7-NEXT: vsraw v3, v3, v4
242 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
243 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
244 ; CHECK-PWR7-NEXT: vsubuwm v3, v5, v0
245 ; CHECK-PWR7-NEXT: vsubuwm v5, v4, v3
246 ; CHECK-PWR7-NEXT: vsubuwm v4, v4, v2
247 ; CHECK-PWR7-NEXT: vmaxsw v3, v3, v5
248 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v4
249 ; CHECK-PWR7-NEXT: vpkuwum v2, v2, v3
250 ; CHECK-PWR7-NEXT: blr
251 entry:
252 %0 = sext <8 x i16> %a to <8 x i32>
253 %1 = sext <8 x i16> %b to <8 x i32>
254 %2 = sub nsw <8 x i32> %0, %1
255 %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
256 %4 = sub nsw <8 x i32> zeroinitializer, %2
257 %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4
258 %6 = trunc <8 x i32> %5 to <8 x i16>
259 ret <8 x i16> %6
260 }
262 ; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly!
263 ; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8.
264 ; Function Attrs: norecurse nounwind readnone
265 define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
266 ; CHECK-PWR9-LE-LABEL: sub_absv_8_ext:
267 ; CHECK-PWR9-LE: # %bb.0: # %entry
268 ; CHECK-PWR9-LE-NEXT: li r3, 0
269 ; CHECK-PWR9-LE-NEXT: li r5, 2
270 ; CHECK-PWR9-LE-NEXT: li r4, 1
271 ; CHECK-PWR9-LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
272 ; CHECK-PWR9-LE-NEXT: vextubrx r6, r3, v2
273 ; CHECK-PWR9-LE-NEXT: vextubrx r3, r3, v3
274 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r5, v2
275 ; CHECK-PWR9-LE-NEXT: vextubrx r5, r5, v3
276 ; CHECK-PWR9-LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
277 ; CHECK-PWR9-LE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
278 ; CHECK-PWR9-LE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
279 ; CHECK-PWR9-LE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
280 ; CHECK-PWR9-LE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
281 ; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24
282 ; CHECK-PWR9-LE-NEXT: clrlwi r3, r3, 24
283 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
284 ; CHECK-PWR9-LE-NEXT: clrlwi r5, r5, 24
285 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r4, v2
286 ; CHECK-PWR9-LE-NEXT: vextubrx r4, r4, v3
287 ; CHECK-PWR9-LE-NEXT: sub r3, r6, r3
288 ; CHECK-PWR9-LE-NEXT: sub r6, r8, r5
289 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
290 ; CHECK-PWR9-LE-NEXT: clrlwi r4, r4, 24
291 ; CHECK-PWR9-LE-NEXT: sub r4, r7, r4
292 ; CHECK-PWR9-LE-NEXT: srawi r5, r3, 31
293 ; CHECK-PWR9-LE-NEXT: srawi r7, r4, 31
294 ; CHECK-PWR9-LE-NEXT: xor r3, r3, r5
295 ; CHECK-PWR9-LE-NEXT: xor r4, r4, r7
296 ; CHECK-PWR9-LE-NEXT: sub r5, r3, r5
297 ; CHECK-PWR9-LE-NEXT: srawi r3, r6, 31
298 ; CHECK-PWR9-LE-NEXT: sub r4, r4, r7
299 ; CHECK-PWR9-LE-NEXT: xor r6, r6, r3
300 ; CHECK-PWR9-LE-NEXT: sub r3, r6, r3
301 ; CHECK-PWR9-LE-NEXT: li r6, 3
302 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r6, v2
303 ; CHECK-PWR9-LE-NEXT: vextubrx r6, r6, v3
304 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
305 ; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24
306 ; CHECK-PWR9-LE-NEXT: sub r6, r7, r6
307 ; CHECK-PWR9-LE-NEXT: srawi r7, r6, 31
308 ; CHECK-PWR9-LE-NEXT: xor r6, r6, r7
309 ; CHECK-PWR9-LE-NEXT: sub r6, r6, r7
310 ; CHECK-PWR9-LE-NEXT: li r7, 4
311 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r7, v2
312 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r7, v3
313 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r6
314 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
315 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
316 ; CHECK-PWR9-LE-NEXT: sub r7, r8, r7
317 ; CHECK-PWR9-LE-NEXT: srawi r8, r7, 31
318 ; CHECK-PWR9-LE-NEXT: xor r7, r7, r8
319 ; CHECK-PWR9-LE-NEXT: sub r7, r7, r8
320 ; CHECK-PWR9-LE-NEXT: li r8, 5
321 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r8, v2
322 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r8, v3
323 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
324 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
325 ; CHECK-PWR9-LE-NEXT: sub r8, r9, r8
326 ; CHECK-PWR9-LE-NEXT: srawi r9, r8, 31
327 ; CHECK-PWR9-LE-NEXT: xor r8, r8, r9
328 ; CHECK-PWR9-LE-NEXT: sub r8, r8, r9
329 ; CHECK-PWR9-LE-NEXT: li r9, 6
330 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r9, v2
331 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r9, v3
332 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
333 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
334 ; CHECK-PWR9-LE-NEXT: sub r9, r10, r9
335 ; CHECK-PWR9-LE-NEXT: srawi r10, r9, 31
336 ; CHECK-PWR9-LE-NEXT: xor r9, r9, r10
337 ; CHECK-PWR9-LE-NEXT: sub r9, r9, r10
338 ; CHECK-PWR9-LE-NEXT: li r10, 7
339 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r10, v2
340 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r10, v3
341 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
342 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
343 ; CHECK-PWR9-LE-NEXT: sub r10, r11, r10
344 ; CHECK-PWR9-LE-NEXT: srawi r11, r10, 31
345 ; CHECK-PWR9-LE-NEXT: xor r10, r10, r11
346 ; CHECK-PWR9-LE-NEXT: sub r10, r10, r11
347 ; CHECK-PWR9-LE-NEXT: li r11, 8
348 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r11, v2
349 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r11, v3
350 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r10
351 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
352 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
353 ; CHECK-PWR9-LE-NEXT: sub r11, r12, r11
354 ; CHECK-PWR9-LE-NEXT: srawi r12, r11, 31
355 ; CHECK-PWR9-LE-NEXT: xor r11, r11, r12
356 ; CHECK-PWR9-LE-NEXT: sub r11, r11, r12
357 ; CHECK-PWR9-LE-NEXT: li r12, 9
358 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r12, v2
359 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r12, v3
360 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
361 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
362 ; CHECK-PWR9-LE-NEXT: sub r12, r0, r12
363 ; CHECK-PWR9-LE-NEXT: srawi r0, r12, 31
364 ; CHECK-PWR9-LE-NEXT: xor r12, r12, r0
365 ; CHECK-PWR9-LE-NEXT: sub r12, r12, r0
366 ; CHECK-PWR9-LE-NEXT: li r0, 10
367 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r0, v2
368 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r0, v3
369 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
370 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
371 ; CHECK-PWR9-LE-NEXT: sub r0, r30, r0
372 ; CHECK-PWR9-LE-NEXT: srawi r30, r0, 31
373 ; CHECK-PWR9-LE-NEXT: xor r0, r0, r30
374 ; CHECK-PWR9-LE-NEXT: sub r0, r0, r30
375 ; CHECK-PWR9-LE-NEXT: li r30, 11
376 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r30, v2
377 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r30, v3
378 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
379 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
380 ; CHECK-PWR9-LE-NEXT: sub r30, r29, r30
381 ; CHECK-PWR9-LE-NEXT: srawi r29, r30, 31
382 ; CHECK-PWR9-LE-NEXT: xor r30, r30, r29
383 ; CHECK-PWR9-LE-NEXT: sub r30, r30, r29
384 ; CHECK-PWR9-LE-NEXT: li r29, 12
385 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r29, v2
386 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r29, v3
387 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
388 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
389 ; CHECK-PWR9-LE-NEXT: sub r29, r28, r29
390 ; CHECK-PWR9-LE-NEXT: srawi r28, r29, 31
391 ; CHECK-PWR9-LE-NEXT: xor r29, r29, r28
392 ; CHECK-PWR9-LE-NEXT: sub r29, r29, r28
393 ; CHECK-PWR9-LE-NEXT: li r28, 13
394 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r28, v2
395 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r28, v3
396 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
397 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
398 ; CHECK-PWR9-LE-NEXT: sub r28, r27, r28
399 ; CHECK-PWR9-LE-NEXT: srawi r27, r28, 31
400 ; CHECK-PWR9-LE-NEXT: xor r28, r28, r27
401 ; CHECK-PWR9-LE-NEXT: sub r28, r28, r27
402 ; CHECK-PWR9-LE-NEXT: li r27, 14
403 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r27, v2
404 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r27, v3
405 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
406 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
407 ; CHECK-PWR9-LE-NEXT: sub r27, r26, r27
408 ; CHECK-PWR9-LE-NEXT: srawi r26, r27, 31
409 ; CHECK-PWR9-LE-NEXT: xor r27, r27, r26
410 ; CHECK-PWR9-LE-NEXT: sub r27, r27, r26
411 ; CHECK-PWR9-LE-NEXT: li r26, 15
412 ; CHECK-PWR9-LE-NEXT: vextubrx r25, r26, v2
413 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r26, v3
414 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r5
415 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r4
416 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
417 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r3
418 ; CHECK-PWR9-LE-NEXT: clrlwi r25, r25, 24
419 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
420 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
421 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r8
422 ; CHECK-PWR9-LE-NEXT: sub r26, r25, r26
423 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
424 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r7
425 ; CHECK-PWR9-LE-NEXT: srawi r25, r26, 31
426 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
427 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r9
428 ; CHECK-PWR9-LE-NEXT: xor r26, r26, r25
429 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
430 ; CHECK-PWR9-LE-NEXT: sub r26, r26, r25
431 ; CHECK-PWR9-LE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
432 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r26
433 ; CHECK-PWR9-LE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
434 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
435 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r30
436 ; CHECK-PWR9-LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
437 ; CHECK-PWR9-LE-NEXT: xxmrglw vs0, v3, v2
438 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r11
439 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r12
440 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
441 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r0
442 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
443 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r28
444 ; CHECK-PWR9-LE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
445 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
446 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r29
447 ; CHECK-PWR9-LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
448 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
449 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r27
450 ; CHECK-PWR9-LE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
451 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
452 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
453 ; CHECK-PWR9-LE-NEXT: xxmrglw vs1, v3, v2
454 ; CHECK-PWR9-LE-NEXT: xxmrgld v2, vs1, vs0
455 ; CHECK-PWR9-LE-NEXT: blr
456 ;
457 ; CHECK-PWR9-BE-LABEL: sub_absv_8_ext:
458 ; CHECK-PWR9-BE: # %bb.0: # %entry
459 ; CHECK-PWR9-BE-NEXT: li r3, 0
460 ; CHECK-PWR9-BE-NEXT: li r4, 1
461 ; CHECK-PWR9-BE-NEXT: li r5, 2
462 ; CHECK-PWR9-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
463 ; CHECK-PWR9-BE-NEXT: vextublx r6, r3, v2
464 ; CHECK-PWR9-BE-NEXT: vextublx r3, r3, v3
465 ; CHECK-PWR9-BE-NEXT: vextublx r7, r4, v2
466 ; CHECK-PWR9-BE-NEXT: vextublx r4, r4, v3
467 ; CHECK-PWR9-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
468 ; CHECK-PWR9-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
469 ; CHECK-PWR9-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
470 ; CHECK-PWR9-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
471 ; CHECK-PWR9-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
472 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
473 ; CHECK-PWR9-BE-NEXT: clrlwi r3, r3, 24
474 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
475 ; CHECK-PWR9-BE-NEXT: clrlwi r4, r4, 24
476 ; CHECK-PWR9-BE-NEXT: vextublx r8, r5, v2
477 ; CHECK-PWR9-BE-NEXT: vextublx r5, r5, v3
478 ; CHECK-PWR9-BE-NEXT: sub r3, r6, r3
479 ; CHECK-PWR9-BE-NEXT: sub r4, r7, r4
480 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
481 ; CHECK-PWR9-BE-NEXT: clrlwi r5, r5, 24
482 ; CHECK-PWR9-BE-NEXT: sub r5, r8, r5
483 ; CHECK-PWR9-BE-NEXT: srawi r6, r3, 31
484 ; CHECK-PWR9-BE-NEXT: srawi r7, r4, 31
485 ; CHECK-PWR9-BE-NEXT: srawi r8, r5, 31
486 ; CHECK-PWR9-BE-NEXT: xor r3, r3, r6
487 ; CHECK-PWR9-BE-NEXT: xor r4, r4, r7
488 ; CHECK-PWR9-BE-NEXT: xor r5, r5, r8
489 ; CHECK-PWR9-BE-NEXT: sub r3, r3, r6
490 ; CHECK-PWR9-BE-NEXT: li r6, 3
491 ; CHECK-PWR9-BE-NEXT: sub r4, r4, r7
492 ; CHECK-PWR9-BE-NEXT: sub r5, r5, r8
493 ; CHECK-PWR9-BE-NEXT: vextublx r7, r6, v2
494 ; CHECK-PWR9-BE-NEXT: vextublx r6, r6, v3
495 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
496 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
497 ; CHECK-PWR9-BE-NEXT: sub r6, r7, r6
498 ; CHECK-PWR9-BE-NEXT: srawi r7, r6, 31
499 ; CHECK-PWR9-BE-NEXT: xor r6, r6, r7
500 ; CHECK-PWR9-BE-NEXT: sub r6, r6, r7
501 ; CHECK-PWR9-BE-NEXT: li r7, 4
502 ; CHECK-PWR9-BE-NEXT: vextublx r8, r7, v2
503 ; CHECK-PWR9-BE-NEXT: vextublx r7, r7, v3
504 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
505 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
506 ; CHECK-PWR9-BE-NEXT: sub r7, r8, r7
507 ; CHECK-PWR9-BE-NEXT: srawi r8, r7, 31
508 ; CHECK-PWR9-BE-NEXT: xor r7, r7, r8
509 ; CHECK-PWR9-BE-NEXT: sub r7, r7, r8
510 ; CHECK-PWR9-BE-NEXT: li r8, 5
511 ; CHECK-PWR9-BE-NEXT: vextublx r9, r8, v2
512 ; CHECK-PWR9-BE-NEXT: vextublx r8, r8, v3
513 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
514 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
515 ; CHECK-PWR9-BE-NEXT: sub r8, r9, r8
516 ; CHECK-PWR9-BE-NEXT: srawi r9, r8, 31
517 ; CHECK-PWR9-BE-NEXT: xor r8, r8, r9
518 ; CHECK-PWR9-BE-NEXT: sub r8, r8, r9
519 ; CHECK-PWR9-BE-NEXT: li r9, 6
520 ; CHECK-PWR9-BE-NEXT: vextublx r10, r9, v2
521 ; CHECK-PWR9-BE-NEXT: vextublx r9, r9, v3
522 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
523 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
524 ; CHECK-PWR9-BE-NEXT: sub r9, r10, r9
525 ; CHECK-PWR9-BE-NEXT: srawi r10, r9, 31
526 ; CHECK-PWR9-BE-NEXT: xor r9, r9, r10
527 ; CHECK-PWR9-BE-NEXT: sub r9, r9, r10
528 ; CHECK-PWR9-BE-NEXT: li r10, 7
529 ; CHECK-PWR9-BE-NEXT: vextublx r11, r10, v2
530 ; CHECK-PWR9-BE-NEXT: vextublx r10, r10, v3
531 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r9
532 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
533 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
534 ; CHECK-PWR9-BE-NEXT: sub r10, r11, r10
535 ; CHECK-PWR9-BE-NEXT: srawi r11, r10, 31
536 ; CHECK-PWR9-BE-NEXT: xor r10, r10, r11
537 ; CHECK-PWR9-BE-NEXT: sub r10, r10, r11
538 ; CHECK-PWR9-BE-NEXT: li r11, 8
539 ; CHECK-PWR9-BE-NEXT: vextublx r12, r11, v2
540 ; CHECK-PWR9-BE-NEXT: vextublx r11, r11, v3
541 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
542 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
543 ; CHECK-PWR9-BE-NEXT: sub r11, r12, r11
544 ; CHECK-PWR9-BE-NEXT: srawi r12, r11, 31
545 ; CHECK-PWR9-BE-NEXT: xor r11, r11, r12
546 ; CHECK-PWR9-BE-NEXT: sub r11, r11, r12
547 ; CHECK-PWR9-BE-NEXT: li r12, 9
548 ; CHECK-PWR9-BE-NEXT: vextublx r0, r12, v2
549 ; CHECK-PWR9-BE-NEXT: vextublx r12, r12, v3
550 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
551 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
552 ; CHECK-PWR9-BE-NEXT: sub r12, r0, r12
553 ; CHECK-PWR9-BE-NEXT: srawi r0, r12, 31
554 ; CHECK-PWR9-BE-NEXT: xor r12, r12, r0
555 ; CHECK-PWR9-BE-NEXT: sub r12, r12, r0
556 ; CHECK-PWR9-BE-NEXT: li r0, 10
557 ; CHECK-PWR9-BE-NEXT: vextublx r30, r0, v2
558 ; CHECK-PWR9-BE-NEXT: vextublx r0, r0, v3
559 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r12
560 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
561 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
562 ; CHECK-PWR9-BE-NEXT: sub r0, r30, r0
563 ; CHECK-PWR9-BE-NEXT: srawi r30, r0, 31
564 ; CHECK-PWR9-BE-NEXT: xor r0, r0, r30
565 ; CHECK-PWR9-BE-NEXT: sub r0, r0, r30
566 ; CHECK-PWR9-BE-NEXT: li r30, 11
567 ; CHECK-PWR9-BE-NEXT: vextublx r29, r30, v2
568 ; CHECK-PWR9-BE-NEXT: vextublx r30, r30, v3
569 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
570 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
571 ; CHECK-PWR9-BE-NEXT: sub r30, r29, r30
572 ; CHECK-PWR9-BE-NEXT: srawi r29, r30, 31
573 ; CHECK-PWR9-BE-NEXT: xor r30, r30, r29
574 ; CHECK-PWR9-BE-NEXT: sub r30, r30, r29
575 ; CHECK-PWR9-BE-NEXT: li r29, 12
576 ; CHECK-PWR9-BE-NEXT: vextublx r28, r29, v2
577 ; CHECK-PWR9-BE-NEXT: vextublx r29, r29, v3
578 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
579 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
580 ; CHECK-PWR9-BE-NEXT: sub r29, r28, r29
581 ; CHECK-PWR9-BE-NEXT: srawi r28, r29, 31
582 ; CHECK-PWR9-BE-NEXT: xor r29, r29, r28
583 ; CHECK-PWR9-BE-NEXT: sub r29, r29, r28
584 ; CHECK-PWR9-BE-NEXT: li r28, 13
585 ; CHECK-PWR9-BE-NEXT: vextublx r27, r28, v2
586 ; CHECK-PWR9-BE-NEXT: vextublx r28, r28, v3
587 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
588 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
589 ; CHECK-PWR9-BE-NEXT: sub r28, r27, r28
590 ; CHECK-PWR9-BE-NEXT: srawi r27, r28, 31
591 ; CHECK-PWR9-BE-NEXT: xor r28, r28, r27
592 ; CHECK-PWR9-BE-NEXT: sub r28, r28, r27
593 ; CHECK-PWR9-BE-NEXT: li r27, 14
594 ; CHECK-PWR9-BE-NEXT: vextublx r26, r27, v2
595 ; CHECK-PWR9-BE-NEXT: vextublx r27, r27, v3
596 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
597 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
598 ; CHECK-PWR9-BE-NEXT: sub r27, r26, r27
599 ; CHECK-PWR9-BE-NEXT: srawi r26, r27, 31
600 ; CHECK-PWR9-BE-NEXT: xor r27, r27, r26
601 ; CHECK-PWR9-BE-NEXT: sub r27, r27, r26
602 ; CHECK-PWR9-BE-NEXT: li r26, 15
603 ; CHECK-PWR9-BE-NEXT: vextublx r25, r26, v2
604 ; CHECK-PWR9-BE-NEXT: vextublx r26, r26, v3
605 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r27
606 ; CHECK-PWR9-BE-NEXT: addis r27, r2, .LCPI9_0@toc@ha
607 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28
608 ; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
609 ; CHECK-PWR9-BE-NEXT: addi r27, r27, .LCPI9_0@toc@l
610 ; CHECK-PWR9-BE-NEXT: clrlwi r25, r25, 24
611 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
612 ; CHECK-PWR9-BE-NEXT: lxv vs1, 0(r27)
613 ; CHECK-PWR9-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
614 ; CHECK-PWR9-BE-NEXT: sub r26, r25, r26
615 ; CHECK-PWR9-BE-NEXT: srawi r25, r26, 31
616 ; CHECK-PWR9-BE-NEXT: xor r26, r26, r25
617 ; CHECK-PWR9-BE-NEXT: sub r26, r26, r25
618 ; CHECK-PWR9-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
619 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r26
620 ; CHECK-PWR9-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
621 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs0, vs1
622 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r29
623 ; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
624 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
625 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r0
626 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
627 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r30
628 ; CHECK-PWR9-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
629 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
630 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r11
631 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs0, vs1
632 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
633 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r4
634 ; CHECK-PWR9-BE-NEXT: xxmrghw vs0, v3, v2
635 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r10
636 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r8
637 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs2, vs1
638 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r7
639 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
640 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r5
641 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
642 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r6
643 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
644 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r3
645 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs2, vs1
646 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
647 ; CHECK-PWR9-BE-NEXT: xxmrghw vs1, v3, v2
648 ; CHECK-PWR9-BE-NEXT: xxmrghd v2, vs1, vs0
649 ; CHECK-PWR9-BE-NEXT: blr
650 ;
651 ; CHECK-PWR8-LABEL: sub_absv_8_ext:
652 ; CHECK-PWR8: # %bb.0: # %entry
653 ; CHECK-PWR8-NEXT: xxswapd vs0, v2
654 ; CHECK-PWR8-NEXT: xxswapd vs1, v3
655 ; CHECK-PWR8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
656 ; CHECK-PWR8-NEXT: std r28, -32(r1) # 8-byte Folded Spill
657 ; CHECK-PWR8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
658 ; CHECK-PWR8-NEXT: std r26, -48(r1) # 8-byte Folded Spill
659 ; CHECK-PWR8-NEXT: mffprd r11, f0
660 ; CHECK-PWR8-NEXT: mffprd r8, f1
661 ; CHECK-PWR8-NEXT: std r27, -40(r1) # 8-byte Folded Spill
662 ; CHECK-PWR8-NEXT: std r25, -56(r1) # 8-byte Folded Spill
663 ; CHECK-PWR8-NEXT: clrldi r3, r11, 56
664 ; CHECK-PWR8-NEXT: clrldi r4, r8, 56
665 ; CHECK-PWR8-NEXT: rldicl r5, r11, 56, 56
666 ; CHECK-PWR8-NEXT: rldicl r6, r8, 56, 56
667 ; CHECK-PWR8-NEXT: rldicl r7, r11, 48, 56
668 ; CHECK-PWR8-NEXT: rldicl r9, r8, 48, 56
669 ; CHECK-PWR8-NEXT: rldicl r0, r11, 32, 56
670 ; CHECK-PWR8-NEXT: rldicl r30, r8, 32, 56
671 ; CHECK-PWR8-NEXT: rldicl r29, r11, 24, 56
672 ; CHECK-PWR8-NEXT: rldicl r28, r8, 24, 56
673 ; CHECK-PWR8-NEXT: rldicl r10, r11, 40, 56
674 ; CHECK-PWR8-NEXT: rldicl r12, r8, 40, 56
675 ; CHECK-PWR8-NEXT: rldicl r27, r11, 16, 56
676 ; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56
677 ; CHECK-PWR8-NEXT: std r24, -64(r1) # 8-byte Folded Spill
678 ; CHECK-PWR8-NEXT: clrlwi r3, r3, 24
679 ; CHECK-PWR8-NEXT: clrlwi r4, r4, 24
680 ; CHECK-PWR8-NEXT: clrlwi r5, r5, 24
681 ; CHECK-PWR8-NEXT: clrlwi r6, r6, 24
682 ; CHECK-PWR8-NEXT: clrlwi r7, r7, 24
683 ; CHECK-PWR8-NEXT: clrlwi r9, r9, 24
684 ; CHECK-PWR8-NEXT: sub r3, r3, r4
685 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
686 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
687 ; CHECK-PWR8-NEXT: sub r4, r5, r6
688 ; CHECK-PWR8-NEXT: sub r5, r7, r9
689 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
690 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
691 ; CHECK-PWR8-NEXT: sub r7, r0, r30
692 ; CHECK-PWR8-NEXT: sub r9, r29, r28
693 ; CHECK-PWR8-NEXT: clrlwi r10, r10, 24
694 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
695 ; CHECK-PWR8-NEXT: sub r6, r10, r12
696 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
697 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
698 ; CHECK-PWR8-NEXT: srawi r0, r5, 31
699 ; CHECK-PWR8-NEXT: srawi r29, r7, 31
700 ; CHECK-PWR8-NEXT: srawi r12, r4, 31
701 ; CHECK-PWR8-NEXT: srawi r28, r9, 31
702 ; CHECK-PWR8-NEXT: srawi r30, r6, 31
703 ; CHECK-PWR8-NEXT: srawi r10, r3, 31
704 ; CHECK-PWR8-NEXT: xor r5, r5, r0
705 ; CHECK-PWR8-NEXT: xor r26, r7, r29
706 ; CHECK-PWR8-NEXT: sub r7, r5, r0
707 ; CHECK-PWR8-NEXT: rldicl r5, r8, 16, 56
708 ; CHECK-PWR8-NEXT: rldicl r8, r8, 8, 56
709 ; CHECK-PWR8-NEXT: xor r4, r4, r12
710 ; CHECK-PWR8-NEXT: xor r25, r9, r28
711 ; CHECK-PWR8-NEXT: sub r9, r4, r12
712 ; CHECK-PWR8-NEXT: sub r4, r26, r29
713 ; CHECK-PWR8-NEXT: mtvsrd v1, r9
714 ; CHECK-PWR8-NEXT: clrlwi r5, r5, 24
715 ; CHECK-PWR8-NEXT: sub r5, r27, r5
716 ; CHECK-PWR8-NEXT: clrlwi r8, r8, 24
717 ; CHECK-PWR8-NEXT: sub r8, r11, r8
718 ; CHECK-PWR8-NEXT: xor r6, r6, r30
719 ; CHECK-PWR8-NEXT: sub r6, r6, r30
720 ; CHECK-PWR8-NEXT: xor r3, r3, r10
721 ; CHECK-PWR8-NEXT: sub r10, r3, r10
722 ; CHECK-PWR8-NEXT: sub r3, r25, r28
723 ; CHECK-PWR8-NEXT: mtvsrd v6, r6
724 ; CHECK-PWR8-NEXT: mtvsrd v7, r3
725 ; CHECK-PWR8-NEXT: srawi r12, r5, 31
726 ; CHECK-PWR8-NEXT: srawi r11, r8, 31
727 ; CHECK-PWR8-NEXT: xor r5, r5, r12
728 ; CHECK-PWR8-NEXT: xor r8, r8, r11
729 ; CHECK-PWR8-NEXT: sub r5, r5, r12
730 ; CHECK-PWR8-NEXT: sub r8, r8, r11
731 ; CHECK-PWR8-NEXT: mfvsrd r11, v2
732 ; CHECK-PWR8-NEXT: mfvsrd r12, v3
733 ; CHECK-PWR8-NEXT: mtvsrd v8, r8
734 ; CHECK-PWR8-NEXT: clrldi r0, r11, 56
735 ; CHECK-PWR8-NEXT: clrldi r30, r12, 56
736 ; CHECK-PWR8-NEXT: rldicl r29, r12, 56, 56
737 ; CHECK-PWR8-NEXT: rldicl r28, r12, 48, 56
738 ; CHECK-PWR8-NEXT: rldicl r27, r12, 40, 56
739 ; CHECK-PWR8-NEXT: rldicl r26, r12, 32, 56
740 ; CHECK-PWR8-NEXT: rldicl r25, r12, 24, 56
741 ; CHECK-PWR8-NEXT: rldicl r24, r12, 16, 56
742 ; CHECK-PWR8-NEXT: rldicl r12, r12, 8, 56
743 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
744 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
745 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
746 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
747 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
748 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
749 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
750 ; CHECK-PWR8-NEXT: clrlwi r24, r24, 24
751 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
752 ; CHECK-PWR8-NEXT: sub r0, r0, r30
753 ; CHECK-PWR8-NEXT: srawi r30, r0, 31
754 ; CHECK-PWR8-NEXT: xor r0, r0, r30
755 ; CHECK-PWR8-NEXT: sub r0, r0, r30
756 ; CHECK-PWR8-NEXT: rldicl r30, r11, 56, 56
757 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
758 ; CHECK-PWR8-NEXT: mtvsrd v2, r0
759 ; CHECK-PWR8-NEXT: sub r30, r30, r29
760 ; CHECK-PWR8-NEXT: srawi r29, r30, 31
761 ; CHECK-PWR8-NEXT: xor r30, r30, r29
762 ; CHECK-PWR8-NEXT: sub r30, r30, r29
763 ; CHECK-PWR8-NEXT: rldicl r29, r11, 48, 56
764 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
765 ; CHECK-PWR8-NEXT: mtvsrd v3, r30
766 ; CHECK-PWR8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
767 ; CHECK-PWR8-NEXT: sub r29, r29, r28
768 ; CHECK-PWR8-NEXT: srawi r28, r29, 31
769 ; CHECK-PWR8-NEXT: xor r29, r29, r28
770 ; CHECK-PWR8-NEXT: sub r29, r29, r28
771 ; CHECK-PWR8-NEXT: rldicl r28, r11, 40, 56
772 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
773 ; CHECK-PWR8-NEXT: sub r28, r28, r27
774 ; CHECK-PWR8-NEXT: srawi r27, r28, 31
775 ; CHECK-PWR8-NEXT: xor r28, r28, r27
776 ; CHECK-PWR8-NEXT: sub r28, r28, r27
777 ; CHECK-PWR8-NEXT: rldicl r27, r11, 32, 56
778 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
779 ; CHECK-PWR8-NEXT: mtvsrd v4, r28
780 ; CHECK-PWR8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
781 ; CHECK-PWR8-NEXT: sub r27, r27, r26
782 ; CHECK-PWR8-NEXT: srawi r26, r27, 31
783 ; CHECK-PWR8-NEXT: xor r27, r27, r26
784 ; CHECK-PWR8-NEXT: sub r27, r27, r26
785 ; CHECK-PWR8-NEXT: rldicl r26, r11, 24, 56
786 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
787 ; CHECK-PWR8-NEXT: sub r26, r26, r25
788 ; CHECK-PWR8-NEXT: srawi r25, r26, 31
789 ; CHECK-PWR8-NEXT: xor r26, r26, r25
790 ; CHECK-PWR8-NEXT: sub r26, r26, r25
791 ; CHECK-PWR8-NEXT: rldicl r25, r11, 16, 56
792 ; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56
793 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
794 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
795 ; CHECK-PWR8-NEXT: mtvsrd v5, r26
796 ; CHECK-PWR8-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
797 ; CHECK-PWR8-NEXT: sub r25, r25, r24
798 ; CHECK-PWR8-NEXT: sub r11, r11, r12
799 ; CHECK-PWR8-NEXT: srawi r24, r25, 31
800 ; CHECK-PWR8-NEXT: srawi r12, r11, 31
801 ; CHECK-PWR8-NEXT: xor r25, r25, r24
802 ; CHECK-PWR8-NEXT: xor r11, r11, r12
803 ; CHECK-PWR8-NEXT: sub r25, r25, r24
804 ; CHECK-PWR8-NEXT: sub r11, r11, r12
805 ; CHECK-PWR8-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
806 ; CHECK-PWR8-NEXT: mtvsrd v0, r11
807 ; CHECK-PWR8-NEXT: vmrghb v2, v3, v2
808 ; CHECK-PWR8-NEXT: mtvsrd v3, r29
809 ; CHECK-PWR8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
810 ; CHECK-PWR8-NEXT: vmrghb v3, v4, v3
811 ; CHECK-PWR8-NEXT: mtvsrd v4, r27
812 ; CHECK-PWR8-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
813 ; CHECK-PWR8-NEXT: vmrglh v2, v3, v2
814 ; CHECK-PWR8-NEXT: vmrghb v4, v5, v4
815 ; CHECK-PWR8-NEXT: mtvsrd v5, r25
816 ; CHECK-PWR8-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
817 ; CHECK-PWR8-NEXT: vmrghb v5, v0, v5
818 ; CHECK-PWR8-NEXT: mtvsrd v0, r10
819 ; CHECK-PWR8-NEXT: vmrglh v3, v5, v4
820 ; CHECK-PWR8-NEXT: xxmrglw vs0, v3, v2
821 ; CHECK-PWR8-NEXT: vmrghb v0, v1, v0
822 ; CHECK-PWR8-NEXT: mtvsrd v1, r7
823 ; CHECK-PWR8-NEXT: vmrghb v1, v6, v1
824 ; CHECK-PWR8-NEXT: mtvsrd v6, r4
825 ; CHECK-PWR8-NEXT: vmrglh v4, v1, v0
826 ; CHECK-PWR8-NEXT: vmrghb v6, v7, v6
827 ; CHECK-PWR8-NEXT: mtvsrd v7, r5
828 ; CHECK-PWR8-NEXT: vmrghb v7, v8, v7
829 ; CHECK-PWR8-NEXT: vmrglh v5, v7, v6
830 ; CHECK-PWR8-NEXT: xxmrglw vs1, v5, v4
831 ; CHECK-PWR8-NEXT: xxmrgld v2, vs0, vs1
832 ; CHECK-PWR8-NEXT: blr
833 ;
834 ; CHECK-PWR7-LABEL: sub_absv_8_ext:
835 ; CHECK-PWR7: # %bb.0: # %entry
836 ; CHECK-PWR7-NEXT: stdu r1, -400(r1)
837 ; CHECK-PWR7-NEXT: .cfi_def_cfa_offset 400
838 ; CHECK-PWR7-NEXT: .cfi_offset r24, -64
839 ; CHECK-PWR7-NEXT: .cfi_offset r25, -56
840 ; CHECK-PWR7-NEXT: .cfi_offset r26, -48
841 ; CHECK-PWR7-NEXT: .cfi_offset r27, -40
842 ; CHECK-PWR7-NEXT: .cfi_offset r28, -32
843 ; CHECK-PWR7-NEXT: .cfi_offset r29, -24
844 ; CHECK-PWR7-NEXT: .cfi_offset r30, -16
845 ; CHECK-PWR7-NEXT: addi r3, r1, 304
846 ; CHECK-PWR7-NEXT: std r24, 336(r1) # 8-byte Folded Spill
847 ; CHECK-PWR7-NEXT: std r25, 344(r1) # 8-byte Folded Spill
848 ; CHECK-PWR7-NEXT: std r26, 352(r1) # 8-byte Folded Spill
849 ; CHECK-PWR7-NEXT: std r27, 360(r1) # 8-byte Folded Spill
850 ; CHECK-PWR7-NEXT: std r28, 368(r1) # 8-byte Folded Spill
851 ; CHECK-PWR7-NEXT: std r29, 376(r1) # 8-byte Folded Spill
852 ; CHECK-PWR7-NEXT: std r30, 384(r1) # 8-byte Folded Spill
853 ; CHECK-PWR7-NEXT: stxvw4x v2, 0, r3
854 ; CHECK-PWR7-NEXT: addi r3, r1, 320
855 ; CHECK-PWR7-NEXT: lbz r4, 304(r1)
856 ; CHECK-PWR7-NEXT: stxvw4x v3, 0, r3
857 ; CHECK-PWR7-NEXT: lbz r5, 305(r1)
858 ; CHECK-PWR7-NEXT: lbz r6, 321(r1)
859 ; CHECK-PWR7-NEXT: lbz r7, 306(r1)
860 ; CHECK-PWR7-NEXT: lbz r8, 322(r1)
861 ; CHECK-PWR7-NEXT: lbz r9, 307(r1)
862 ; CHECK-PWR7-NEXT: lbz r10, 323(r1)
863 ; CHECK-PWR7-NEXT: lbz r0, 309(r1)
864 ; CHECK-PWR7-NEXT: lbz r30, 325(r1)
865 ; CHECK-PWR7-NEXT: lbz r29, 310(r1)
866 ; CHECK-PWR7-NEXT: lbz r28, 326(r1)
867 ; CHECK-PWR7-NEXT: lbz r11, 308(r1)
868 ; CHECK-PWR7-NEXT: lbz r12, 324(r1)
869 ; CHECK-PWR7-NEXT: lbz r27, 311(r1)
870 ; CHECK-PWR7-NEXT: lbz r26, 327(r1)
871 ; CHECK-PWR7-NEXT: lbz r25, 312(r1)
872 ; CHECK-PWR7-NEXT: sub r5, r5, r6
873 ; CHECK-PWR7-NEXT: sub r6, r7, r8
874 ; CHECK-PWR7-NEXT: sub r7, r9, r10
875 ; CHECK-PWR7-NEXT: sub r9, r0, r30
876 ; CHECK-PWR7-NEXT: sub r10, r29, r28
877 ; CHECK-PWR7-NEXT: sub r8, r11, r12
878 ; CHECK-PWR7-NEXT: srawi r0, r5, 31
879 ; CHECK-PWR7-NEXT: srawi r30, r6, 31
880 ; CHECK-PWR7-NEXT: srawi r29, r7, 31
881 ; CHECK-PWR7-NEXT: srawi r28, r8, 31
882 ; CHECK-PWR7-NEXT: sub r11, r27, r26
883 ; CHECK-PWR7-NEXT: srawi r27, r9, 31
884 ; CHECK-PWR7-NEXT: lbz r24, 328(r1)
885 ; CHECK-PWR7-NEXT: xor r5, r5, r0
886 ; CHECK-PWR7-NEXT: xor r6, r6, r30
887 ; CHECK-PWR7-NEXT: xor r7, r7, r29
888 ; CHECK-PWR7-NEXT: xor r8, r8, r28
889 ; CHECK-PWR7-NEXT: xor r9, r9, r27
890 ; CHECK-PWR7-NEXT: srawi r26, r10, 31
891 ; CHECK-PWR7-NEXT: sub r5, r5, r0
892 ; CHECK-PWR7-NEXT: sub r6, r6, r30
893 ; CHECK-PWR7-NEXT: lbz r0, 313(r1)
894 ; CHECK-PWR7-NEXT: lbz r30, 329(r1)
895 ; CHECK-PWR7-NEXT: sub r7, r7, r29
896 ; CHECK-PWR7-NEXT: lbz r29, 330(r1)
897 ; CHECK-PWR7-NEXT: sub r8, r8, r28
898 ; CHECK-PWR7-NEXT: lbz r28, 331(r1)
899 ; CHECK-PWR7-NEXT: sub r9, r9, r27
900 ; CHECK-PWR7-NEXT: lbz r27, 332(r1)
901 ; CHECK-PWR7-NEXT: xor r10, r10, r26
902 ; CHECK-PWR7-NEXT: sub r10, r10, r26
903 ; CHECK-PWR7-NEXT: lbz r26, 333(r1)
904 ; CHECK-PWR7-NEXT: sub r12, r25, r24
905 ; CHECK-PWR7-NEXT: srawi r25, r11, 31
906 ; CHECK-PWR7-NEXT: lbz r3, 320(r1)
907 ; CHECK-PWR7-NEXT: sub r0, r0, r30
908 ; CHECK-PWR7-NEXT: xor r11, r11, r25
909 ; CHECK-PWR7-NEXT: sub r11, r11, r25
910 ; CHECK-PWR7-NEXT: lbz r25, 334(r1)
911 ; CHECK-PWR7-NEXT: sub r4, r4, r3
912 ; CHECK-PWR7-NEXT: srawi r30, r0, 31
913 ; CHECK-PWR7-NEXT: srawi r24, r12, 31
914 ; CHECK-PWR7-NEXT: xor r12, r12, r24
915 ; CHECK-PWR7-NEXT: sub r12, r12, r24
916 ; CHECK-PWR7-NEXT: lbz r24, 335(r1)
917 ; CHECK-PWR7-NEXT: srawi r3, r4, 31
918 ; CHECK-PWR7-NEXT: xor r4, r4, r3
919 ; CHECK-PWR7-NEXT: xor r0, r0, r30
920 ; CHECK-PWR7-NEXT: sub r3, r4, r3
921 ; CHECK-PWR7-NEXT: stb r3, 48(r1)
922 ; CHECK-PWR7-NEXT: addi r3, r1, 288
923 ; CHECK-PWR7-NEXT: stb r12, 176(r1)
924 ; CHECK-PWR7-NEXT: sub r0, r0, r30
925 ; CHECK-PWR7-NEXT: lbz r30, 314(r1)
926 ; CHECK-PWR7-NEXT: stb r11, 160(r1)
927 ; CHECK-PWR7-NEXT: sub r30, r30, r29
928 ; CHECK-PWR7-NEXT: stb r0, 192(r1)
929 ; CHECK-PWR7-NEXT: stb r10, 144(r1)
930 ; CHECK-PWR7-NEXT: stb r9, 128(r1)
931 ; CHECK-PWR7-NEXT: stb r8, 112(r1)
932 ; CHECK-PWR7-NEXT: stb r7, 96(r1)
933 ; CHECK-PWR7-NEXT: stb r6, 80(r1)
934 ; CHECK-PWR7-NEXT: srawi r29, r30, 31
935 ; CHECK-PWR7-NEXT: stb r5, 64(r1)
936 ; CHECK-PWR7-NEXT: xor r30, r30, r29
937 ; CHECK-PWR7-NEXT: sub r30, r30, r29
938 ; CHECK-PWR7-NEXT: lbz r29, 315(r1)
939 ; CHECK-PWR7-NEXT: sub r29, r29, r28
940 ; CHECK-PWR7-NEXT: stb r30, 208(r1)
941 ; CHECK-PWR7-NEXT: ld r30, 384(r1) # 8-byte Folded Reload
942 ; CHECK-PWR7-NEXT: srawi r28, r29, 31
943 ; CHECK-PWR7-NEXT: xor r29, r29, r28
944 ; CHECK-PWR7-NEXT: sub r29, r29, r28
945 ; CHECK-PWR7-NEXT: lbz r28, 316(r1)
946 ; CHECK-PWR7-NEXT: sub r28, r28, r27
947 ; CHECK-PWR7-NEXT: stb r29, 224(r1)
948 ; CHECK-PWR7-NEXT: ld r29, 376(r1) # 8-byte Folded Reload
949 ; CHECK-PWR7-NEXT: srawi r27, r28, 31
950 ; CHECK-PWR7-NEXT: xor r28, r28, r27
951 ; CHECK-PWR7-NEXT: sub r28, r28, r27
952 ; CHECK-PWR7-NEXT: lbz r27, 317(r1)
953 ; CHECK-PWR7-NEXT: sub r27, r27, r26
954 ; CHECK-PWR7-NEXT: stb r28, 240(r1)
955 ; CHECK-PWR7-NEXT: ld r28, 368(r1) # 8-byte Folded Reload
956 ; CHECK-PWR7-NEXT: srawi r26, r27, 31
957 ; CHECK-PWR7-NEXT: xor r27, r27, r26
958 ; CHECK-PWR7-NEXT: sub r27, r27, r26
959 ; CHECK-PWR7-NEXT: lbz r26, 318(r1)
960 ; CHECK-PWR7-NEXT: sub r26, r26, r25
961 ; CHECK-PWR7-NEXT: stb r27, 256(r1)
962 ; CHECK-PWR7-NEXT: ld r27, 360(r1) # 8-byte Folded Reload
963 ; CHECK-PWR7-NEXT: srawi r25, r26, 31
964 ; CHECK-PWR7-NEXT: xor r26, r26, r25
965 ; CHECK-PWR7-NEXT: sub r26, r26, r25
966 ; CHECK-PWR7-NEXT: lbz r25, 319(r1)
967 ; CHECK-PWR7-NEXT: sub r25, r25, r24
968 ; CHECK-PWR7-NEXT: stb r26, 272(r1)
969 ; CHECK-PWR7-NEXT: ld r26, 352(r1) # 8-byte Folded Reload
970 ; CHECK-PWR7-NEXT: srawi r24, r25, 31
971 ; CHECK-PWR7-NEXT: xor r25, r25, r24
972 ; CHECK-PWR7-NEXT: sub r25, r25, r24
973 ; CHECK-PWR7-NEXT: ld r24, 336(r1) # 8-byte Folded Reload
974 ; CHECK-PWR7-NEXT: stb r25, 288(r1)
975 ; CHECK-PWR7-NEXT: ld r25, 344(r1) # 8-byte Folded Reload
976 ; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3
977 ; CHECK-PWR7-NEXT: addi r3, r1, 272
978 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
979 ; CHECK-PWR7-NEXT: addi r3, r1, 256
980 ; CHECK-PWR7-NEXT: vmrghb v2, v3, v2
981 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
982 ; CHECK-PWR7-NEXT: addi r3, r1, 240
983 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
984 ; CHECK-PWR7-NEXT: addi r3, r1, 224
985 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
986 ; CHECK-PWR7-NEXT: vmrghh v2, v3, v2
987 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
988 ; CHECK-PWR7-NEXT: addi r3, r1, 208
989 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
990 ; CHECK-PWR7-NEXT: addi r3, r1, 192
991 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
992 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
993 ; CHECK-PWR7-NEXT: addi r3, r1, 176
994 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3
995 ; CHECK-PWR7-NEXT: addi r3, r1, 160
996 ; CHECK-PWR7-NEXT: vmrghb v4, v5, v4
997 ; CHECK-PWR7-NEXT: vmrghh v3, v4, v3
998 ; CHECK-PWR7-NEXT: xxmrghw vs0, v3, v2
999 ; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3
1000 ; CHECK-PWR7-NEXT: addi r3, r1, 144
1001 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1002 ; CHECK-PWR7-NEXT: addi r3, r1, 128
1003 ; CHECK-PWR7-NEXT: vmrghb v2, v3, v2
1004 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1005 ; CHECK-PWR7-NEXT: addi r3, r1, 112
1006 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1007 ; CHECK-PWR7-NEXT: addi r3, r1, 96
1008 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
1009 ; CHECK-PWR7-NEXT: vmrghh v2, v3, v2
1010 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1011 ; CHECK-PWR7-NEXT: addi r3, r1, 80
1012 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1013 ; CHECK-PWR7-NEXT: addi r3, r1, 64
1014 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
1015 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1016 ; CHECK-PWR7-NEXT: addi r3, r1, 48
1017 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3
1018 ; CHECK-PWR7-NEXT: vmrghb v4, v5, v4
1019 ; CHECK-PWR7-NEXT: vmrghh v3, v4, v3
1020 ; CHECK-PWR7-NEXT: xxmrghw vs1, v3, v2
1021 ; CHECK-PWR7-NEXT: xxmrghd v2, vs1, vs0
1022 ; CHECK-PWR7-NEXT: addi r1, r1, 400
1023 ; CHECK-PWR7-NEXT: blr
1024 entry:
1025 %vecext = extractelement <16 x i8> %a, i32 0
1026 %conv = zext i8 %vecext to i32
1027 %vecext1 = extractelement <16 x i8> %b, i32 0
1028 %conv2 = zext i8 %vecext1 to i32
1029 %sub = sub nsw i32 %conv, %conv2
1030 %ispos = icmp sgt i32 %sub, -1
1031 %neg = sub nsw i32 0, %sub
1032 %0 = select i1 %ispos, i32 %sub, i32 %neg
1033 %conv3 = trunc i32 %0 to i8
1034 %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0
1035 %vecext4 = extractelement <16 x i8> %a, i32 1
1036 %conv5 = zext i8 %vecext4 to i32
1037 %vecext6 = extractelement <16 x i8> %b, i32 1
1038 %conv7 = zext i8 %vecext6 to i32
1039 %sub8 = sub nsw i32 %conv5, %conv7
1040 %ispos171 = icmp sgt i32 %sub8, -1
1041 %neg172 = sub nsw i32 0, %sub8
1042 %1 = select i1 %ispos171, i32 %sub8, i32 %neg172
1043 %conv10 = trunc i32 %1 to i8
1044 %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1
1045 %vecext12 = extractelement <16 x i8> %a, i32 2
1046 %conv13 = zext i8 %vecext12 to i32
1047 %vecext14 = extractelement <16 x i8> %b, i32 2
1048 %conv15 = zext i8 %vecext14 to i32
1049 %sub16 = sub nsw i32 %conv13, %conv15
1050 %ispos173 = icmp sgt i32 %sub16, -1
1051 %neg174 = sub nsw i32 0, %sub16
1052 %2 = select i1 %ispos173, i32 %sub16, i32 %neg174
1053 %conv18 = trunc i32 %2 to i8
1054 %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2
1055 %vecext20 = extractelement <16 x i8> %a, i32 3
1056 %conv21 = zext i8 %vecext20 to i32
1057 %vecext22 = extractelement <16 x i8> %b, i32 3
1058 %conv23 = zext i8 %vecext22 to i32
1059 %sub24 = sub nsw i32 %conv21, %conv23
1060 %ispos175 = icmp sgt i32 %sub24, -1
1061 %neg176 = sub nsw i32 0, %sub24
1062 %3 = select i1 %ispos175, i32 %sub24, i32 %neg176
1063 %conv26 = trunc i32 %3 to i8
1064 %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3
1065 %vecext28 = extractelement <16 x i8> %a, i32 4
1066 %conv29 = zext i8 %vecext28 to i32
1067 %vecext30 = extractelement <16 x i8> %b, i32 4
1068 %conv31 = zext i8 %vecext30 to i32
1069 %sub32 = sub nsw i32 %conv29, %conv31
1070 %ispos177 = icmp sgt i32 %sub32, -1
1071 %neg178 = sub nsw i32 0, %sub32
1072 %4 = select i1 %ispos177, i32 %sub32, i32 %neg178
1073 %conv34 = trunc i32 %4 to i8
1074 %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4
1075 %vecext36 = extractelement <16 x i8> %a, i32 5
1076 %conv37 = zext i8 %vecext36 to i32
1077 %vecext38 = extractelement <16 x i8> %b, i32 5
1078 %conv39 = zext i8 %vecext38 to i32
1079 %sub40 = sub nsw i32 %conv37, %conv39
1080 %ispos179 = icmp sgt i32 %sub40, -1
1081 %neg180 = sub nsw i32 0, %sub40
1082 %5 = select i1 %ispos179, i32 %sub40, i32 %neg180
1083 %conv42 = trunc i32 %5 to i8
1084 %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5
1085 %vecext44 = extractelement <16 x i8> %a, i32 6
1086 %conv45 = zext i8 %vecext44 to i32
1087 %vecext46 = extractelement <16 x i8> %b, i32 6
1088 %conv47 = zext i8 %vecext46 to i32
1089 %sub48 = sub nsw i32 %conv45, %conv47
1090 %ispos181 = icmp sgt i32 %sub48, -1
1091 %neg182 = sub nsw i32 0, %sub48
1092 %6 = select i1 %ispos181, i32 %sub48, i32 %neg182
1093 %conv50 = trunc i32 %6 to i8
1094 %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6
1095 %vecext52 = extractelement <16 x i8> %a, i32 7
1096 %conv53 = zext i8 %vecext52 to i32
1097 %vecext54 = extractelement <16 x i8> %b, i32 7
1098 %conv55 = zext i8 %vecext54 to i32
1099 %sub56 = sub nsw i32 %conv53, %conv55
1100 %ispos183 = icmp sgt i32 %sub56, -1
1101 %neg184 = sub nsw i32 0, %sub56
1102 %7 = select i1 %ispos183, i32 %sub56, i32 %neg184
1103 %conv58 = trunc i32 %7 to i8
1104 %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7
1105 %vecext60 = extractelement <16 x i8> %a, i32 8
1106 %conv61 = zext i8 %vecext60 to i32
1107 %vecext62 = extractelement <16 x i8> %b, i32 8
1108 %conv63 = zext i8 %vecext62 to i32
1109 %sub64 = sub nsw i32 %conv61, %conv63
1110 %ispos185 = icmp sgt i32 %sub64, -1
1111 %neg186 = sub nsw i32 0, %sub64
1112 %8 = select i1 %ispos185, i32 %sub64, i32 %neg186
1113 %conv66 = trunc i32 %8 to i8
1114 %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8
1115 %vecext68 = extractelement <16 x i8> %a, i32 9
1116 %conv69 = zext i8 %vecext68 to i32
1117 %vecext70 = extractelement <16 x i8> %b, i32 9
1118 %conv71 = zext i8 %vecext70 to i32
1119 %sub72 = sub nsw i32 %conv69, %conv71
1120 %ispos187 = icmp sgt i32 %sub72, -1
1121 %neg188 = sub nsw i32 0, %sub72
1122 %9 = select i1 %ispos187, i32 %sub72, i32 %neg188
1123 %conv74 = trunc i32 %9 to i8
1124 %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9
1125 %vecext76 = extractelement <16 x i8> %a, i32 10
1126 %conv77 = zext i8 %vecext76 to i32
1127 %vecext78 = extractelement <16 x i8> %b, i32 10
1128 %conv79 = zext i8 %vecext78 to i32
1129 %sub80 = sub nsw i32 %conv77, %conv79
1130 %ispos189 = icmp sgt i32 %sub80, -1
1131 %neg190 = sub nsw i32 0, %sub80
1132 %10 = select i1 %ispos189, i32 %sub80, i32 %neg190
1133 %conv82 = trunc i32 %10 to i8
1134 %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10
1135 %vecext84 = extractelement <16 x i8> %a, i32 11
1136 %conv85 = zext i8 %vecext84 to i32
1137 %vecext86 = extractelement <16 x i8> %b, i32 11
1138 %conv87 = zext i8 %vecext86 to i32
1139 %sub88 = sub nsw i32 %conv85, %conv87
1140 %ispos191 = icmp sgt i32 %sub88, -1
1141 %neg192 = sub nsw i32 0, %sub88
1142 %11 = select i1 %ispos191, i32 %sub88, i32 %neg192
1143 %conv90 = trunc i32 %11 to i8
1144 %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11
1145 %vecext92 = extractelement <16 x i8> %a, i32 12
1146 %conv93 = zext i8 %vecext92 to i32
1147 %vecext94 = extractelement <16 x i8> %b, i32 12
1148 %conv95 = zext i8 %vecext94 to i32
1149 %sub96 = sub nsw i32 %conv93, %conv95
1150 %ispos193 = icmp sgt i32 %sub96, -1
1151 %neg194 = sub nsw i32 0, %sub96
1152 %12 = select i1 %ispos193, i32 %sub96, i32 %neg194
1153 %conv98 = trunc i32 %12 to i8
1154 %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12
1155 %vecext100 = extractelement <16 x i8> %a, i32 13
1156 %conv101 = zext i8 %vecext100 to i32
1157 %vecext102 = extractelement <16 x i8> %b, i32 13
1158 %conv103 = zext i8 %vecext102 to i32
1159 %sub104 = sub nsw i32 %conv101, %conv103
1160 %ispos195 = icmp sgt i32 %sub104, -1
1161 %neg196 = sub nsw i32 0, %sub104
1162 %13 = select i1 %ispos195, i32 %sub104, i32 %neg196
1163 %conv106 = trunc i32 %13 to i8
1164 %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13
1165 %vecext108 = extractelement <16 x i8> %a, i32 14
1166 %conv109 = zext i8 %vecext108 to i32
1167 %vecext110 = extractelement <16 x i8> %b, i32 14
1168 %conv111 = zext i8 %vecext110 to i32
1169 %sub112 = sub nsw i32 %conv109, %conv111
1170 %ispos197 = icmp sgt i32 %sub112, -1
1171 %neg198 = sub nsw i32 0, %sub112
1172 %14 = select i1 %ispos197, i32 %sub112, i32 %neg198
1173 %conv114 = trunc i32 %14 to i8
1174 %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14
1175 %vecext116 = extractelement <16 x i8> %a, i32 15
1176 %conv117 = zext i8 %vecext116 to i32
1177 %vecext118 = extractelement <16 x i8> %b, i32 15
1178 %conv119 = zext i8 %vecext118 to i32
1179 %sub120 = sub nsw i32 %conv117, %conv119
1180 %ispos199 = icmp sgt i32 %sub120, -1
1181 %neg200 = sub nsw i32 0, %sub120
1182 %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
1183 %conv122 = trunc i32 %15 to i8
1184 %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
1185 ret <16 x i8> %vecins123
1186 }
1188 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
1189 ; CHECK-PWR9-LABEL: sub_absv_vec_32:
1190 ; CHECK-PWR9: # %bb.0: # %entry
1191 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1192 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1193 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1194 ; CHECK-PWR9-NEXT: blr
1195 ;
1196 ; CHECK-PWR78-LABEL: sub_absv_vec_32:
1197 ; CHECK-PWR78: # %bb.0: # %entry
1198 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3
1199 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1200 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
1201 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1202 ; CHECK-PWR78-NEXT: blr
1203 entry:
1204 %sub = sub nsw <4 x i32> %a, %b
1205 %sub.i = sub <4 x i32> zeroinitializer, %sub
1206 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
1207 ret <4 x i32> %0
1208 }
1210 define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
1211 ; CHECK-LABEL: sub_absv_vec_16:
1212 ; CHECK: # %bb.0: # %entry
1213 ; CHECK-NEXT: vsubuhm v2, v2, v3
1214 ; CHECK-NEXT: xxlxor v3, v3, v3
1215 ; CHECK-NEXT: vsubuhm v3, v3, v2
1216 ; CHECK-NEXT: vmaxsh v2, v2, v3
1217 ; CHECK-NEXT: blr
1218 entry:
1219 %sub = sub nsw <8 x i16> %a, %b
1220 %sub.i = sub <8 x i16> zeroinitializer, %sub
1221 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
1222 ret <8 x i16> %0
1223 }
1225 define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
1226 ; CHECK-LABEL: sub_absv_vec_8:
1227 ; CHECK: # %bb.0: # %entry
1228 ; CHECK-NEXT: vsububm v2, v2, v3
1229 ; CHECK-NEXT: xxlxor v3, v3, v3
1230 ; CHECK-NEXT: vsububm v3, v3, v2
1231 ; CHECK-NEXT: vmaxsb v2, v2, v3
1232 ; CHECK-NEXT: blr
1233 entry:
1234 %sub = sub nsw <16 x i8> %a, %b
1235 %sub.i = sub <16 x i8> zeroinitializer, %sub
1236 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
1237 ret <16 x i8> %0
1238 }
1240 define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1241 ; CHECK-PWR9-LE-LABEL: zext_sub_absd32:
1242 ; CHECK-PWR9-LE: # %bb.0:
1243 ; CHECK-PWR9-LE-NEXT: xxlxor v4, v4, v4
1244 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v4, v2
1245 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
1246 ; CHECK-PWR9-LE-NEXT: vabsduw v2, v2, v3
1247 ; CHECK-PWR9-LE-NEXT: blr
1248 ;
1249 ; CHECK-PWR9-BE-LABEL: zext_sub_absd32:
1250 ; CHECK-PWR9-BE: # %bb.0:
1251 ; CHECK-PWR9-BE-NEXT: xxlxor v4, v4, v4
1252 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v4, v2
1253 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
1254 ; CHECK-PWR9-BE-NEXT: vabsduw v2, v2, v3
1255 ; CHECK-PWR9-BE-NEXT: blr
1256 ;
1257 ; CHECK-PWR8-LABEL: zext_sub_absd32:
1258 ; CHECK-PWR8: # %bb.0:
1259 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1260 ; CHECK-PWR8-NEXT: vmrglh v2, v4, v2
1261 ; CHECK-PWR8-NEXT: vmrglh v3, v4, v3
1262 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1263 ; CHECK-PWR8-NEXT: vsubuwm v3, v4, v2
1264 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1265 ; CHECK-PWR8-NEXT: blr
1266 ;
1267 ; CHECK-PWR7-LABEL: zext_sub_absd32:
1268 ; CHECK-PWR7: # %bb.0:
1269 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI13_0@toc@ha
1270 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1271 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI13_0@toc@l
1272 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1273 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1274 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1275 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1276 ; CHECK-PWR7-NEXT: vsubuwm v3, v5, v2
1277 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1278 ; CHECK-PWR7-NEXT: blr
1279 %3 = zext <4 x i16> %0 to <4 x i32>
1280 %4 = zext <4 x i16> %1 to <4 x i32>
1281 %5 = sub <4 x i32> %3, %4
1282 %6 = sub <4 x i32> zeroinitializer, %5
1283 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1284 ret <4 x i32> %7
1285 }
1287 define <8 x i16> @zext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1288 ; CHECK-PWR9-LE-LABEL: zext_sub_absd16:
1289 ; CHECK-PWR9-LE: # %bb.0:
1290 ; CHECK-PWR9-LE-NEXT: xxlxor v4, v4, v4
1291 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v4, v2
1292 ; CHECK-PWR9-LE-NEXT: vmrglb v3, v4, v3
1293 ; CHECK-PWR9-LE-NEXT: vabsduh v2, v2, v3
1294 ; CHECK-PWR9-LE-NEXT: blr
1295 ;
1296 ; CHECK-PWR9-BE-LABEL: zext_sub_absd16:
1297 ; CHECK-PWR9-BE: # %bb.0:
1298 ; CHECK-PWR9-BE-NEXT: xxlxor v4, v4, v4
1299 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v4, v2
1300 ; CHECK-PWR9-BE-NEXT: vmrghb v3, v4, v3
1301 ; CHECK-PWR9-BE-NEXT: vabsduh v2, v2, v3
1302 ; CHECK-PWR9-BE-NEXT: blr
1303 ;
1304 ; CHECK-PWR8-LABEL: zext_sub_absd16:
1305 ; CHECK-PWR8: # %bb.0:
1306 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1307 ; CHECK-PWR8-NEXT: vmrglb v2, v4, v2
1308 ; CHECK-PWR8-NEXT: vmrglb v3, v4, v3
1309 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1310 ; CHECK-PWR8-NEXT: vsubuhm v3, v4, v2
1311 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1312 ; CHECK-PWR8-NEXT: blr
1313 ;
1314 ; CHECK-PWR7-LABEL: zext_sub_absd16:
1315 ; CHECK-PWR7: # %bb.0:
1316 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI14_0@toc@ha
1317 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1318 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI14_0@toc@l
1319 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1320 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1321 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1322 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1323 ; CHECK-PWR7-NEXT: vsubuhm v3, v5, v2
1324 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1325 ; CHECK-PWR7-NEXT: blr
1326 %3 = zext <8 x i8> %0 to <8 x i16>
1327 %4 = zext <8 x i8> %1 to <8 x i16>
1328 %5 = sub <8 x i16> %3, %4
1329 %6 = sub <8 x i16> zeroinitializer, %5
1330 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1331 ret <8 x i16> %7
1332 }
1334 define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1335 ; CHECK-PWR9-LABEL: zext_sub_absd8:
1336 ; CHECK-PWR9: # %bb.0:
1337 ; CHECK-PWR9-NEXT: xxspltib vs0, 15
1338 ; CHECK-PWR9-NEXT: xxland v2, v2, vs0
1339 ; CHECK-PWR9-NEXT: xxland v3, v3, vs0
1340 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1341 ; CHECK-PWR9-NEXT: blr
1342 ;
1343 ; CHECK-PWR78-LABEL: zext_sub_absd8:
1344 ; CHECK-PWR78: # %bb.0:
1345 ; CHECK-PWR78-NEXT: vspltisb v4, 15
1346 ; CHECK-PWR78-NEXT: xxland v2, v2, v4
1347 ; CHECK-PWR78-NEXT: xxland v3, v3, v4
1348 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1349 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1350 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1351 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1352 ; CHECK-PWR78-NEXT: blr
1353 %3 = zext <16 x i4> %0 to <16 x i8>
1354 %4 = zext <16 x i4> %1 to <16 x i8>
1355 %5 = sub <16 x i8> %3, %4
1356 %6 = sub <16 x i8> zeroinitializer, %5
1357 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1358 ret <16 x i8> %7
1359 }
1361 define <4 x i32> @sext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1362 ; CHECK-PWR9-LE-LABEL: sext_sub_absd32:
1363 ; CHECK-PWR9-LE: # %bb.0:
1364 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v2, v2
1365 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v3, v3
1366 ; CHECK-PWR9-LE-NEXT: vextsh2w v2, v2
1367 ; CHECK-PWR9-LE-NEXT: vextsh2w v3, v3
1368 ; CHECK-PWR9-LE-NEXT: xvnegsp v3, v3
1369 ; CHECK-PWR9-LE-NEXT: xvnegsp v2, v2
1370 ; CHECK-PWR9-LE-NEXT: vabsduw v2, v2, v3
1371 ; CHECK-PWR9-LE-NEXT: blr
1372 ;
1373 ; CHECK-PWR9-BE-LABEL: sext_sub_absd32:
1374 ; CHECK-PWR9-BE: # %bb.0:
1375 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v2, v2
1376 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v3, v3
1377 ; CHECK-PWR9-BE-NEXT: vextsh2w v2, v2
1378 ; CHECK-PWR9-BE-NEXT: vextsh2w v3, v3
1379 ; CHECK-PWR9-BE-NEXT: xvnegsp v3, v3
1380 ; CHECK-PWR9-BE-NEXT: xvnegsp v2, v2
1381 ; CHECK-PWR9-BE-NEXT: vabsduw v2, v2, v3
1382 ; CHECK-PWR9-BE-NEXT: blr
1383 ;
1384 ; CHECK-PWR8-LABEL: sext_sub_absd32:
1385 ; CHECK-PWR8: # %bb.0:
1386 ; CHECK-PWR8-NEXT: vspltisw v4, 8
1387 ; CHECK-PWR8-NEXT: vmrglh v2, v2, v2
1388 ; CHECK-PWR8-NEXT: vadduwm v4, v4, v4
1389 ; CHECK-PWR8-NEXT: vmrglh v3, v3, v3
1390 ; CHECK-PWR8-NEXT: vslw v2, v2, v4
1391 ; CHECK-PWR8-NEXT: vslw v3, v3, v4
1392 ; CHECK-PWR8-NEXT: vsraw v2, v2, v4
1393 ; CHECK-PWR8-NEXT: vsraw v3, v3, v4
1394 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1395 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1396 ; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2
1397 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1398 ; CHECK-PWR8-NEXT: blr
1399 ;
1400 ; CHECK-PWR7-LABEL: sext_sub_absd32:
1401 ; CHECK-PWR7: # %bb.0:
1402 ; CHECK-PWR7-NEXT: vspltisw v4, 8
1403 ; CHECK-PWR7-NEXT: vmrghh v2, v2, v2
1404 ; CHECK-PWR7-NEXT: vmrghh v3, v3, v3
1405 ; CHECK-PWR7-NEXT: vadduwm v4, v4, v4
1406 ; CHECK-PWR7-NEXT: vslw v2, v2, v4
1407 ; CHECK-PWR7-NEXT: vslw v3, v3, v4
1408 ; CHECK-PWR7-NEXT: vsraw v2, v2, v4
1409 ; CHECK-PWR7-NEXT: vsraw v3, v3, v4
1410 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1411 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1412 ; CHECK-PWR7-NEXT: vsubuwm v3, v3, v2
1413 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1414 ; CHECK-PWR7-NEXT: blr
1415 %3 = sext <4 x i16> %0 to <4 x i32>
1416 %4 = sext <4 x i16> %1 to <4 x i32>
1417 %5 = sub <4 x i32> %3, %4
1418 %6 = sub <4 x i32> zeroinitializer, %5
1419 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1420 ret <4 x i32> %7
1421 }
1423 define <8 x i16> @sext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1424 ; CHECK-PWR9-LE-LABEL: sext_sub_absd16:
1425 ; CHECK-PWR9-LE: # %bb.0:
1426 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v2, v2
1427 ; CHECK-PWR9-LE-NEXT: vspltish v4, 8
1428 ; CHECK-PWR9-LE-NEXT: vmrglb v3, v3, v3
1429 ; CHECK-PWR9-LE-NEXT: vslh v2, v2, v4
1430 ; CHECK-PWR9-LE-NEXT: vslh v3, v3, v4
1431 ; CHECK-PWR9-LE-NEXT: vsrah v2, v2, v4
1432 ; CHECK-PWR9-LE-NEXT: vsrah v3, v3, v4
1433 ; CHECK-PWR9-LE-NEXT: vsubuhm v2, v2, v3
1434 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1435 ; CHECK-PWR9-LE-NEXT: vsubuhm v3, v3, v2
1436 ; CHECK-PWR9-LE-NEXT: vmaxsh v2, v2, v3
1437 ; CHECK-PWR9-LE-NEXT: blr
1438 ;
1439 ; CHECK-PWR9-BE-LABEL: sext_sub_absd16:
1440 ; CHECK-PWR9-BE: # %bb.0:
1441 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v2, v2
1442 ; CHECK-PWR9-BE-NEXT: vspltish v4, 8
1443 ; CHECK-PWR9-BE-NEXT: vmrghb v3, v3, v3
1444 ; CHECK-PWR9-BE-NEXT: vslh v2, v2, v4
1445 ; CHECK-PWR9-BE-NEXT: vslh v3, v3, v4
1446 ; CHECK-PWR9-BE-NEXT: vsrah v2, v2, v4
1447 ; CHECK-PWR9-BE-NEXT: vsrah v3, v3, v4
1448 ; CHECK-PWR9-BE-NEXT: vsubuhm v2, v2, v3
1449 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1450 ; CHECK-PWR9-BE-NEXT: vsubuhm v3, v3, v2
1451 ; CHECK-PWR9-BE-NEXT: vmaxsh v2, v2, v3
1452 ; CHECK-PWR9-BE-NEXT: blr
1453 ;
1454 ; CHECK-PWR8-LABEL: sext_sub_absd16:
1455 ; CHECK-PWR8: # %bb.0:
1456 ; CHECK-PWR8-NEXT: vmrglb v2, v2, v2
1457 ; CHECK-PWR8-NEXT: vspltish v4, 8
1458 ; CHECK-PWR8-NEXT: vslh v2, v2, v4
1459 ; CHECK-PWR8-NEXT: vmrglb v3, v3, v3
1460 ; CHECK-PWR8-NEXT: vslh v3, v3, v4
1461 ; CHECK-PWR8-NEXT: vsrah v2, v2, v4
1462 ; CHECK-PWR8-NEXT: vsrah v3, v3, v4
1463 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1464 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1465 ; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2
1466 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1467 ; CHECK-PWR8-NEXT: blr
1468 ;
1469 ; CHECK-PWR7-LABEL: sext_sub_absd16:
1470 ; CHECK-PWR7: # %bb.0:
1471 ; CHECK-PWR7-NEXT: vspltish v4, 8
1472 ; CHECK-PWR7-NEXT: vmrghb v2, v2, v2
1473 ; CHECK-PWR7-NEXT: vmrghb v3, v3, v3
1474 ; CHECK-PWR7-NEXT: vslh v2, v2, v4
1475 ; CHECK-PWR7-NEXT: vslh v3, v3, v4
1476 ; CHECK-PWR7-NEXT: vsrah v2, v2, v4
1477 ; CHECK-PWR7-NEXT: vsrah v3, v3, v4
1478 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1479 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1480 ; CHECK-PWR7-NEXT: vsubuhm v3, v3, v2
1481 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1482 ; CHECK-PWR7-NEXT: blr
1483 %3 = sext <8 x i8> %0 to <8 x i16>
1484 %4 = sext <8 x i8> %1 to <8 x i16>
1485 %5 = sub <8 x i16> %3, %4
1486 %6 = sub <8 x i16> zeroinitializer, %5
1487 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1488 ret <8 x i16> %7
1489 }
1491 define <16 x i8> @sext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1492 ; CHECK-PWR9-LABEL: sext_sub_absd8:
1493 ; CHECK-PWR9: # %bb.0:
1494 ; CHECK-PWR9-NEXT: xxspltib v4, 4
1495 ; CHECK-PWR9-NEXT: vslb v2, v2, v4
1496 ; CHECK-PWR9-NEXT: vslb v3, v3, v4
1497 ; CHECK-PWR9-NEXT: vsrab v2, v2, v4
1498 ; CHECK-PWR9-NEXT: vsrab v3, v3, v4
1499 ; CHECK-PWR9-NEXT: vsububm v2, v2, v3
1500 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
1501 ; CHECK-PWR9-NEXT: vsububm v3, v3, v2
1502 ; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3
1503 ; CHECK-PWR9-NEXT: blr
1504 ;
1505 ; CHECK-PWR78-LABEL: sext_sub_absd8:
1506 ; CHECK-PWR78: # %bb.0:
1507 ; CHECK-PWR78-NEXT: vspltisb v4, 4
1508 ; CHECK-PWR78-NEXT: vslb v2, v2, v4
1509 ; CHECK-PWR78-NEXT: vslb v3, v3, v4
1510 ; CHECK-PWR78-NEXT: vsrab v2, v2, v4
1511 ; CHECK-PWR78-NEXT: vsrab v3, v3, v4
1512 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1513 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1514 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1515 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1516 ; CHECK-PWR78-NEXT: blr
1517 %3 = sext <16 x i4> %0 to <16 x i8>
1518 %4 = sext <16 x i4> %1 to <16 x i8>
1519 %5 = sub <16 x i8> %3, %4
1520 %6 = sub <16 x i8> zeroinitializer, %5
1521 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1522 ret <16 x i8> %7
1523 }
1525 ; To verify vabsdu* exploitation for ucmp + sub + select sequence
1527 define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {
1528 ; CHECK-PWR9-LABEL: absd_int32_ugt:
1529 ; CHECK-PWR9: # %bb.0:
1530 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1531 ; CHECK-PWR9-NEXT: blr
1532 ;
1533 ; CHECK-PWR78-LABEL: absd_int32_ugt:
1534 ; CHECK-PWR78: # %bb.0:
1535 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
1536 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1537 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1538 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1539 ; CHECK-PWR78-NEXT: blr
1540 %3 = icmp ugt <4 x i32> %0, %1
1541 %4 = sub <4 x i32> %0, %1
1542 %5 = sub <4 x i32> %1, %0
1543 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1544 ret <4 x i32> %6
1545 }
1547 define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {
1548 ; CHECK-PWR9-LABEL: absd_int32_uge:
1549 ; CHECK-PWR9: # %bb.0:
1550 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1551 ; CHECK-PWR9-NEXT: blr
1552 ;
1553 ; CHECK-PWR78-LABEL: absd_int32_uge:
1554 ; CHECK-PWR78: # %bb.0:
1555 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v3, v2
1556 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1557 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1558 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1559 ; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
1560 ; CHECK-PWR78-NEXT: blr
1561 %3 = icmp uge <4 x i32> %0, %1
1562 %4 = sub <4 x i32> %0, %1
1563 %5 = sub <4 x i32> %1, %0
1564 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1565 ret <4 x i32> %6
1566 }
1568 define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {
1569 ; CHECK-PWR9-LABEL: absd_int32_ult:
1570 ; CHECK-PWR9: # %bb.0:
1571 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1572 ; CHECK-PWR9-NEXT: blr
1573 ;
1574 ; CHECK-PWR78-LABEL: absd_int32_ult:
1575 ; CHECK-PWR78: # %bb.0:
1576 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v3, v2
1577 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1578 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1579 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1580 ; CHECK-PWR78-NEXT: blr
1581 %3 = icmp ult <4 x i32> %0, %1
1582 %4 = sub <4 x i32> %0, %1
1583 %5 = sub <4 x i32> %1, %0
1584 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1585 ret <4 x i32> %6
1586 }
1588 define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {
1589 ; CHECK-PWR9-LABEL: absd_int32_ule:
1590 ; CHECK-PWR9: # %bb.0:
1591 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1592 ; CHECK-PWR9-NEXT: blr
1593 ;
1594 ; CHECK-PWR78-LABEL: absd_int32_ule:
1595 ; CHECK-PWR78: # %bb.0:
1596 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
1597 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1598 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1599 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1600 ; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
1601 ; CHECK-PWR78-NEXT: blr
1602 %3 = icmp ule <4 x i32> %0, %1
1603 %4 = sub <4 x i32> %0, %1
1604 %5 = sub <4 x i32> %1, %0
1605 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1606 ret <4 x i32> %6
1607 }
1609 define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {
1610 ; CHECK-PWR9-LABEL: absd_int16_ugt:
1611 ; CHECK-PWR9: # %bb.0:
1612 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1613 ; CHECK-PWR9-NEXT: blr
1614 ;
1615 ; CHECK-PWR78-LABEL: absd_int16_ugt:
1616 ; CHECK-PWR78: # %bb.0:
1617 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v2, v3
1618 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1619 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1620 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1621 ; CHECK-PWR78-NEXT: blr
1622 %3 = icmp ugt <8 x i16> %0, %1
1623 %4 = sub <8 x i16> %0, %1
1624 %5 = sub <8 x i16> %1, %0
1625 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1626 ret <8 x i16> %6
1627 }
1629 define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {
1630 ; CHECK-PWR9-LABEL: absd_int16_uge:
1631 ; CHECK-PWR9: # %bb.0:
1632 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1633 ; CHECK-PWR9-NEXT: blr
1634 ;
1635 ; CHECK-PWR78-LABEL: absd_int16_uge:
1636 ; CHECK-PWR78: # %bb.0:
1637 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v3, v2
1638 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1639 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1640 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1641 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1642 ; CHECK-PWR78-NEXT: blr
1643 %3 = icmp uge <8 x i16> %0, %1
1644 %4 = sub <8 x i16> %0, %1
1645 %5 = sub <8 x i16> %1, %0
1646 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1647 ret <8 x i16> %6
1648 }
1650 define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {
1651 ; CHECK-PWR9-LABEL: absd_int16_ult:
1652 ; CHECK-PWR9: # %bb.0:
1653 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1654 ; CHECK-PWR9-NEXT: blr
1655 ;
1656 ; CHECK-PWR78-LABEL: absd_int16_ult:
1657 ; CHECK-PWR78: # %bb.0:
1658 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v3, v2
1659 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1660 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1661 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1662 ; CHECK-PWR78-NEXT: blr
1663 %3 = icmp ult <8 x i16> %0, %1
1664 %4 = sub <8 x i16> %0, %1
1665 %5 = sub <8 x i16> %1, %0
1666 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1667 ret <8 x i16> %6
1668 }
1670 define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {
1671 ; CHECK-PWR9-LABEL: absd_int16_ule:
1672 ; CHECK-PWR9: # %bb.0:
1673 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1674 ; CHECK-PWR9-NEXT: blr
1675 ;
1676 ; CHECK-PWR78-LABEL: absd_int16_ule:
1677 ; CHECK-PWR78: # %bb.0:
1678 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v2, v3
1679 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1680 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1681 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1682 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1683 ; CHECK-PWR78-NEXT: blr
1684 %3 = icmp ule <8 x i16> %0, %1
1685 %4 = sub <8 x i16> %0, %1
1686 %5 = sub <8 x i16> %1, %0
1687 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1688 ret <8 x i16> %6
1689 }
1691 define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {
1692 ; CHECK-PWR9-LABEL: absd_int8_ugt:
1693 ; CHECK-PWR9: # %bb.0:
1694 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1695 ; CHECK-PWR9-NEXT: blr
1696 ;
1697 ; CHECK-PWR78-LABEL: absd_int8_ugt:
1698 ; CHECK-PWR78: # %bb.0:
1699 ; CHECK-PWR78-NEXT: vcmpgtub v4, v2, v3
1700 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1701 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1702 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1703 ; CHECK-PWR78-NEXT: blr
1704 %3 = icmp ugt <16 x i8> %0, %1
1705 %4 = sub <16 x i8> %0, %1
1706 %5 = sub <16 x i8> %1, %0
1707 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1708 ret <16 x i8> %6
1709 }
1711 define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {
1712 ; CHECK-PWR9-LABEL: absd_int8_uge:
1713 ; CHECK-PWR9: # %bb.0:
1714 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1715 ; CHECK-PWR9-NEXT: blr
1716 ;
1717 ; CHECK-PWR78-LABEL: absd_int8_uge:
1718 ; CHECK-PWR78: # %bb.0:
1719 ; CHECK-PWR78-NEXT: vcmpgtub v4, v3, v2
1720 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1721 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1722 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1723 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1724 ; CHECK-PWR78-NEXT: blr
1725 %3 = icmp uge <16 x i8> %0, %1
1726 %4 = sub <16 x i8> %0, %1
1727 %5 = sub <16 x i8> %1, %0
1728 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1729 ret <16 x i8> %6
1730 }
1732 define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {
1733 ; CHECK-PWR9-LABEL: absd_int8_ult:
1734 ; CHECK-PWR9: # %bb.0:
1735 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1736 ; CHECK-PWR9-NEXT: blr
1737 ;
1738 ; CHECK-PWR78-LABEL: absd_int8_ult:
1739 ; CHECK-PWR78: # %bb.0:
1740 ; CHECK-PWR78-NEXT: vcmpgtub v4, v3, v2
1741 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1742 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1743 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1744 ; CHECK-PWR78-NEXT: blr
1745 %3 = icmp ult <16 x i8> %0, %1
1746 %4 = sub <16 x i8> %0, %1
1747 %5 = sub <16 x i8> %1, %0
1748 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1749 ret <16 x i8> %6
1750 }
1752 define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {
1753 ; CHECK-PWR9-LABEL: absd_int8_ule:
1754 ; CHECK-PWR9: # %bb.0:
1755 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1756 ; CHECK-PWR9-NEXT: blr
1757 ;
1758 ; CHECK-PWR78-LABEL: absd_int8_ule:
1759 ; CHECK-PWR78: # %bb.0:
1760 ; CHECK-PWR78-NEXT: vcmpgtub v4, v2, v3
1761 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1762 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1763 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1764 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1765 ; CHECK-PWR78-NEXT: blr
1766 %3 = icmp ule <16 x i8> %0, %1
1767 %4 = sub <16 x i8> %0, %1
1768 %5 = sub <16 x i8> %1, %0
1769 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1770 ret <16 x i8> %6
1771 }
1773 ; Tests for ABDS icmp + sub + select sequence
1775 define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {
1776 ; CHECK-PWR9-LABEL: absd_int32_sgt:
1777 ; CHECK-PWR9: # %bb.0:
1778 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1779 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1780 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1781 ; CHECK-PWR9-NEXT: blr
1782 ;
1783 ; CHECK-PWR78-LABEL: absd_int32_sgt:
1784 ; CHECK-PWR78: # %bb.0:
1785 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1786 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1787 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1788 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1789 ; CHECK-PWR78-NEXT: blr
1790 %3 = icmp sgt <4 x i32> %0, %1
1791 %4 = sub <4 x i32> %0, %1
1792 %5 = sub <4 x i32> %1, %0
1793 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1794 ret <4 x i32> %6
1795 }
1797 define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {
1798 ; CHECK-PWR9-LABEL: absd_int32_sge:
1799 ; CHECK-PWR9: # %bb.0:
1800 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1801 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1802 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1803 ; CHECK-PWR9-NEXT: blr
1804 ;
1805 ; CHECK-PWR78-LABEL: absd_int32_sge:
1806 ; CHECK-PWR78: # %bb.0:
1807 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1808 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1809 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1810 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1811 ; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
1812 ; CHECK-PWR78-NEXT: blr
1813 %3 = icmp sge <4 x i32> %0, %1
1814 %4 = sub <4 x i32> %0, %1
1815 %5 = sub <4 x i32> %1, %0
1816 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1817 ret <4 x i32> %6
1818 }
1820 define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {
1821 ; CHECK-PWR9-LABEL: absd_int32_slt:
1822 ; CHECK-PWR9: # %bb.0:
1823 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1824 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1825 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1826 ; CHECK-PWR9-NEXT: blr
1827 ;
1828 ; CHECK-PWR78-LABEL: absd_int32_slt:
1829 ; CHECK-PWR78: # %bb.0:
1830 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1831 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1832 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1833 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1834 ; CHECK-PWR78-NEXT: blr
1835 %3 = icmp slt <4 x i32> %0, %1
1836 %4 = sub <4 x i32> %0, %1
1837 %5 = sub <4 x i32> %1, %0
1838 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1839 ret <4 x i32> %6
1840 }
1842 define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {
1843 ; CHECK-PWR9-LABEL: absd_int32_sle:
1844 ; CHECK-PWR9: # %bb.0:
1845 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1846 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1847 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1848 ; CHECK-PWR9-NEXT: blr
1849 ;
1850 ; CHECK-PWR78-LABEL: absd_int32_sle:
1851 ; CHECK-PWR78: # %bb.0:
1852 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1853 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1854 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1855 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1856 ; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
1857 ; CHECK-PWR78-NEXT: blr
1858 %3 = icmp sle <4 x i32> %0, %1
1859 %4 = sub <4 x i32> %0, %1
1860 %5 = sub <4 x i32> %1, %0
1861 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1862 ret <4 x i32> %6
1863 }
1865 define <8 x i16> @absd_int16_sgt(<8 x i16>, <8 x i16>) {
1866 ; CHECK-LABEL: absd_int16_sgt:
1867 ; CHECK: # %bb.0:
1868 ; CHECK-NEXT: vcmpgtsh v4, v2, v3
1869 ; CHECK-NEXT: vsubuhm v5, v2, v3
1870 ; CHECK-NEXT: vsubuhm v2, v3, v2
1871 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1872 ; CHECK-NEXT: blr
1873 %3 = icmp sgt <8 x i16> %0, %1
1874 %4 = sub <8 x i16> %0, %1
1875 %5 = sub <8 x i16> %1, %0
1876 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1877 ret <8 x i16> %6
1878 }
1880 define <8 x i16> @absd_int16_sge(<8 x i16>, <8 x i16>) {
1881 ; CHECK-LABEL: absd_int16_sge:
1882 ; CHECK: # %bb.0:
1883 ; CHECK-NEXT: vcmpgtsh v4, v3, v2
1884 ; CHECK-NEXT: vsubuhm v5, v2, v3
1885 ; CHECK-NEXT: vsubuhm v2, v3, v2
1886 ; CHECK-NEXT: xxlnor v4, v4, v4
1887 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1888 ; CHECK-NEXT: blr
1889 %3 = icmp sge <8 x i16> %0, %1
1890 %4 = sub <8 x i16> %0, %1
1891 %5 = sub <8 x i16> %1, %0
1892 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1893 ret <8 x i16> %6
1894 }
1896 define <8 x i16> @absd_int16_slt(<8 x i16>, <8 x i16>) {
1897 ; CHECK-LABEL: absd_int16_slt:
1898 ; CHECK: # %bb.0:
1899 ; CHECK-NEXT: vcmpgtsh v4, v3, v2
1900 ; CHECK-NEXT: vsubuhm v5, v2, v3
1901 ; CHECK-NEXT: vsubuhm v2, v3, v2
1902 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1903 ; CHECK-NEXT: blr
1904 %3 = icmp slt <8 x i16> %0, %1
1905 %4 = sub <8 x i16> %0, %1
1906 %5 = sub <8 x i16> %1, %0
1907 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1908 ret <8 x i16> %6
1909 }
1911 define <8 x i16> @absd_int16_sle(<8 x i16>, <8 x i16>) {
1912 ; CHECK-LABEL: absd_int16_sle:
1913 ; CHECK: # %bb.0:
1914 ; CHECK-NEXT: vcmpgtsh v4, v2, v3
1915 ; CHECK-NEXT: vsubuhm v5, v2, v3
1916 ; CHECK-NEXT: vsubuhm v2, v3, v2
1917 ; CHECK-NEXT: xxlnor v4, v4, v4
1918 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1919 ; CHECK-NEXT: blr
1920 %3 = icmp sle <8 x i16> %0, %1
1921 %4 = sub <8 x i16> %0, %1
1922 %5 = sub <8 x i16> %1, %0
1923 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1924 ret <8 x i16> %6
1925 }
1927 define <16 x i8> @absd_int8_sgt(<16 x i8>, <16 x i8>) {
1928 ; CHECK-LABEL: absd_int8_sgt:
1929 ; CHECK: # %bb.0:
1930 ; CHECK-NEXT: vcmpgtsb v4, v2, v3
1931 ; CHECK-NEXT: vsububm v5, v2, v3
1932 ; CHECK-NEXT: vsububm v2, v3, v2
1933 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1934 ; CHECK-NEXT: blr
1935 %3 = icmp sgt <16 x i8> %0, %1
1936 %4 = sub <16 x i8> %0, %1
1937 %5 = sub <16 x i8> %1, %0
1938 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1939 ret <16 x i8> %6
1940 }
1942 define <16 x i8> @absd_int8_sge(<16 x i8>, <16 x i8>) {
1943 ; CHECK-LABEL: absd_int8_sge:
1944 ; CHECK: # %bb.0:
1945 ; CHECK-NEXT: vcmpgtsb v4, v3, v2
1946 ; CHECK-NEXT: vsububm v5, v2, v3
1947 ; CHECK-NEXT: vsububm v2, v3, v2
1948 ; CHECK-NEXT: xxlnor v4, v4, v4
1949 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1950 ; CHECK-NEXT: blr
1951 %3 = icmp sge <16 x i8> %0, %1
1952 %4 = sub <16 x i8> %0, %1
1953 %5 = sub <16 x i8> %1, %0
1954 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1955 ret <16 x i8> %6
1956 }
1958 define <16 x i8> @absd_int8_slt(<16 x i8>, <16 x i8>) {
1959 ; CHECK-LABEL: absd_int8_slt:
1960 ; CHECK: # %bb.0:
1961 ; CHECK-NEXT: vcmpgtsb v4, v3, v2
1962 ; CHECK-NEXT: vsububm v5, v2, v3
1963 ; CHECK-NEXT: vsububm v2, v3, v2
1964 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1965 ; CHECK-NEXT: blr
1966 %3 = icmp slt <16 x i8> %0, %1
1967 %4 = sub <16 x i8> %0, %1
1968 %5 = sub <16 x i8> %1, %0
1969 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1970 ret <16 x i8> %6
1971 }
1973 define <16 x i8> @absd_int8_sle(<16 x i8>, <16 x i8>) {
1974 ; CHECK-LABEL: absd_int8_sle:
1975 ; CHECK: # %bb.0:
1976 ; CHECK-NEXT: vcmpgtsb v4, v2, v3
1977 ; CHECK-NEXT: vsububm v5, v2, v3
1978 ; CHECK-NEXT: vsububm v2, v3, v2
1979 ; CHECK-NEXT: xxlnor v4, v4, v4
1980 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1981 ; CHECK-NEXT: blr
1982 %3 = icmp sle <16 x i8> %0, %1
1983 %4 = sub <16 x i8> %0, %1
1984 %5 = sub <16 x i8> %1, %0
1985 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1986 ret <16 x i8> %6
1987 }
1989 ; some cases we are unable to optimize
1990 ; check whether goes beyond the scope
1991 define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {
1992 ; CHECK-LABEL: absd_int32_ugt_opp:
1993 ; CHECK: # %bb.0:
1994 ; CHECK-NEXT: vcmpgtuw v4, v2, v3
1995 ; CHECK-NEXT: vsubuwm v5, v2, v3
1996 ; CHECK-NEXT: vsubuwm v2, v3, v2
1997 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1998 ; CHECK-NEXT: blr
1999 %3 = icmp ugt <4 x i32> %0, %1
2000 %4 = sub <4 x i32> %0, %1
2001 %5 = sub <4 x i32> %1, %0
2002 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
2003 ret <4 x i32> %6
2004 }
2006 define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {
2007 ; CHECK-PWR9-LABEL: absd_int64_ugt:
2008 ; CHECK-PWR9: # %bb.0:
2009 ; CHECK-PWR9-NEXT: vcmpgtud v4, v2, v3
2010 ; CHECK-PWR9-NEXT: vsubudm v5, v2, v3
2011 ; CHECK-PWR9-NEXT: vsubudm v2, v3, v2
2012 ; CHECK-PWR9-NEXT: xxsel v2, v2, v5, v4
2013 ; CHECK-PWR9-NEXT: blr
2014 ;
2015 ; CHECK-PWR8-LABEL: absd_int64_ugt:
2016 ; CHECK-PWR8: # %bb.0:
2017 ; CHECK-PWR8-NEXT: vcmpgtud v4, v2, v3
2018 ; CHECK-PWR8-NEXT: vsubudm v5, v2, v3
2019 ; CHECK-PWR8-NEXT: vsubudm v2, v3, v2
2020 ; CHECK-PWR8-NEXT: xxsel v2, v2, v5, v4
2021 ; CHECK-PWR8-NEXT: blr
2022 ;
2023 ; CHECK-PWR7-LABEL: absd_int64_ugt:
2024 ; CHECK-PWR7: # %bb.0:
2025 ; CHECK-PWR7-NEXT: addi r3, r1, -64
2026 ; CHECK-PWR7-NEXT: addi r4, r1, -80
2027 ; CHECK-PWR7-NEXT: li r5, 0
2028 ; CHECK-PWR7-NEXT: li r6, -1
2029 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r3
2030 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r4
2031 ; CHECK-PWR7-NEXT: addi r9, r1, -16
2032 ; CHECK-PWR7-NEXT: ld r3, -56(r1)
2033 ; CHECK-PWR7-NEXT: ld r4, -72(r1)
2034 ; CHECK-PWR7-NEXT: ld r8, -80(r1)
2035 ; CHECK-PWR7-NEXT: cmpld r4, r3
2036 ; CHECK-PWR7-NEXT: iselgt r7, r6, r5
2037 ; CHECK-PWR7-NEXT: std r7, -8(r1)
2038 ; CHECK-PWR7-NEXT: ld r7, -64(r1)
2039 ; CHECK-PWR7-NEXT: cmpld r8, r7
2040 ; CHECK-PWR7-NEXT: iselgt r5, r6, r5
2041 ; CHECK-PWR7-NEXT: std r5, -16(r1)
2042 ; CHECK-PWR7-NEXT: sub r5, r4, r3
2043 ; CHECK-PWR7-NEXT: sub r3, r3, r4
2044 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r9
2045 ; CHECK-PWR7-NEXT: std r5, -40(r1)
2046 ; CHECK-PWR7-NEXT: sub r5, r8, r7
2047 ; CHECK-PWR7-NEXT: std r5, -48(r1)
2048 ; CHECK-PWR7-NEXT: addi r5, r1, -48
2049 ; CHECK-PWR7-NEXT: lxvd2x v3, 0, r5
2050 ; CHECK-PWR7-NEXT: std r3, -24(r1)
2051 ; CHECK-PWR7-NEXT: sub r3, r7, r8
2052 ; CHECK-PWR7-NEXT: std r3, -32(r1)
2053 ; CHECK-PWR7-NEXT: addi r3, r1, -32
2054 ; CHECK-PWR7-NEXT: lxvd2x v4, 0, r3
2055 ; CHECK-PWR7-NEXT: xxsel v2, v4, v3, v2
2056 ; CHECK-PWR7-NEXT: blr
2057 %3 = icmp ugt <2 x i64> %0, %1
2058 %4 = sub <2 x i64> %0, %1
2059 %5 = sub <2 x i64> %1, %0
2060 %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %5
2061 ret <2 x i64> %6
2062 }
2064 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
2066 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
2068 declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)