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Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / llvm / unittests / CodeGen / GlobalISel / KnownBitsTest.cpp
blobf3659bc695636137822be2a3811cb7fc70c390d1
1 //===- KnownBitsTest.cpp -------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "GISelMITest.h"
10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12
13 TEST_F(AArch64GISelMITest, TestKnownBitsCst) {
14 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
15 " %4:_(s8) = COPY %3\n";
16 setUp(MIRString);
17 if (!TM)
18 GTEST_SKIP();
19 unsigned CopyReg = Copies[Copies.size() - 1];
20 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
21 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
22 unsigned DstReg = FinalCopy->getOperand(0).getReg();
23 GISelKnownBits Info(*MF);
24 KnownBits Res = Info.getKnownBits(SrcReg);
25 EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
26 EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
27
28 KnownBits Res2 = Info.getKnownBits(DstReg);
29 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
30 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
31 }
32
33 TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) {
34 StringRef MIRString = " %10:gpr32 = MOVi32imm 1\n"
35 " %4:_(s32) = COPY %10\n";
36 setUp(MIRString);
37 if (!TM)
38 GTEST_SKIP();
39 unsigned CopyReg = Copies[Copies.size() - 1];
40 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
41 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
42 unsigned DstReg = FinalCopy->getOperand(0).getReg();
43 GISelKnownBits Info(*MF);
44 KnownBits Res = Info.getKnownBits(SrcReg);
45 // We can't analyze %3 due to the register class constraint. We will get a
46 // default-constructed KnownBits back.
47 EXPECT_EQ((uint64_t)1, Res.getBitWidth());
48 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
49 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
50
51 KnownBits Res2 = Info.getKnownBits(DstReg);
52 // We still don't know the values due to the register class constraint but %4
53 // did reveal the size of %3.
54 EXPECT_EQ((uint64_t)32, Res2.getBitWidth());
55 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
56 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
57 }
58
59 // Check that we are able to track bits through PHIs
60 // and get the intersections of everything we know on each operand.
61 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) {
62 StringRef MIRString = " bb.10:\n"
63 " %10:_(s8) = G_CONSTANT i8 3\n"
64 " %11:_(s1) = G_IMPLICIT_DEF\n"
65 " G_BRCOND %11(s1), %bb.11\n"
66 " G_BR %bb.12\n"
67 "\n"
68 " bb.11:\n"
69 " %12:_(s8) = G_CONSTANT i8 2\n"
70 " G_BR %bb.12\n"
71 "\n"
72 " bb.12:\n"
73 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n"
74 " %14:_(s8) = COPY %13\n";
75 setUp(MIRString);
76 if (!TM)
77 GTEST_SKIP();
78 Register CopyReg = Copies[Copies.size() - 1];
79 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
80 Register SrcReg = FinalCopy->getOperand(1).getReg();
81 Register DstReg = FinalCopy->getOperand(0).getReg();
82 GISelKnownBits Info(*MF);
83 KnownBits Res = Info.getKnownBits(SrcReg);
84 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());
85 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());
86
87 KnownBits Res2 = Info.getKnownBits(DstReg);
88 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
89 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
90 }
91
92 // Check that we report we know nothing when we hit a
93 // non-generic register.
94 // Note: this could be improved though!
95 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIToNonGenericReg) {
96 StringRef MIRString = " bb.10:\n"
97 " %10:gpr32 = MOVi32imm 3\n"
98 " %11:_(s1) = G_IMPLICIT_DEF\n"
99 " G_BRCOND %11(s1), %bb.11\n"
100 " G_BR %bb.12\n"
101 "\n"
102 " bb.11:\n"
103 " %12:_(s8) = G_CONSTANT i8 2\n"
104 " G_BR %bb.12\n"
105 "\n"
106 " bb.12:\n"
107 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n"
108 " %14:_(s8) = COPY %13\n";
109 setUp(MIRString);
110 if (!TM)
111 GTEST_SKIP();
112 Register CopyReg = Copies[Copies.size() - 1];
113 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
114 Register SrcReg = FinalCopy->getOperand(1).getReg();
115 Register DstReg = FinalCopy->getOperand(0).getReg();
116 GISelKnownBits Info(*MF);
117 KnownBits Res = Info.getKnownBits(SrcReg);
118 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
119 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
120
121 KnownBits Res2 = Info.getKnownBits(DstReg);
122 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
123 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
124 }
125
126 // Check that we know nothing when at least one value of a PHI
127 // comes from something we cannot analysis.
128 // This test is not particularly interesting, it is just
129 // here to cover the code that stops the analysis of PHIs
130 // earlier. In that case, we would not even look at the
131 // second incoming value.
132 TEST_F(AArch64GISelMITest, TestKnownBitsUnknownPHI) {
133 StringRef MIRString =
134 " bb.10:\n"
135 " %10:_(s64) = COPY %0\n"
136 " %11:_(s1) = G_IMPLICIT_DEF\n"
137 " G_BRCOND %11(s1), %bb.11\n"
138 " G_BR %bb.12\n"
139 "\n"
140 " bb.11:\n"
141 " %12:_(s64) = G_CONSTANT i64 2\n"
142 " G_BR %bb.12\n"
143 "\n"
144 " bb.12:\n"
145 " %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n"
146 " %14:_(s64) = COPY %13\n";
147 setUp(MIRString);
148 if (!TM)
149 GTEST_SKIP();
150 Register CopyReg = Copies[Copies.size() - 1];
151 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
152 Register SrcReg = FinalCopy->getOperand(1).getReg();
153 Register DstReg = FinalCopy->getOperand(0).getReg();
154 GISelKnownBits Info(*MF);
155 KnownBits Res = Info.getKnownBits(SrcReg);
156 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
157 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
158
159 KnownBits Res2 = Info.getKnownBits(DstReg);
160 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
161 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
162 }
163
164 // Check that we manage to process PHIs that loop on themselves.
165 // For now, the analysis just stops and assumes it knows nothing,
166 // eventually we could teach it how to properly track phis that
167 // loop back.
168 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIWithLoop) {
169 StringRef MIRString =
170 " bb.10:\n"
171 " %10:_(s8) = G_CONSTANT i8 3\n"
172 " %11:_(s1) = G_IMPLICIT_DEF\n"
173 " G_BRCOND %11(s1), %bb.11\n"
174 " G_BR %bb.12\n"
175 "\n"
176 " bb.11:\n"
177 " %12:_(s8) = G_CONSTANT i8 2\n"
178 " G_BR %bb.12\n"
179 "\n"
180 " bb.12:\n"
181 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n"
182 " %14:_(s8) = COPY %13\n"
183 " G_BR %bb.12\n";
184 setUp(MIRString);
185 if (!TM)
186 GTEST_SKIP();
187 Register CopyReg = Copies[Copies.size() - 1];
188 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
189 Register SrcReg = FinalCopy->getOperand(1).getReg();
190 Register DstReg = FinalCopy->getOperand(0).getReg();
191 GISelKnownBits Info(*MF);
192 KnownBits Res = Info.getKnownBits(SrcReg);
193 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
194 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
195
196 KnownBits Res2 = Info.getKnownBits(DstReg);
197 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
198 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
199 }
200
201 // Check that we don't try to analysis PHIs progression.
202 // Setting a deep enough max depth would allow to effectively simulate
203 // what happens in the loop.
204 // Thus, with a deep enough depth, we could actually figure out
205 // that %14's zero known bits are actually at least what we know
206 // for %10, right shifted by one.
207 // However, this process is super expensive compile-time wise and
208 // we don't want to reach that conclusion while playing with max depth.
209 // For now, the analysis just stops and assumes it knows nothing
210 // on PHIs, but eventually we could teach it how to properly track
211 // phis that loop back without relying on the luck effect of max
212 // depth.
213 TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) {
214 StringRef MIRString = " bb.10:\n"
215 " %10:_(s8) = G_CONSTANT i8 5\n"
216 " %11:_(s8) = G_CONSTANT i8 1\n"
217 "\n"
218 " bb.12:\n"
219 " %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n"
220 " %14:_(s8) = G_LSHR %13, %11\n"
221 " %15:_(s8) = COPY %14\n"
222 " G_BR %bb.12\n";
223 setUp(MIRString);
224 if (!TM)
225 GTEST_SKIP();
226 Register CopyReg = Copies[Copies.size() - 1];
227 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
228 Register SrcReg = FinalCopy->getOperand(1).getReg();
229 Register DstReg = FinalCopy->getOperand(0).getReg();
230 GISelKnownBits Info(*MF, /*MaxDepth=*/24);
231 KnownBits Res = Info.getKnownBits(SrcReg);
232 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
233 // A single iteration on the PHI (%13) gives:
234 // %10 has known zero of 0xFA
235 // %12 has known zero of 0x80 (we shift right by one so high bit is zero)
236 // Therefore, %14's known zero are 0x80 shifted by one 0xC0.
237 // If we had simulated the loop we could have more zero bits, basically
238 // up to 0xFC (count leading zero of 5, + 1).
239 EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue());
240
241 KnownBits Res2 = Info.getKnownBits(DstReg);
242 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
243 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
244 }
245
246 TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) {
247 StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"
248 " %4:_(p0) = G_INTTOPTR %3\n"
249 " %5:_(s32) = G_PTRTOINT %4\n"
250 " %6:_(s32) = COPY %5\n";
251 setUp(MIRString);
252 if (!TM)
253 GTEST_SKIP();
254 unsigned CopyReg = Copies[Copies.size() - 1];
255 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
256 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
257 GISelKnownBits Info(*MF);
258 KnownBits Res = Info.getKnownBits(SrcReg);
259 EXPECT_EQ(256u, Res.One.getZExtValue());
260 EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
261 }
262
263 TEST_F(AArch64GISelMITest, TestKnownBitsAND) {
264 StringRef MIRString = R"(
265 %ptr:_(p0) = G_IMPLICIT_DEF
266 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
267 %mask0:_(s8) = G_CONSTANT i8 52
268 %mask1:_(s8) = G_CONSTANT i8 10
269 %tmp0:_(s8) = G_AND %unknown, %mask0
270 %val0:_(s8) = G_OR %tmp0, %mask1
271 %mask2:_(s8) = G_CONSTANT i8 32
272 %mask3:_(s8) = G_CONSTANT i8 24
273 %tmp1:_(s8) = G_AND %unknown, %mask2
274 %val1:_(s8) = G_OR %tmp1, %mask3
275 %and:_(s8) = G_AND %val0, %val1
276 %copy_and:_(s8) = COPY %and
277 )";
278
279 setUp(MIRString);
280 if (!TM)
281 GTEST_SKIP();
282
283 Register CopyReg = Copies[Copies.size() - 1];
284 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
285 Register SrcReg = FinalCopy->getOperand(1).getReg();
286 GISelKnownBits Info(*MF);
287 KnownBits Res = Info.getKnownBits(SrcReg);
288 // 00??1?10
289 // & 00?11000
290 // = 00??1000
291 EXPECT_EQ(0x08u, Res.One.getZExtValue());
292 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());
293 }
294
295 TEST_F(AArch64GISelMITest, TestKnownBitsOR) {
296 StringRef MIRString = R"(
297 %ptr:_(p0) = G_IMPLICIT_DEF
298 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
299 %mask0:_(s8) = G_CONSTANT i8 52
300 %mask1:_(s8) = G_CONSTANT i8 10
301 %tmp0:_(s8) = G_AND %unknown, %mask0
302 %val0:_(s8) = G_OR %tmp0, %mask1
303 %mask2:_(s8) = G_CONSTANT i8 32
304 %mask3:_(s8) = G_CONSTANT i8 24
305 %tmp1:_(s8) = G_AND %unknown, %mask2
306 %val1:_(s8) = G_OR %tmp1, %mask3
307 %or:_(s8) = G_OR %val0, %val1
308 %copy_or:_(s8) = COPY %or
309 )";
310
311 setUp(MIRString);
312 if (!TM)
313 GTEST_SKIP();
314
315 Register CopyReg = Copies[Copies.size() - 1];
316 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
317 Register SrcReg = FinalCopy->getOperand(1).getReg();
318 GISelKnownBits Info(*MF);
319 KnownBits Res = Info.getKnownBits(SrcReg);
320 // 00??1?10
321 // | 00?11000
322 // = 00?11?10
323 EXPECT_EQ(0x1Au, Res.One.getZExtValue());
324 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());
325 }
326
327 TEST_F(AArch64GISelMITest, TestKnownBitsXOR) {
328 StringRef MIRString = R"(
329 %ptr:_(p0) = G_IMPLICIT_DEF
330 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
331 %mask0:_(s8) = G_CONSTANT i8 52
332 %mask1:_(s8) = G_CONSTANT i8 10
333 %tmp0:_(s8) = G_AND %unknown, %mask0
334 %val0:_(s8) = G_OR %tmp0, %mask1
335 %mask2:_(s8) = G_CONSTANT i8 32
336 %mask3:_(s8) = G_CONSTANT i8 24
337 %tmp1:_(s8) = G_AND %unknown, %mask2
338 %val1:_(s8) = G_OR %tmp1, %mask3
339 %xor:_(s8) = G_XOR %val0, %val1
340 %copy_xor:_(s8) = COPY %xor
341 )";
342
343 setUp(MIRString);
344 if (!TM)
345 GTEST_SKIP();
346
347 Register CopyReg = Copies[Copies.size() - 1];
348 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
349 Register SrcReg = FinalCopy->getOperand(1).getReg();
350 GISelKnownBits Info(*MF);
351 KnownBits Res = Info.getKnownBits(SrcReg);
352 // Xor KnowBits does not track if we are doing xor of unknown bit with itself
353 // or negated itself.
354 // 00??1?10
355 // ^ 00?11000
356 // = 00??0?10
357 EXPECT_EQ(0x02u, Res.One.getZExtValue());
358 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());
359 }
360
361 TEST_F(AArch64GISelMITest, TestKnownBitsXORConstant) {
362 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n"
363 " %4:_(s8) = G_CONSTANT i8 7\n"
364 " %5:_(s8) = G_XOR %3, %4\n"
365 " %6:_(s8) = COPY %5\n";
366 setUp(MIRString);
367 if (!TM)
368 GTEST_SKIP();
369 unsigned CopyReg = Copies[Copies.size() - 1];
370 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
371 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
372 GISelKnownBits Info(*MF);
373 KnownBits Res = Info.getKnownBits(SrcReg);
374 EXPECT_EQ(3u, Res.One.getZExtValue());
375 EXPECT_EQ(252u, Res.Zero.getZExtValue());
376 }
377
378 TEST_F(AArch64GISelMITest, TestKnownBitsASHR) {
379 StringRef MIRString = R"(
380 %ptr:_(p0) = G_IMPLICIT_DEF
381 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
382 %mask0:_(s8) = G_CONSTANT i8 38
383 %mask1:_(s8) = G_CONSTANT i8 202
384 %tmp0:_(s8) = G_AND %unknown, %mask0
385 %val0:_(s8) = G_OR %tmp0, %mask1
386 %cst0:_(s8) = G_CONSTANT i8 2
387 %ashr0:_(s8) = G_ASHR %val0, %cst0
388 %copy_ashr0:_(s8) = COPY %ashr0
389
390 %mask2:_(s8) = G_CONSTANT i8 204
391 %mask3:_(s8) = G_CONSTANT i8 18
392 %tmp1:_(s8) = G_AND %unknown, %mask2
393 %val1:_(s8) = G_OR %tmp1, %mask3
394 %ashr1:_(s8) = G_ASHR %val1, %cst0
395 %copy_ashr1:_(s8) = COPY %ashr1
396 )";
397
398 setUp(MIRString);
399 if (!TM)
400 GTEST_SKIP();
401
402 Register CopyReg0 = Copies[Copies.size() - 2];
403 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
404 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
405 GISelKnownBits Info(*MF);
406 KnownBits Res0 = Info.getKnownBits(SrcReg0);
407 // 11?01??0 >> 2
408 // = 1111?01?
409 EXPECT_EQ(0xF2u, Res0.One.getZExtValue());
410 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());
411
412 Register CopyReg1 = Copies[Copies.size() - 1];
413 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
414 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
415 KnownBits Res1 = Info.getKnownBits(SrcReg1);
416 // ??01??10 >> 2
417 // = ????01??
418 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
419 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());
420 }
421
422 TEST_F(AArch64GISelMITest, TestKnownBitsLSHR) {
423 StringRef MIRString = R"(
424 %ptr:_(p0) = G_IMPLICIT_DEF
425 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
426 %mask0:_(s8) = G_CONSTANT i8 38
427 %mask1:_(s8) = G_CONSTANT i8 202
428 %tmp0:_(s8) = G_AND %unknown, %mask0
429 %val0:_(s8) = G_OR %tmp0, %mask1
430 %cst0:_(s8) = G_CONSTANT i8 2
431 %lshr0:_(s8) = G_LSHR %val0, %cst0
432 %copy_lshr0:_(s8) = COPY %lshr0
433
434 %mask2:_(s8) = G_CONSTANT i8 204
435 %mask3:_(s8) = G_CONSTANT i8 18
436 %tmp1:_(s8) = G_AND %unknown, %mask2
437 %val1:_(s8) = G_OR %tmp1, %mask3
438 %lshr1:_(s8) = G_LSHR %val1, %cst0
439 %copy_lshr1:_(s8) = COPY %lshr1
440 )";
441
442 setUp(MIRString);
443 if (!TM)
444 GTEST_SKIP();
445
446 Register CopyReg0 = Copies[Copies.size() - 2];
447 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
448 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
449 GISelKnownBits Info(*MF);
450 KnownBits Res0 = Info.getKnownBits(SrcReg0);
451 // 11?01??0 >> 2
452 // = 0011?01?
453 EXPECT_EQ(0x32u, Res0.One.getZExtValue());
454 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());
455
456 Register CopyReg1 = Copies[Copies.size() - 1];
457 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
458 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
459 KnownBits Res1 = Info.getKnownBits(SrcReg1);
460 // ??01??10 >> 2
461 // = 00??01??
462 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
463 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());
464 }
465
466 TEST_F(AArch64GISelMITest, TestKnownBitsSHL) {
467 StringRef MIRString = R"(
468 %ptr:_(p0) = G_IMPLICIT_DEF
469 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
470 %mask0:_(s8) = G_CONSTANT i8 51
471 %mask1:_(s8) = G_CONSTANT i8 72
472 %tmp:_(s8) = G_AND %unknown, %mask0
473 %val:_(s8) = G_OR %tmp, %mask1
474 %cst:_(s8) = G_CONSTANT i8 3
475 %shl:_(s8) = G_SHL %val, %cst
476 %copy_shl:_(s8) = COPY %shl
477 )";
478
479 setUp(MIRString);
480 if (!TM)
481 GTEST_SKIP();
482
483 Register CopyReg = Copies[Copies.size() - 1];
484 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
485 Register SrcReg = FinalCopy->getOperand(1).getReg();
486 GISelKnownBits Info(*MF);
487 KnownBits Res = Info.getKnownBits(SrcReg);
488 // 01??10?? << 3
489 // = ?10??000
490 EXPECT_EQ(0x40u, Res.One.getZExtValue());
491 EXPECT_EQ(0x27u, Res.Zero.getZExtValue());
492 }
493
494 TEST_F(AArch64GISelMITest, TestKnownBitsADD) {
495 StringRef MIRString = R"(
496 %ptr:_(p0) = G_IMPLICIT_DEF
497 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
498 %mask0:_(s16) = G_CONSTANT i16 4642
499 %mask1:_(s16) = G_CONSTANT i16 9536
500 %tmp0:_(s16) = G_AND %unknown, %mask0
501 %val0:_(s16) = G_OR %tmp0, %mask1
502 %mask2:_(s16) = G_CONSTANT i16 4096
503 %mask3:_(s16) = G_CONSTANT i16 371
504 %tmp1:_(s16) = G_AND %unknown, %mask2
505 %val1:_(s16) = G_OR %tmp1, %mask3
506 %add:_(s16) = G_ADD %val0, %val1
507 %copy_add:_(s16) = COPY %add
508 )";
509
510 setUp(MIRString);
511 if (!TM)
512 GTEST_SKIP();
513
514 Register CopyReg = Copies[Copies.size() - 1];
515 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
516 Register SrcReg = FinalCopy->getOperand(1).getReg();
517 GISelKnownBits Info(*MF);
518 KnownBits Res = Info.getKnownBits(SrcReg);
519 // Add KnowBits works out known carry bits first and then calculates result.
520 // 001?01?101?000?0
521 // + 000?000101110011
522 // = 0??????01??10??1
523 EXPECT_EQ(0x0091u, Res.One.getZExtValue());
524 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());
525 }
526
527 TEST_F(AArch64GISelMITest, TestKnownBitsSUB) {
528 StringRef MIRString = R"(
529 %ptr:_(p0) = G_IMPLICIT_DEF
530 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
531 %mask0:_(s16) = G_CONSTANT i16 4642
532 %mask1:_(s16) = G_CONSTANT i16 9536
533 %tmp0:_(s16) = G_AND %unknown, %mask0
534 %val0:_(s16) = G_OR %tmp0, %mask1
535 %mask2:_(s16) = G_CONSTANT i16 4096
536 %mask3:_(s16) = G_CONSTANT i16 371
537 %tmp1:_(s16) = G_AND %unknown, %mask2
538 %val1:_(s16) = G_OR %tmp1, %mask3
539 %sub:_(s16) = G_SUB %val0, %val1
540 %copy_sub:_(s16) = COPY %sub
541 )";
542
543 setUp(MIRString);
544 if (!TM)
545 GTEST_SKIP();
546
547 Register CopyReg = Copies[Copies.size() - 1];
548 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
549 Register SrcReg = FinalCopy->getOperand(1).getReg();
550 GISelKnownBits Info(*MF);
551 KnownBits Res = Info.getKnownBits(SrcReg);
552 // Sub KnowBits for LHS - RHS use Add KnownBits for LHS + ~RHS + 1.
553 EXPECT_EQ(0x01CDu, Res.One.getZExtValue());
554 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());
555 }
556
557 TEST_F(AArch64GISelMITest, TestKnownBitsMUL) {
558 StringRef MIRString = R"(
559 %ptr0:_(p0) = G_IMPLICIT_DEF
560 %load0:_(s16) = G_LOAD %ptr0(p0) :: (load (s16))
561 %mask0:_(s16) = G_CONSTANT i16 4
562 %mask1:_(s16) = G_CONSTANT i16 18
563 %tmp:_(s16) = G_AND %load0, %mask0
564 %val0:_(s16) = G_OR %tmp, %mask1
565 %cst:_(s16) = G_CONSTANT i16 12
566 %mul:_(s16) = G_MUL %val0, %cst
567 %copy_mul:_(s16) = COPY %mul
568 )";
569
570 setUp(MIRString);
571 if (!TM)
572 GTEST_SKIP();
573
574 Register CopyReg = Copies[Copies.size() - 1];
575 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
576 Register SrcReg = FinalCopy->getOperand(1).getReg();
577 GISelKnownBits Info(*MF);
578 KnownBits Res = Info.getKnownBits(SrcReg);
579 // Mul KnowBits are conservatively correct, but not guaranteed to be precise.
580 // Precise for trailing bits up to the first unknown bit.
581 // 00010?10 * 00001100 =
582 // 00010?1000
583 // + 00010?10000
584 // = 0000000010??1000
585 // KB 0000000?????1000
586 EXPECT_EQ(0x0008u, Res.One.getZExtValue());
587 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());
588 }
589
590 TEST_F(AArch64GISelMITest, TestKnownBitsICMP) {
591 StringRef MIRString = R"(
592 %cst0:_(s32) = G_CONSTANT i32 0
593 %cst1:_(s32) = G_CONSTANT i32 1
594 %icmp:_(s32) = G_ICMP intpred(ne), %cst0, %cst1
595 %copy_icmp:_(s32) = COPY %icmp
596 )";
597
598 setUp(MIRString);
599 if (!TM)
600 GTEST_SKIP();
601
602 Register CopyReg = Copies[Copies.size() - 1];
603 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
604 Register SrcReg = FinalCopy->getOperand(1).getReg();
605 GISelKnownBits Info(*MF);
606 KnownBits Res = Info.getKnownBits(SrcReg);
607 // For targets that use 0 or 1 as icmp result in large register set high bits
608 // to 0, does not analyze operands/compare predicate.
609 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
610 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
611 }
612
613 TEST_F(AArch64GISelMITest, TestKnownBitsFCMP) {
614 StringRef MIRString = R"(
615 %cst0:_(s32) = G_FCONSTANT float 0.0
616 %cst1:_(s32) = G_FCONSTANT float 1.0
617 %fcmp:_(s32) = G_FCMP floatpred(one), %cst0, %cst1
618 %copy_fcmp:_(s32) = COPY %fcmp
619 )";
620
621 setUp(MIRString);
622 if (!TM)
623 GTEST_SKIP();
624
625 Register CopyReg = Copies[Copies.size() - 1];
626 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
627 Register SrcReg = FinalCopy->getOperand(1).getReg();
628 GISelKnownBits Info(*MF);
629 KnownBits Res = Info.getKnownBits(SrcReg);
630 // For targets that use 0 or 1 as fcmp result in large register set high bits
631 // to 0, does not analyze operands/compare predicate.
632 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
633 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
634 }
635
636 TEST_F(AArch64GISelMITest, TestKnownBitsSelect) {
637 StringRef MIRString = R"(
638 %ptr:_(p0) = G_IMPLICIT_DEF
639 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
640 %mask0:_(s8) = G_CONSTANT i8 24
641 %mask1:_(s8) = G_CONSTANT i8 224
642 %tmp0:_(s8) = G_AND %unknown, %mask0
643 %val0:_(s8) = G_OR %tmp0, %mask1
644 %mask2:_(s8) = G_CONSTANT i8 146
645 %mask3:_(s8) = G_CONSTANT i8 36
646 %tmp1:_(s8) = G_AND %unknown, %mask2
647 %val1:_(s8) = G_OR %tmp1, %mask3
648 %cond:_(s1) = G_CONSTANT i1 false
649 %select:_(s8) = G_SELECT %cond, %val0, %val1
650 %copy_select:_(s8) = COPY %select
651 )";
652
653 setUp(MIRString);
654 if (!TM)
655 GTEST_SKIP();
656
657 Register CopyReg = Copies[Copies.size() - 1];
658 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
659 Register SrcReg = FinalCopy->getOperand(1).getReg();
660 GISelKnownBits Info(*MF);
661 KnownBits Res = Info.getKnownBits(SrcReg);
662 // Select KnownBits takes common bits of LHS and RHS, does not analyze
663 // condition operand.
664 // 111??000
665 // select ?01?01?0
666 // = ??1????0
667 EXPECT_EQ(0x20u, Res.One.getZExtValue());
668 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
669 }
670
671 TEST_F(AArch64GISelMITest, TestKnownBits) {
672
673 StringRef MIR = " %3:_(s32) = G_TRUNC %0\n"
674 " %4:_(s32) = G_TRUNC %1\n"
675 " %5:_(s32) = G_CONSTANT i32 5\n"
676 " %6:_(s32) = G_CONSTANT i32 24\n"
677 " %7:_(s32) = G_CONSTANT i32 28\n"
678 " %14:_(p0) = G_INTTOPTR %7\n"
679 " %16:_(s32) = G_PTRTOINT %14\n"
680 " %8:_(s32) = G_SHL %3, %5\n"
681 " %9:_(s32) = G_SHL %4, %5\n"
682 " %10:_(s32) = G_OR %8, %6\n"
683 " %11:_(s32) = G_OR %9, %16\n"
684 " %12:_(s32) = G_MUL %10, %11\n"
685 " %13:_(s32) = COPY %12\n";
686 setUp(MIR);
687 if (!TM)
688 GTEST_SKIP();
689 unsigned CopyReg = Copies[Copies.size() - 1];
690 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
691 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
692 GISelKnownBits Info(*MF);
693 KnownBits Known = Info.getKnownBits(SrcReg);
694 EXPECT_FALSE(Known.hasConflict());
695 EXPECT_EQ(32u, Known.One.getZExtValue());
696 EXPECT_EQ(95u, Known.Zero.getZExtValue());
697 APInt Zeroes = Info.getKnownZeroes(SrcReg);
698 EXPECT_EQ(Known.Zero, Zeroes);
699 }
700
701 TEST_F(AArch64GISelMITest, TestSignBitIsZero) {
702 setUp();
703 if (!TM)
704 GTEST_SKIP();
705
706 const LLT S32 = LLT::scalar(32);
707 auto SignBit = B.buildConstant(S32, 0x80000000);
708 auto Zero = B.buildConstant(S32, 0);
709
710 GISelKnownBits KnownBits(*MF);
711
712 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
713 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
714 }
715
716 TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) {
717 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
718 " %4:_(s8) = COPY %3\n"
719
720 " %5:_(s8) = G_CONSTANT i8 -1\n"
721 " %6:_(s8) = COPY %5\n"
722
723 " %7:_(s8) = G_CONSTANT i8 127\n"
724 " %8:_(s8) = COPY %7\n"
725
726 " %9:_(s8) = G_CONSTANT i8 32\n"
727 " %10:_(s8) = COPY %9\n"
728
729 " %11:_(s8) = G_CONSTANT i8 -32\n"
730 " %12:_(s8) = COPY %11\n";
731 setUp(MIRString);
732 if (!TM)
733 GTEST_SKIP();
734 Register CopyReg1 = Copies[Copies.size() - 5];
735 Register CopyRegNeg1 = Copies[Copies.size() - 4];
736 Register CopyReg127 = Copies[Copies.size() - 3];
737 Register CopyReg32 = Copies[Copies.size() - 2];
738 Register CopyRegNeg32 = Copies[Copies.size() - 1];
739
740 GISelKnownBits Info(*MF);
741 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));
742 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));
743 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));
744 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));
745 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));
746 }
747
748 TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {
749 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
750 " %4:_(s8) = G_LOAD %3 :: (load (s8))\n"
751 " %5:_(s32) = G_SEXT %4\n"
752 " %6:_(s32) = COPY %5\n"
753
754 " %7:_(s8) = G_CONSTANT i8 -1\n"
755 " %8:_(s32) = G_SEXT %7\n"
756 " %9:_(s32) = COPY %8\n";
757 setUp(MIRString);
758 if (!TM)
759 GTEST_SKIP();
760 Register CopySextLoad = Copies[Copies.size() - 2];
761 Register CopySextNeg1 = Copies[Copies.size() - 1];
762
763 GISelKnownBits Info(*MF);
764 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
765 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));
766 }
767
768 TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) {
769 StringRef MIRString = R"(
770 %ptr:_(p0) = G_IMPLICIT_DEF
771 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
772
773 %inreg7:_(s32) = G_SEXT_INREG %load4, 7
774 %copy_inreg7:_(s32) = COPY %inreg7
775
776 %inreg8:_(s32) = G_SEXT_INREG %load4, 8
777 %copy_inreg8:_(s32) = COPY %inreg8
778
779 %inreg9:_(s32) = G_SEXT_INREG %load4, 9
780 %copy_inreg9:_(s32) = COPY %inreg9
781
782 %inreg31:_(s32) = G_SEXT_INREG %load4, 31
783 %copy_inreg31:_(s32) = COPY %inreg31
784
785 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
786 %sext_load1:_(s32) = G_SEXT %load1
787
788 %inreg6_sext:_(s32) = G_SEXT_INREG %sext_load1, 6
789 %copy_inreg6_sext:_(s32) = COPY %inreg6_sext
790
791 %inreg7_sext:_(s32) = G_SEXT_INREG %sext_load1, 7
792 %copy_inreg7_sext:_(s32) = COPY %inreg7_sext
793
794 %inreg8_sext:_(s32) = G_SEXT_INREG %sext_load1, 8
795 %copy_inreg8_sext:_(s32) = COPY %inreg8_sext
796
797 %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9
798 %copy_inreg9_sext:_(s32) = COPY %inreg9_sext
799
800 %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31
801 %copy_inreg31_sext:_(s32) = COPY %inreg31_sext
802 )";
803
804 setUp(MIRString);
805 if (!TM)
806 GTEST_SKIP();
807
808 Register CopyInReg7 = Copies[Copies.size() - 9];
809 Register CopyInReg8 = Copies[Copies.size() - 8];
810 Register CopyInReg9 = Copies[Copies.size() - 7];
811 Register CopyInReg31 = Copies[Copies.size() - 6];
812
813 Register CopyInReg6Sext = Copies[Copies.size() - 5];
814 Register CopyInReg7Sext = Copies[Copies.size() - 4];
815 Register CopyInReg8Sext = Copies[Copies.size() - 3];
816 Register CopyInReg9Sext = Copies[Copies.size() - 2];
817 Register CopyInReg31Sext = Copies[Copies.size() - 1];
818
819 GISelKnownBits Info(*MF);
820 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
821 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
822 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
823 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
824
825 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
826 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
827 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
828 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
829 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
830 }
831
832 TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) {
833 StringRef MIRString = R"(
834 %ptr:_(p0) = G_IMPLICIT_DEF
835 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
836
837 %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1
838 %copy_assert_sext1:_(s32) = COPY %assert_sext1
839
840 %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7
841 %copy_assert_sext7:_(s32) = COPY %assert_sext7
842
843 %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8
844 %copy_assert_sext8:_(s32) = COPY %assert_sext8
845
846 %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9
847 %copy_assert_sext9:_(s32) = COPY %assert_sext9
848
849 %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31
850 %copy_assert_sext31:_(s32) = COPY %assert_sext31
851
852 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
853 %sext_load1:_(s32) = G_SEXT %load1
854
855 %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6
856 %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext
857
858 %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7
859 %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext
860
861 %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8
862 %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext
863
864 %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9
865 %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext
866
867 %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31
868 %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext
869 )";
870
871 setUp(MIRString);
872 if (!TM)
873 GTEST_SKIP();
874
875 Register CopyInReg1 = Copies[Copies.size() - 10];
876 Register CopyInReg7 = Copies[Copies.size() - 9];
877 Register CopyInReg8 = Copies[Copies.size() - 8];
878 Register CopyInReg9 = Copies[Copies.size() - 7];
879 Register CopyInReg31 = Copies[Copies.size() - 6];
880
881 Register CopyInReg6Sext = Copies[Copies.size() - 5];
882 Register CopyInReg7Sext = Copies[Copies.size() - 4];
883 Register CopyInReg8Sext = Copies[Copies.size() - 3];
884 Register CopyInReg9Sext = Copies[Copies.size() - 2];
885 Register CopyInReg31Sext = Copies[Copies.size() - 1];
886
887 GISelKnownBits Info(*MF);
888 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));
889 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
890 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
891 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
892 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
893
894 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
895 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
896 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
897 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
898 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
899 }
900
901 TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {
902 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
903 " %4:_(s32) = G_LOAD %3 :: (load (s32))\n"
904 " %5:_(s8) = G_TRUNC %4\n"
905 " %6:_(s8) = COPY %5\n"
906
907 " %7:_(s32) = G_CONSTANT i32 -1\n"
908 " %8:_(s8) = G_TRUNC %7\n"
909 " %9:_(s8) = COPY %8\n"
910
911 " %10:_(s32) = G_CONSTANT i32 7\n"
912 " %11:_(s8) = G_TRUNC %10\n"
913 " %12:_(s8) = COPY %11\n";
914 setUp(MIRString);
915 if (!TM)
916 GTEST_SKIP();
917 Register CopyTruncLoad = Copies[Copies.size() - 3];
918 Register CopyTruncNeg1 = Copies[Copies.size() - 2];
919 Register CopyTrunc7 = Copies[Copies.size() - 1];
920
921 GISelKnownBits Info(*MF);
922 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
923 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
924 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
925 }
926
927 TEST_F(AArch64GISelMITest, TestNumSignBitsCmp) {
928 StringRef MIRString =
929 " %v1:_(<4 x s32>) = G_IMPLICIT_DEF\n"
930 " %v2:_(<4 x s32>) = G_IMPLICIT_DEF\n"
931 " %s1:_(s64) = G_IMPLICIT_DEF\n"
932 " %s2:_(s64) = G_IMPLICIT_DEF\n"
933 " %cmp:_(<4 x s32>) = G_FCMP floatpred(ogt), %v1, %v2\n"
934 " %cpy1:_(<4 x s32>) = COPY %cmp\n"
935 " %cmp2:_(<4 x s32>) = G_ICMP intpred(eq), %v1, %v2\n"
936 " %cpy2:_(<4 x s32>) = COPY %cmp2\n"
937 " %cmp3:_(s32) = G_FCMP floatpred(ogt), %s1, %s2\n"
938 " %cpy3:_(s32) = COPY %cmp3\n"
939 " %cmp4:_(s32) = G_ICMP intpred(eq), %s1, %s2\n"
940 " %cpy4:_(s32) = COPY %cmp4\n";
941
942 setUp(MIRString);
943 if (!TM)
944 GTEST_SKIP();
945 Register CopyVecFCMP = Copies[Copies.size() - 4];
946 Register CopyVecICMP = Copies[Copies.size() - 3];
947 Register CopyScalarFCMP = Copies[Copies.size() - 2];
948 Register CopyScalarICMP = Copies[Copies.size() - 1];
949
950 GISelKnownBits Info(*MF);
951 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecFCMP));
952 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecICMP));
953 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarFCMP));
954 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarICMP));
955 }
956
957 TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
958 StringRef MIRString =
959 " %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"
960 " %4:_(s32) = G_IMPLICIT_DEF\n"
961 " %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
962 " %6:_(s32) = COPY %5\n"
963
964 " %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
965 " %8:_(s32) = COPY %7\n"
966
967 " %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
968 " %10:_(s32) = COPY %9\n"
969
970 " %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
971 " %12:_(s32) = COPY %11\n";
972
973 setUp(MIRString);
974 if (!TM)
975 GTEST_SKIP();
976
977 Register CopyLoadUByte = Copies[Copies.size() - 4];
978 Register CopyLoadSByte = Copies[Copies.size() - 3];
979 Register CopyLoadUShort = Copies[Copies.size() - 2];
980 Register CopyLoadSShort = Copies[Copies.size() - 1];
981
982 GISelKnownBits Info(*MF);
983
984 EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));
985 EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));
986 EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));
987 EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));
988 }
989
990 TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {
991 StringRef MIRString =
992 " %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n"
993 " %6:_(p4) = COPY %5\n"
994 " %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n"
995 " %8:_(p4) = COPY %7\n"
996 " %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"
997 " %10:_(p4) = COPY %9\n"
998 " %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"
999 " %12:_(p4) = COPY %11\n"
1000 " %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"
1001 " %14:_(p4) = COPY %13\n";
1002
1003 setUp(MIRString);
1004 if (!TM)
1005 GTEST_SKIP();
1006
1007 Register CopyDispatchPtr = Copies[Copies.size() - 5];
1008 Register CopyQueuePtr = Copies[Copies.size() - 4];
1009 Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];
1010 Register CopyImplicitArgPtr = Copies[Copies.size() - 2];
1011 Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];
1012
1013 GISelKnownBits Info(*MF);
1014
1015 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr));
1016 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr));
1017 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr));
1018 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr));
1019 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));
1020 }
1021
1022 TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {
1023
1024 StringRef MIRString = R"MIR(
1025 %zero:_(s32) = G_CONSTANT i32 0
1026 %one:_(s32) = G_CONSTANT i32 1
1027 %two:_(s32) = G_CONSTANT i32 2
1028 %three:_(s32) = G_CONSTANT i32 3
1029 %five:_(s32) = G_CONSTANT i32 5
1030 %copy_zero:_(s32) = COPY %zero
1031 %copy_one:_(s32) = COPY %one
1032 %copy_two:_(s32) = COPY %two
1033 %copy_three:_(s32) = COPY %three
1034
1035 %trunc_two:_(s1) = G_TRUNC %two
1036 %trunc_three:_(s1) = G_TRUNC %three
1037 %trunc_five:_(s1) = G_TRUNC %five
1038
1039 %copy_trunc_two:_(s1) = COPY %trunc_two
1040 %copy_trunc_three:_(s1) = COPY %trunc_three
1041 %copy_trunc_five:_(s1) = COPY %trunc_five
1042
1043 %ptr:_(p1) = G_IMPLICIT_DEF
1044 %shift_amt:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1045
1046 %shl_1:_(s32) = G_SHL %one, %shift_amt
1047 %copy_shl_1:_(s32) = COPY %shl_1
1048
1049 %shl_2:_(s32) = G_SHL %two, %shift_amt
1050 %copy_shl_2:_(s32) = COPY %shl_2
1051
1052 %not_sign_mask:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1053 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648
1054
1055 %lshr_not_sign_mask:_(s32) = G_LSHR %not_sign_mask, %shift_amt
1056 %copy_lshr_not_sign_mask:_(s32) = COPY %lshr_not_sign_mask
1057
1058 %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt
1059 %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask
1060
1061 %or_pow2:_(s32) = G_OR %zero, %two
1062 %copy_or_pow2:_(s32) = COPY %or_pow2
1063
1064 )MIR";
1065 setUp(MIRString);
1066 if (!TM)
1067 GTEST_SKIP();
1068
1069 GISelKnownBits KB(*MF);
1070
1071 Register CopyZero = Copies[Copies.size() - 12];
1072 Register CopyOne = Copies[Copies.size() - 11];
1073 Register CopyTwo = Copies[Copies.size() - 10];
1074 Register CopyThree = Copies[Copies.size() - 9];
1075 Register CopyTruncTwo = Copies[Copies.size() - 8];
1076 Register CopyTruncThree = Copies[Copies.size() - 7];
1077 Register CopyTruncFive = Copies[Copies.size() - 6];
1078
1079 Register CopyShl1 = Copies[Copies.size() - 5];
1080 Register CopyShl2 = Copies[Copies.size() - 4];
1081
1082 Register CopyLShrNotSignMask = Copies[Copies.size() - 3];
1083 Register CopyLShrSignMask = Copies[Copies.size() - 2];
1084 Register CopyOrPow2 = Copies[Copies.size() - 1];
1085
1086 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB));
1087 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB));
1088 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB));
1089 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB));
1090
1091 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB));
1092 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB));
1093 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB));
1094
1095 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB));
1096 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB));
1097
1098 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB));
1099 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB));
1100 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB));
1101 }
1102
1103 TEST_F(AArch64GISelMITest, TestMetadata) {
1104 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1105 " %load:_(s8) = G_LOAD %imp(p0) :: (load (s8))\n"
1106 " %ext:_(s32) = G_ZEXT %load(s8)\n"
1107 " %cst:_(s32) = G_CONSTANT i32 1\n"
1108 " %and:_(s32) = G_AND %ext, %cst\n"
1109 " %copy:_(s32) = COPY %and(s32)\n";
1110 setUp(MIRString);
1111 if (!TM)
1112 GTEST_SKIP();
1113
1114 Register CopyReg = Copies[Copies.size() - 1];
1115 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1116 Register SrcReg = FinalCopy->getOperand(1).getReg();
1117
1118 // We need a load with a metadata range for this to break. Fudge the load in
1119 // the string and replace it with something we can work with.
1120 MachineInstr *And = MRI->getVRegDef(SrcReg);
1121 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());
1122 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());
1123 IntegerType *Int8Ty = Type::getInt8Ty(Context);
1124
1125 // Value must be in [0, 2)
1126 Metadata *LowAndHigh[] = {
1127 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),
1128 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};
1129 auto NewMDNode = MDNode::get(Context, LowAndHigh);
1130 const MachineMemOperand *OldMMO = *Load->memoperands_begin();
1131 MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(),
1132 OldMMO->getSizeInBits(), OldMMO->getAlign(),
1133 OldMMO->getAAInfo(), NewMDNode);
1134 MachineIRBuilder MIB(*Load);
1135 MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO);
1136 Load->eraseFromParent();
1137
1138 GISelKnownBits Info(*MF);
1139 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());
1140
1141 // We don't know what the result of the load is, so we don't know any ones.
1142 EXPECT_TRUE(Res.One.isZero());
1143
1144 // We know that the value is in [0, 2). So, we don't know if the first bit
1145 // is 0 or not. However, we do know that every other bit must be 0.
1146 APInt Mask(Res.getBitWidth(), 1);
1147 Mask.flipAllBits();
1148 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());
1149 }
1150
1151 TEST_F(AArch64GISelMITest, TestKnownBitsExt) {
1152 StringRef MIRString = " %c1:_(s16) = G_CONSTANT i16 1\n"
1153 " %x:_(s16) = G_IMPLICIT_DEF\n"
1154 " %y:_(s16) = G_AND %x, %c1\n"
1155 " %anyext:_(s32) = G_ANYEXT %y(s16)\n"
1156 " %r1:_(s32) = COPY %anyext\n"
1157 " %zext:_(s32) = G_ZEXT %y(s16)\n"
1158 " %r2:_(s32) = COPY %zext\n"
1159 " %sext:_(s32) = G_SEXT %y(s16)\n"
1160 " %r3:_(s32) = COPY %sext\n";
1161 setUp(MIRString);
1162 if (!TM)
1163 GTEST_SKIP();
1164 Register CopyRegAny = Copies[Copies.size() - 3];
1165 Register CopyRegZ = Copies[Copies.size() - 2];
1166 Register CopyRegS = Copies[Copies.size() - 1];
1167
1168 GISelKnownBits Info(*MF);
1169 MachineInstr *Copy;
1170 Register SrcReg;
1171 KnownBits Res;
1172
1173 Copy = MRI->getVRegDef(CopyRegAny);
1174 SrcReg = Copy->getOperand(1).getReg();
1175 Res = Info.getKnownBits(SrcReg);
1176 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1177 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1178 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());
1179
1180 Copy = MRI->getVRegDef(CopyRegZ);
1181 SrcReg = Copy->getOperand(1).getReg();
1182 Res = Info.getKnownBits(SrcReg);
1183 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1184 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1185 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1186
1187 Copy = MRI->getVRegDef(CopyRegS);
1188 SrcReg = Copy->getOperand(1).getReg();
1189 Res = Info.getKnownBits(SrcReg);
1190 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1191 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1192 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1193 }
1194
1195 TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {
1196 StringRef MIRString = R"(
1197 ; 000...0001
1198 %one:_(s32) = G_CONSTANT i32 1
1199
1200 ; 000...0010
1201 %two:_(s32) = G_CONSTANT i32 2
1202
1203 ; 000...1010
1204 %ten:_(s32) = G_CONSTANT i32 10
1205
1206 ; ???...????
1207 %w0:_(s32) = COPY $w0
1208
1209 ; ???...?1?
1210 %or:_(s32) = G_OR %w0, %two
1211
1212 ; All bits are known.
1213 %inreg1:_(s32) = G_SEXT_INREG %one, 1
1214 %copy_inreg1:_(s32) = COPY %inreg1
1215
1216 ; All bits unknown
1217 %inreg2:_(s32) = G_SEXT_INREG %or, 1
1218 %copy_inreg2:_(s32) = COPY %inreg2
1219
1220 ; Extending from the only (known) set bit
1221 ; 111...11?
1222 %inreg3:_(s32) = G_SEXT_INREG %or, 2
1223 %copy_inreg3:_(s32) = COPY %inreg3
1224
1225 ; Extending from a known set bit, overwriting all of the high set bits.
1226 ; 111...1110
1227 %inreg4:_(s32) = G_SEXT_INREG %ten, 2
1228 %copy_inreg4:_(s32) = COPY %inreg4
1229
1230 )";
1231 setUp(MIRString);
1232 if (!TM)
1233 GTEST_SKIP();
1234 GISelKnownBits Info(*MF);
1235 KnownBits Res;
1236 auto GetKB = [&](unsigned Idx) {
1237 Register CopyReg = Copies[Idx];
1238 auto *Copy = MRI->getVRegDef(CopyReg);
1239 return Info.getKnownBits(Copy->getOperand(1).getReg());
1240 };
1241
1242 // Every bit is known to be a 1.
1243 Res = GetKB(Copies.size() - 4);
1244 EXPECT_EQ(32u, Res.getBitWidth());
1245 EXPECT_TRUE(Res.isAllOnes());
1246
1247 // All bits are unknown
1248 Res = GetKB(Copies.size() - 3);
1249 EXPECT_EQ(32u, Res.getBitWidth());
1250 EXPECT_TRUE(Res.isUnknown());
1251
1252 // Extending from the only known set bit
1253 // 111...11?
1254 Res = GetKB(Copies.size() - 2);
1255 EXPECT_EQ(32u, Res.getBitWidth());
1256 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1257 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1258
1259 // Extending from a known set bit, overwriting all of the high set bits.
1260 // 111...1110
1261 Res = GetKB(Copies.size() - 1);
1262 EXPECT_EQ(32u, Res.getBitWidth());
1263 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1264 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1265 }
1266
1267 TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {
1268 StringRef MIRString = R"(
1269 ; 000...0001
1270 %one:_(s32) = G_CONSTANT i32 1
1271
1272 ; 000...0010
1273 %two:_(s32) = G_CONSTANT i32 2
1274
1275 ; 000...1010
1276 %ten:_(s32) = G_CONSTANT i32 10
1277
1278 ; ???...????
1279 %w0:_(s32) = COPY $w0
1280
1281 ; ???...?1?
1282 %or:_(s32) = G_OR %w0, %two
1283
1284 ; All bits are known.
1285 %assert_sext1:_(s32) = G_ASSERT_SEXT %one, 1
1286 %copy_assert_sext1:_(s32) = COPY %assert_sext1
1287
1288 ; All bits unknown
1289 %assert_sext2:_(s32) = G_ASSERT_SEXT %or, 1
1290 %copy_assert_sext2:_(s32) = COPY %assert_sext2
1291
1292 ; Extending from the only (known) set bit
1293 ; 111...11?
1294 %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 2
1295 %copy_assert_sext3:_(s32) = COPY %assert_sext3
1296
1297 ; Extending from a known set bit, overwriting all of the high set bits.
1298 ; 111...1110
1299 %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 2
1300 %copy_assert_sext4:_(s32) = COPY %assert_sext4
1301 )";
1302 setUp(MIRString);
1303 if (!TM)
1304 GTEST_SKIP();
1305 GISelKnownBits Info(*MF);
1306 KnownBits Res;
1307 auto GetKB = [&](unsigned Idx) {
1308 Register CopyReg = Copies[Idx];
1309 auto *Copy = MRI->getVRegDef(CopyReg);
1310 return Info.getKnownBits(Copy->getOperand(1).getReg());
1311 };
1312
1313 // Every bit is known to be a 1.
1314 Res = GetKB(Copies.size() - 4);
1315 EXPECT_EQ(32u, Res.getBitWidth());
1316 EXPECT_TRUE(Res.isAllOnes());
1317
1318 // All bits are unknown
1319 Res = GetKB(Copies.size() - 3);
1320 EXPECT_EQ(32u, Res.getBitWidth());
1321 EXPECT_TRUE(Res.isUnknown());
1322
1323 // Extending from the only known set bit
1324 // 111...11?
1325 Res = GetKB(Copies.size() - 2);
1326 EXPECT_EQ(32u, Res.getBitWidth());
1327 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1328 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1329
1330 // Extending from a known set bit, overwriting all of the high set bits.
1331 // 111...1110
1332 Res = GetKB(Copies.size() - 1);
1333 EXPECT_EQ(32u, Res.getBitWidth());
1334 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1335 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1336 }
1337
1338 TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
1339 StringRef MIRString = R"(
1340 %val0:_(s16) = G_CONSTANT i16 35224
1341 %val1:_(s16) = G_CONSTANT i16 17494
1342 %val2:_(s16) = G_CONSTANT i16 4659
1343 %val3:_(s16) = G_CONSTANT i16 43981
1344 %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3
1345 %mergecopy:_(s64) = COPY %merge
1346 )";
1347 setUp(MIRString);
1348 if (!TM)
1349 GTEST_SKIP();
1350
1351 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1352 Register CopyMerge = Copies[Copies.size() - 1];
1353
1354 GISelKnownBits Info(*MF);
1355 KnownBits Res = Info.getKnownBits(CopyMerge);
1356 EXPECT_EQ(64u, Res.getBitWidth());
1357 EXPECT_EQ(TestVal, Res.One.getZExtValue());
1358 EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());
1359 }
1360
1361 TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) {
1362 StringRef MIRString = R"(
1363 %val:_(s64) = G_CONSTANT i64 12379570962110515608
1364 %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val
1365 %part0:_(s16) = COPY %val0
1366 %part1:_(s16) = COPY %val1
1367 %part2:_(s16) = COPY %val2
1368 %part3:_(s16) = COPY %val3
1369
1370 )";
1371 setUp(MIRString);
1372 if (!TM)
1373 GTEST_SKIP();
1374
1375 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1376 GISelKnownBits Info(*MF);
1377
1378 int Offset = -4;
1379 for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) {
1380 Register Part = Copies[Copies.size() + Offset];
1381 KnownBits PartKnown = Info.getKnownBits(Part);
1382 EXPECT_EQ(16u, PartKnown.getBitWidth());
1383
1384 uint16_t PartTestVal = static_cast<uint16_t>(TestVal >> BitOffset);
1385 EXPECT_EQ(PartTestVal, PartKnown.One.getZExtValue());
1386 EXPECT_EQ(static_cast<uint16_t>(~PartTestVal), PartKnown.Zero.getZExtValue());
1387 }
1388 }
1389
1390 TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {
1391 StringRef MIRString = R"(
1392 %const:_(s32) = G_CONSTANT i32 287454020
1393 %bswap:_(s32) = G_BSWAP %const
1394 %bitreverse:_(s32) = G_BITREVERSE %const
1395 %copy_bswap:_(s32) = COPY %bswap
1396 %copy_bitreverse:_(s32) = COPY %bitreverse
1397 )";
1398 setUp(MIRString);
1399 if (!TM)
1400 GTEST_SKIP();
1401
1402 const uint32_t ByteSwappedVal = 0x44332211;
1403 const uint32_t BitSwappedVal = 0x22cc4488;
1404
1405 Register CopyBSwap = Copies[Copies.size() - 2];
1406 Register CopyBitReverse = Copies[Copies.size() - 1];
1407
1408 GISelKnownBits Info(*MF);
1409
1410 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);
1411 EXPECT_EQ(32u, BSwapKnown.getBitWidth());
1412 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());
1413 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());
1414
1415 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);
1416 EXPECT_EQ(32u, BitReverseKnown.getBitWidth());
1417 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());
1418 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());
1419 }
1420
1421 TEST_F(AArch64GISelMITest, TestKnownBitsUMAX) {
1422 StringRef MIRString = R"(
1423 %ptr:_(p0) = G_IMPLICIT_DEF
1424 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1425 %mask0:_(s8) = G_CONSTANT i8 10
1426 %mask1:_(s8) = G_CONSTANT i8 1
1427 %tmp0:_(s8) = G_AND %unknown, %mask0
1428 %val0:_(s8) = G_OR %tmp0, %mask1
1429 %mask2:_(s8) = G_CONSTANT i8 3
1430 %mask3:_(s8) = G_CONSTANT i8 12
1431 %tmp1:_(s8) = G_AND %unknown, %mask2
1432 %val1:_(s8) = G_OR %tmp1, %mask3
1433 %umax0:_(s8) = G_UMAX %val0, %val1
1434 %copy_umax0:_(s8) = COPY %umax0
1435
1436 %mask4:_(s8) = G_CONSTANT i8 14
1437 %mask5:_(s8) = G_CONSTANT i8 2
1438 %tmp3:_(s8) = G_AND %unknown, %mask4
1439 %val3:_(s8) = G_OR %tmp3, %mask5
1440 %mask6:_(s8) = G_CONSTANT i8 4
1441 %mask7:_(s8) = G_CONSTANT i8 11
1442 %tmp4:_(s8) = G_AND %unknown, %mask6
1443 %val4:_(s8) = G_OR %tmp4, %mask7
1444 %umax1:_(s8) = G_UMAX %val3, %val4
1445 %copy_umax1:_(s8) = COPY %umax1
1446 )";
1447
1448 setUp(MIRString);
1449 if (!TM)
1450 GTEST_SKIP();
1451
1452 Register CopyReg0 = Copies[Copies.size() - 2];
1453 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1454 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1455 GISelKnownBits Info(*MF);
1456 // Compares min/max of LHS and RHS, min uses 0 for unknown bits, max uses 1.
1457 // If min(LHS) >= max(RHS) returns KnownBits for LHS, similar for RHS. If this
1458 // fails tries to calculate individual bits: common bits for both operands and
1459 // a few leading bits in some cases.
1460 // 0000?0?1
1461 // umax 000011??
1462 // = 000011??
1463 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1464 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());
1465 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());
1466
1467 Register CopyReg1 = Copies[Copies.size() - 1];
1468 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
1469 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
1470 KnownBits Res1 = Info.getKnownBits(SrcReg1);
1471 // 0000??10
1472 // umax 00001?11
1473 // = 00001?1?
1474 EXPECT_EQ(0x0Au, Res1.One.getZExtValue());
1475 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());
1476 }
1477
1478 TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {
1479 StringRef MIRString = R"(
1480 %val:_(s32) = COPY $w0
1481 %zext:_(s64) = G_ZEXT %val
1482 %const:_(s64) = G_CONSTANT i64 -256
1483 %umax:_(s64) = G_UMAX %zext, %const
1484 %copy_umax:_(s64) = COPY %umax
1485 )";
1486 setUp(MIRString);
1487 if (!TM)
1488 GTEST_SKIP();
1489
1490 Register CopyUMax = Copies[Copies.size() - 1];
1491 GISelKnownBits Info(*MF);
1492
1493 KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
1494 EXPECT_EQ(64u, KnownUmax.getBitWidth());
1495 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1496 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1497
1498 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1499 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1500 }
1501
1502 TEST_F(AArch64GISelMITest, TestKnownBitsUMIN) {
1503 StringRef MIRString = R"(
1504 %ptr:_(p0) = G_IMPLICIT_DEF
1505 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1506 %mask0:_(s8) = G_CONSTANT i8 10
1507 %mask1:_(s8) = G_CONSTANT i8 1
1508 %tmp0:_(s8) = G_AND %unknown, %mask0
1509 %val0:_(s8) = G_OR %tmp0, %mask1
1510 %mask2:_(s8) = G_CONSTANT i8 3
1511 %mask3:_(s8) = G_CONSTANT i8 12
1512 %tmp1:_(s8) = G_AND %unknown, %mask2
1513 %val1:_(s8) = G_OR %tmp1, %mask3
1514 %umin:_(s8) = G_UMIN %val0, %val1
1515 %copy_umin:_(s8) = COPY %umin
1516 )";
1517
1518 setUp(MIRString);
1519 if (!TM)
1520 GTEST_SKIP();
1521
1522 Register CopyReg0 = Copies[Copies.size() - 1];
1523 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1524 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1525 GISelKnownBits Info(*MF);
1526 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1527 // Flips the range of operands: [0, 0xFFFFFFFF] <-> [0xFFFFFFFF, 0],
1528 // uses umax and flips result back.
1529 // 0000?0?1
1530 // umin 000011??
1531 // = 0000?0?1
1532 EXPECT_EQ(0x01u, Res0.One.getZExtValue());
1533 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());
1534 }
1535
1536 TEST_F(AArch64GISelMITest, TestKnownBitsSMAX) {
1537 StringRef MIRString = R"(
1538 %ptr:_(p0) = G_IMPLICIT_DEF
1539 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1540 %mask0:_(s8) = G_CONSTANT i8 128
1541 %mask1:_(s8) = G_CONSTANT i8 64
1542 %tmp0:_(s8) = G_AND %unknown, %mask0
1543 %val0:_(s8) = G_OR %tmp0, %mask1
1544 %mask2:_(s8) = G_CONSTANT i8 1
1545 %mask3:_(s8) = G_CONSTANT i8 128
1546 %tmp1:_(s8) = G_AND %unknown, %mask2
1547 %val1:_(s8) = G_OR %tmp1, %mask3
1548 %smax:_(s8) = G_SMAX %val0, %val1
1549 %copy_smax:_(s8) = COPY %smax
1550 )";
1551
1552 setUp(MIRString);
1553 if (!TM)
1554 GTEST_SKIP();
1555
1556 Register CopyReg0 = Copies[Copies.size() - 1];
1557 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1558 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1559 GISelKnownBits Info(*MF);
1560 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1561 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0, 0xFFFFFFFF],
1562 // uses umax and flips result back.
1563 // RHS is negative, LHS is either positive or negative with smaller abs value.
1564 // ?1000000
1565 // smax 1000000?
1566 // = ?1000000
1567 EXPECT_EQ(0x40u, Res0.One.getZExtValue());
1568 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());
1569 }
1570
1571 TEST_F(AArch64GISelMITest, TestKnownBitsSMIN) {
1572 StringRef MIRString = R"(
1573 %ptr:_(p0) = G_IMPLICIT_DEF
1574 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1575 %mask0:_(s8) = G_CONSTANT i8 128
1576 %mask1:_(s8) = G_CONSTANT i8 64
1577 %tmp0:_(s8) = G_AND %unknown, %mask0
1578 %val0:_(s8) = G_OR %tmp0, %mask1
1579 %mask2:_(s8) = G_CONSTANT i8 1
1580 %mask3:_(s8) = G_CONSTANT i8 128
1581 %tmp1:_(s8) = G_AND %unknown, %mask2
1582 %val1:_(s8) = G_OR %tmp1, %mask3
1583 %smin:_(s8) = G_SMIN %val0, %val1
1584 %copy_smin:_(s8) = COPY %smin
1585 )";
1586
1587 setUp(MIRString);
1588 if (!TM)
1589 GTEST_SKIP();
1590
1591 Register CopyReg0 = Copies[Copies.size() - 1];
1592 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1593 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1594 GISelKnownBits Info(*MF);
1595 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1596 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0xFFFFFFFF, 0],
1597 // uses umax and flips result back.
1598 // RHS is negative, LHS is either positive or negative with smaller abs value.
1599 // ?1000000
1600 // smin 1000000?
1601 // = 1000000?
1602 EXPECT_EQ(0x80u, Res0.One.getZExtValue());
1603 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());
1604 }
1605
1606 TEST_F(AArch64GISelMITest, TestInvalidQueries) {
1607 StringRef MIRString = R"(
1608 %src:_(s32) = COPY $w0
1609 %thirty2:_(s32) = G_CONSTANT i32 32
1610 %equalSized:_(s32) = G_SHL %src, %thirty2
1611 %copy1:_(s32) = COPY %equalSized
1612 %thirty3:_(s32) = G_CONSTANT i32 33
1613 %biggerSized:_(s32) = G_SHL %src, %thirty3
1614 %copy2:_(s32) = COPY %biggerSized
1615 )";
1616 setUp(MIRString);
1617 if (!TM)
1618 GTEST_SKIP();
1619
1620 Register EqSizedCopyReg = Copies[Copies.size() - 2];
1621 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
1622 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
1623
1624 Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
1625 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
1626 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
1627
1628 GISelKnownBits Info(*MF);
1629 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
1630 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
1631
1632
1633 // Result can be anything, but we should not crash.
1634 EXPECT_TRUE(EqSizeRes.One.isZero());
1635 EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());
1636
1637 EXPECT_TRUE(BiggerSizeRes.One.isZero());
1638 EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());
1639 }
1640
1641 TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
1642 StringRef MIRString = R"(
1643 %copy:_(s64) = COPY $x0
1644
1645 %assert8:_(s64) = G_ASSERT_ZEXT %copy, 8
1646 %copy_assert8:_(s64) = COPY %assert8
1647
1648 %assert1:_(s64) = G_ASSERT_ZEXT %copy, 1
1649 %copy_assert1:_(s64) = COPY %assert1
1650
1651 %assert63:_(s64) = G_ASSERT_ZEXT %copy, 63
1652 %copy_assert63:_(s64) = COPY %assert63
1653
1654 %assert3:_(s64) = G_ASSERT_ZEXT %copy, 3
1655 %copy_assert3:_(s64) = COPY %assert3
1656 )";
1657
1658 setUp(MIRString);
1659 if (!TM)
1660 GTEST_SKIP();
1661
1662 Register CopyAssert8 = Copies[Copies.size() - 4];
1663 Register CopyAssert1 = Copies[Copies.size() - 3];
1664 Register CopyAssert63 = Copies[Copies.size() - 2];
1665 Register CopyAssert3 = Copies[Copies.size() - 1];
1666
1667 GISelKnownBits Info(*MF);
1668 MachineInstr *Copy;
1669 Register SrcReg;
1670 KnownBits Res;
1671
1672 // Assert zero-extension from an 8-bit value.
1673 Copy = MRI->getVRegDef(CopyAssert8);
1674 SrcReg = Copy->getOperand(1).getReg();
1675 Res = Info.getKnownBits(SrcReg);
1676 EXPECT_EQ(64u, Res.getBitWidth());
1677 EXPECT_EQ(0u, Res.One.getZExtValue());
1678 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());
1679
1680 // Assert zero-extension from a 1-bit value.
1681 Copy = MRI->getVRegDef(CopyAssert1);
1682 SrcReg = Copy->getOperand(1).getReg();
1683 Res = Info.getKnownBits(SrcReg);
1684 EXPECT_EQ(64u, Res.getBitWidth());
1685 EXPECT_EQ(0u, Res.One.getZExtValue());
1686 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());
1687
1688 // Assert zero-extension from a 63-bit value.
1689 Copy = MRI->getVRegDef(CopyAssert63);
1690 SrcReg = Copy->getOperand(1).getReg();
1691 Res = Info.getKnownBits(SrcReg);
1692 EXPECT_EQ(64u, Res.getBitWidth());
1693 EXPECT_EQ(0u, Res.One.getZExtValue());
1694 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());
1695
1696 // Assert zero-extension from a 3-bit value.
1697 Copy = MRI->getVRegDef(CopyAssert3);
1698 SrcReg = Copy->getOperand(1).getReg();
1699 Res = Info.getKnownBits(SrcReg);
1700 EXPECT_EQ(64u, Res.getBitWidth());
1701 EXPECT_EQ(0u, Res.One.getZExtValue());
1702 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());
1703 }
1704
1705 TEST_F(AArch64GISelMITest, TestKnownBitsCTPOP) {
1706 StringRef MIRString = R"(
1707 %src:_(s32) = COPY $w0
1708 %unknown:_(s32) = G_CTPOP %src
1709 %unknown_copy:_(s32) = COPY %unknown
1710 %constant_4294967295:_(s32) = G_CONSTANT i32 4294967295
1711 %thirtytwo:_(s32) = G_CTPOP %constant_4294967295
1712 %thirtytwo_copy:_(s32) = COPY %thirtytwo
1713 %constant_15:_(s32) = G_CONSTANT i32 15
1714 %four:_(s32) = G_CTPOP %constant_15
1715 %four_copy:_(s32) = COPY %four
1716 %constant_1:_(s32) = G_CONSTANT i32 1
1717 %one:_(s32) = G_CTPOP %constant_1
1718 %one_copy:_(s32) = COPY %one
1719 )";
1720 setUp(MIRString);
1721 if (!TM)
1722 GTEST_SKIP();
1723
1724 Register UnknownCopy = Copies[Copies.size() - 4];
1725 Register ThirtytwoCopy = Copies[Copies.size() - 3];
1726 Register FourCopy = Copies[Copies.size() - 2];
1727 Register OneCopy = Copies[Copies.size() - 1];
1728
1729 GISelKnownBits Info(*MF);
1730 MachineInstr *Copy;
1731 Register SrcReg;
1732 KnownBits Res;
1733
1734 Copy = MRI->getVRegDef(UnknownCopy);
1735 SrcReg = Copy->getOperand(1).getReg();
1736 Res = Info.getKnownBits(SrcReg);
1737 EXPECT_EQ(32u, Res.getBitWidth());
1738 EXPECT_EQ(0u, Res.One.getZExtValue());
1739 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1740
1741 Copy = MRI->getVRegDef(ThirtytwoCopy);
1742 SrcReg = Copy->getOperand(1).getReg();
1743 Res = Info.getKnownBits(SrcReg);
1744 EXPECT_EQ(32u, Res.getBitWidth());
1745 EXPECT_EQ(0u, Res.One.getZExtValue());
1746 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1747
1748 Copy = MRI->getVRegDef(FourCopy);
1749 SrcReg = Copy->getOperand(1).getReg();
1750 Res = Info.getKnownBits(SrcReg);
1751 EXPECT_EQ(32u, Res.getBitWidth());
1752 EXPECT_EQ(0u, Res.One.getZExtValue());
1753 EXPECT_EQ(0xFFFFFFF8u, Res.Zero.getZExtValue());
1754
1755 Copy = MRI->getVRegDef(OneCopy);
1756 SrcReg = Copy->getOperand(1).getReg();
1757 Res = Info.getKnownBits(SrcReg);
1758 EXPECT_EQ(32u, Res.getBitWidth());
1759 EXPECT_EQ(0u, Res.One.getZExtValue());
1760 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
1761 }
1762
1763 TEST_F(AMDGPUGISelMITest, TestKnownBitsUBFX) {
1764 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1765 " %4:_(s32) = G_CONSTANT i32 12\n"
1766 " %5:_(s32) = G_CONSTANT i32 8\n"
1767 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
1768 " %ubfx_copy:_(s32) = COPY %6\n"
1769 " %7:_(s32) = G_CONSTANT i32 28672\n"
1770 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
1771 " %ubfx_copy_val:_(s32) = COPY %8\n"
1772 " %9:_(s32) = G_IMPLICIT_DEF\n"
1773 " %10:_(s32) = G_IMPLICIT_DEF\n"
1774 " %11:_(s32) = G_UBFX %3, %9(s32), %10\n"
1775 " %ubfx_copy_unk:_(s32) = COPY %11\n"
1776 " %12:_(s32) = G_UBFX %3, %9(s32), %5\n"
1777 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
1778 " %13:_(s32) = G_UBFX %3, %4(s32), %10\n"
1779 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
1780 setUp(MIRString);
1781 if (!TM)
1782 GTEST_SKIP();
1783 Register CopyBfxReg = Copies[Copies.size() - 5];
1784 Register CopyValBfxReg = Copies[Copies.size() - 4];
1785 Register CopyUnkBfxReg = Copies[Copies.size() - 3];
1786 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1787 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1788
1789 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
1790 Register SrcReg = CopyBfx->getOperand(1).getReg();
1791 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
1792 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
1793 MachineInstr *CopyUnkBfx = MRI->getVRegDef(CopyUnkBfxReg);
1794 Register UnkSrcReg = CopyUnkBfx->getOperand(1).getReg();
1795 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
1796 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
1797 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
1798 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
1799
1800 GISelKnownBits Info(*MF);
1801
1802 KnownBits Res1 = Info.getKnownBits(SrcReg);
1803 EXPECT_EQ(0u, Res1.One.getZExtValue());
1804 EXPECT_EQ(0xffffff00u, Res1.Zero.getZExtValue());
1805
1806 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
1807 EXPECT_EQ(7u, Res2.One.getZExtValue());
1808 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
1809
1810 KnownBits Res3 = Info.getKnownBits(UnkSrcReg);
1811 EXPECT_EQ(0u, Res3.One.getZExtValue());
1812 EXPECT_EQ(0u, Res3.Zero.getZExtValue());
1813
1814 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
1815 EXPECT_EQ(0u, Res4.One.getZExtValue());
1816 EXPECT_EQ(0xffffff00u, Res4.Zero.getZExtValue());
1817
1818 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
1819 EXPECT_EQ(0u, Res5.One.getZExtValue());
1820 EXPECT_EQ(0xfff00000u, Res5.Zero.getZExtValue());
1821 }
1822
1823 TEST_F(AMDGPUGISelMITest, TestKnownBitsSBFX) {
1824 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1825 " %4:_(s32) = G_CONSTANT i32 8\n"
1826 " %5:_(s32) = G_CONSTANT i32 4\n"
1827 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
1828 " %sbfx_copy:_(s32) = COPY %6\n"
1829 " %7:_(s32) = G_CONSTANT i32 2047\n"
1830 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
1831 " %sbfx_copy_val:_(s32) = COPY %8\n"
1832 " %9:_(s32) = G_CONSTANT i32 2048\n"
1833 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
1834 " %sbfx_copy_neg_val:_(s32) = COPY %10\n"
1835 " %11:_(s32) = G_IMPLICIT_DEF\n"
1836 " %12:_(s32) = G_SBFX %7, %11(s32), %5\n"
1837 " %sbfx_copy_unk_off:_(s32) = COPY %12\n"
1838 " %13:_(s32) = G_SBFX %9, %4(s32), %11\n"
1839 " %sbfx_copy_unk_width:_(s32) = COPY %13\n";
1840 setUp(MIRString);
1841 if (!TM)
1842 GTEST_SKIP();
1843 Register CopyBfxReg = Copies[Copies.size() - 5];
1844 Register CopyValBfxReg = Copies[Copies.size() - 4];
1845 Register CopyNegValBfxReg = Copies[Copies.size() - 3];
1846 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1847 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1848
1849 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
1850 Register SrcReg = CopyBfx->getOperand(1).getReg();
1851 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
1852 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
1853 MachineInstr *CopyNegValBfx = MRI->getVRegDef(CopyNegValBfxReg);
1854 Register NegValSrcReg = CopyNegValBfx->getOperand(1).getReg();
1855 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
1856 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
1857 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
1858 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
1859
1860 GISelKnownBits Info(*MF);
1861
1862 KnownBits Res1 = Info.getKnownBits(SrcReg);
1863 EXPECT_EQ(0u, Res1.One.getZExtValue());
1864 EXPECT_EQ(0u, Res1.Zero.getZExtValue());
1865
1866 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
1867 EXPECT_EQ(7u, Res2.One.getZExtValue());
1868 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
1869
1870 KnownBits Res3 = Info.getKnownBits(NegValSrcReg);
1871 EXPECT_EQ(0xfffffff8u, Res3.One.getZExtValue());
1872 EXPECT_EQ(7u, Res3.Zero.getZExtValue());
1873
1874 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
1875 EXPECT_EQ(0u, Res4.One.getZExtValue());
1876 EXPECT_EQ(0u, Res4.Zero.getZExtValue());
1877
1878 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
1879 EXPECT_EQ(0u, Res5.One.getZExtValue());
1880 EXPECT_EQ(0u, Res5.Zero.getZExtValue());
1881 }
1882
1883 TEST_F(AMDGPUGISelMITest, TestNumSignBitsUBFX) {
1884 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1885 " %4:_(s32) = G_CONSTANT i32 12\n"
1886 " %5:_(s32) = G_CONSTANT i32 8\n"
1887 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
1888 " %ubfx_copy_unk:_(s32) = COPY %6\n"
1889 " %7:_(s32) = G_CONSTANT i32 28672\n"
1890 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
1891 " %ubfx_copy_pos:_(s32) = COPY %8\n"
1892 " %9:_(s32) = G_CONSTANT i32 -1\n"
1893 " %10:_(s32) = G_UBFX %9, %4(s32), %5\n"
1894 " %ubfx_copy_neg:_(s32) = COPY %10\n"
1895 " %11:_(s32) = G_IMPLICIT_DEF\n"
1896 " %12:_(s32) = G_UBFX %7, %11(s32), %5\n"
1897 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
1898 " %13:_(s32) = G_UBFX %7, %4(s32), %11\n"
1899 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
1900 setUp(MIRString);
1901 if (!TM)
1902 GTEST_SKIP();
1903 Register CopyUnkBfxReg = Copies[Copies.size() - 5];
1904 Register CopyPosBfxReg = Copies[Copies.size() - 4];
1905 Register CopyNegBfxReg = Copies[Copies.size() - 3];
1906 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1907 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1908
1909 GISelKnownBits Info(*MF);
1910 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkBfxReg));
1911 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
1912 EXPECT_EQ(24u, Info.computeNumSignBits(CopyNegBfxReg));
1913 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkOffBfxReg));
1914 EXPECT_EQ(29u, Info.computeNumSignBits(CopyUnkWidthBfxReg));
1915 }
1916
1917 TEST_F(AMDGPUGISelMITest, TestNumSignBitsSBFX) {
1918 StringRef MIRString = " %3:_(s32) = G_CONSTANT i32 -1\n"
1919 " %4:_(s32) = G_CONSTANT i32 8\n"
1920 " %5:_(s32) = G_CONSTANT i32 4\n"
1921 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
1922 " %sbfx_copy_neg:_(s32) = COPY %6\n"
1923 " %7:_(s32) = G_CONSTANT i32 2047\n"
1924 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
1925 " %sbfx_copy_pos:_(s32) = COPY %8\n"
1926 " %9:_(s32) = G_CONSTANT i32 2048\n"
1927 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
1928 " %sbfx_copy_hiset:_(s32) = COPY %10\n"
1929 " %11:_(s32) = G_IMPLICIT_DEF\n"
1930 " %12:_(s32) = G_SBFX %11, %4(s32), %5\n"
1931 " %sbfx_copy_unk:_(s32) = COPY %12\n"
1932 " %13:_(s32) = G_SBFX %3, %11(s32), %5\n"
1933 " %sbfx_copy_unk_off:_(s32) = COPY %13\n";
1934 setUp(MIRString);
1935 if (!TM)
1936 GTEST_SKIP();
1937 Register CopyNegBfxReg = Copies[Copies.size() - 5];
1938 Register CopyPosBfxReg = Copies[Copies.size() - 4];
1939 Register CopyHiSetBfxReg = Copies[Copies.size() - 3];
1940 Register CopyUnkValBfxReg = Copies[Copies.size() - 2];
1941 Register CopyUnkOffBfxReg = Copies[Copies.size() - 1];
1942
1943 GISelKnownBits Info(*MF);
1944 EXPECT_EQ(32u, Info.computeNumSignBits(CopyNegBfxReg));
1945 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
1946 EXPECT_EQ(29u, Info.computeNumSignBits(CopyHiSetBfxReg));
1947 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkValBfxReg));
1948 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkOffBfxReg));
1949 }
1950
1951 TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
1952 StringRef MIRString = R"MIR(
1953 %val:_(s64) = COPY $vgpr0_vgpr1
1954 %ptrval:_(p1) = COPY $vgpr0_vgpr1
1955
1956 %assert_align1:_(s64) = G_ASSERT_ALIGN %val, 1
1957 %copy_assert_align1:_(s64) = COPY %assert_align1
1958
1959 %assert_align2:_(s64) = G_ASSERT_ALIGN %val, 2
1960 %copy_assert_align2:_(s64) = COPY %assert_align2
1961
1962 %assert_align4:_(s64) = G_ASSERT_ALIGN %val, 4
1963 %copy_assert_align4:_(s64) = COPY %assert_align4
1964
1965 %assert_align8:_(s64) = G_ASSERT_ALIGN %val, 8
1966 %copy_assert_align8:_(s64) = COPY %assert_align8
1967
1968 %assert_align16:_(s64) = G_ASSERT_ALIGN %val, 16
1969 %copy_assert_maxalign:_(s64) = COPY %assert_align16
1970 )MIR";
1971 setUp(MIRString);
1972 if (!TM)
1973 GTEST_SKIP();
1974 GISelKnownBits Info(*MF);
1975
1976 KnownBits Res;
1977 auto GetKB = [&](unsigned Idx) {
1978 Register CopyReg = Copies[Idx];
1979 auto *Copy = MRI->getVRegDef(CopyReg);
1980 return Info.getKnownBits(Copy->getOperand(1).getReg());
1981 };
1982
1983 auto CheckBits = [&](unsigned NumBits, unsigned Idx) {
1984 Res = GetKB(Idx);
1985 EXPECT_EQ(64u, Res.getBitWidth());
1986 EXPECT_EQ(NumBits - 1, Res.Zero.countr_one());
1987 EXPECT_EQ(64u, Res.One.countr_zero());
1988 EXPECT_EQ(Align(1ull << (NumBits - 1)), Info.computeKnownAlignment(Copies[Idx]));
1989 };
1990
1991 const unsigned NumSetupCopies = 5;
1992 CheckBits(1, NumSetupCopies);
1993 CheckBits(2, NumSetupCopies + 1);
1994 CheckBits(3, NumSetupCopies + 2);
1995 CheckBits(4, NumSetupCopies + 3);
1996 CheckBits(5, NumSetupCopies + 4);
1997 }
1998
1999 TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
2000 StringRef MIRString = R"(
2001 %ptr:_(p0) = G_IMPLICIT_DEF
2002 %ld0:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
2003 %ld1:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
2004
2005 %add:_(s32), %overflow:_(s32) = G_UADDO %ld0, %ld1
2006 %copy_overflow:_(s32) = COPY %overflow
2007 )";
2008
2009 setUp(MIRString);
2010 if (!TM)
2011 GTEST_SKIP();
2012
2013 Register CopyOverflow = Copies[Copies.size() - 1];
2014 GISelKnownBits Info(*MF);
2015 KnownBits Res = Info.getKnownBits(CopyOverflow);
2016 EXPECT_EQ(0u, Res.One.getZExtValue());
2017 EXPECT_EQ(31u, Res.Zero.countl_one());
2018 }
LLVM monorepo