[AMDGPU] Add True16 register classes.
[llvm-project.git] / lldb / unittests / Disassembler / RISCV / TestMCDisasmInstanceRISCV.cpp
blob2f2585a23d7624c8c1d2bab3f2a559e119a3e34c
1 //===-- TestMCDisasmInstanceRISCV.cpp -------------------------------------===//
3 //
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Support/TargetSelect.h"
11 #include "gtest/gtest.h"
13 #include "lldb/Core/Address.h"
14 #include "lldb/Core/Disassembler.h"
15 #include "lldb/Target/ExecutionContext.h"
16 #include "lldb/Utility/ArchSpec.h"
18 #include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
20 using namespace lldb;
21 using namespace lldb_private;
23 namespace {
24 class TestMCDisasmInstanceRISCV : public testing::Test {
25 public:
26 static void SetUpTestCase();
27 static void TearDownTestCase();
29 protected:
32 void TestMCDisasmInstanceRISCV::SetUpTestCase() {
33 llvm::InitializeAllTargets();
34 llvm::InitializeAllAsmPrinters();
35 llvm::InitializeAllTargetMCs();
36 llvm::InitializeAllDisassemblers();
37 DisassemblerLLVMC::Initialize();
40 void TestMCDisasmInstanceRISCV::TearDownTestCase() {
41 DisassemblerLLVMC::Terminate();
43 } // namespace
45 TEST_F(TestMCDisasmInstanceRISCV, TestRISCV32Instruction) {
46 ArchSpec arch("riscv32-*-linux");
48 const unsigned num_of_instructions = 5;
49 uint8_t data[] = {
50 0xef, 0x00, 0x00, 0x00, // call -- jal x1, 0
51 0xe7, 0x00, 0x00, 0x00, // call -- jalr x1, x0, 0
52 0x6f, 0x00, 0x00, 0x00, // jump -- jal x0, 0
53 0x67, 0x00, 0x00, 0x00, // jump -- jalr x0, x0, 0
54 0x67, 0x80, 0x00, 0x00 // ret -- jalr x0, x1, 0
57 DisassemblerSP disass_sp;
58 Address start_addr(0x100);
59 disass_sp =
60 Disassembler::DisassembleBytes(arch, nullptr, nullptr, start_addr, &data,
61 sizeof (data), num_of_instructions, false);
63 // If we failed to get a disassembler, we can assume it is because
64 // the llvm we linked against was not built with the riscv target,
65 // and we should skip these tests without marking anything as failing.
66 if (!disass_sp)
67 return;
69 const InstructionList inst_list(disass_sp->GetInstructionList());
70 EXPECT_EQ(num_of_instructions, inst_list.GetSize());
72 InstructionSP inst_sp;
73 inst_sp = inst_list.GetInstructionAtIndex(0);
74 EXPECT_TRUE(inst_sp->IsCall());
75 EXPECT_TRUE(inst_sp->DoesBranch());
77 inst_sp = inst_list.GetInstructionAtIndex(1);
78 EXPECT_TRUE(inst_sp->IsCall());
79 EXPECT_TRUE(inst_sp->DoesBranch());
81 inst_sp = inst_list.GetInstructionAtIndex(2);
82 EXPECT_FALSE(inst_sp->IsCall());
83 EXPECT_TRUE(inst_sp->DoesBranch());
85 inst_sp = inst_list.GetInstructionAtIndex(3);
86 EXPECT_FALSE(inst_sp->IsCall());
87 EXPECT_TRUE(inst_sp->DoesBranch());
89 inst_sp = inst_list.GetInstructionAtIndex(4);
90 EXPECT_FALSE(inst_sp->IsCall());
91 EXPECT_TRUE(inst_sp->DoesBranch());