| blob | fe649d4333041783361a4ced0ecae6a7a5caacb4 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11 %s
5 define amdgpu_ps float @_amdgpu_ps_main() #0 {
6 ; GFX10-LABEL: _amdgpu_ps_main:
7 ; GFX10: ; %bb.0: ; %.entry
8 ; GFX10-NEXT: image_sample v[0:1], v[0:1], s[0:7], s[0:3] dmask:0x3 dim:SQ_RSRC_IMG_2D
9 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
10 ; GFX10-NEXT: s_waitcnt vmcnt(0)
11 ; GFX10-NEXT: s_clause 0x1
12 ; GFX10-NEXT: image_sample v2, v[0:1], s[0:7], s[0:3] dmask:0x4 dim:SQ_RSRC_IMG_2D
13 ; GFX10-NEXT: image_sample v3, v[0:1], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
14 ; GFX10-NEXT: s_waitcnt vmcnt(0)
15 ; GFX10-NEXT: image_load_mip v4, v[2:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
16 ; GFX10-NEXT: s_clause 0x3
17 ; GFX10-NEXT: s_buffer_load_dword s24, s[0:3], 0x5c
18 ; GFX10-NEXT: s_buffer_load_dword s28, s[0:3], 0x7c
19 ; GFX10-NEXT: s_buffer_load_dword s29, s[0:3], 0xc0
20 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
21 ; GFX10-NEXT: s_nop 0
22 ; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x40
23 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
24 ; GFX10-NEXT: s_clause 0x1
25 ; GFX10-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x50
26 ; GFX10-NEXT: s_nop 0
27 ; GFX10-NEXT: s_buffer_load_dword s0, s[0:3], 0x2c
28 ; GFX10-NEXT: v_sub_f32_e64 v5, s24, s28
29 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
30 ; GFX10-NEXT: s_clause 0x4
31 ; GFX10-NEXT: s_buffer_load_dwordx4 s[8:11], s[0:3], 0x60
32 ; GFX10-NEXT: s_buffer_load_dwordx4 s[12:15], s[0:3], 0x20
33 ; GFX10-NEXT: s_buffer_load_dwordx4 s[16:19], s[0:3], 0x0
34 ; GFX10-NEXT: s_buffer_load_dwordx4 s[20:23], s[0:3], 0x70
35 ; GFX10-NEXT: s_buffer_load_dwordx4 s[24:27], s[0:3], 0x10
36 ; GFX10-NEXT: v_fma_f32 v1, v1, v5, s28
37 ; GFX10-NEXT: v_max_f32_e64 v6, s0, s0 clamp
38 ; GFX10-NEXT: v_add_f32_e64 v5, s29, -1.0
39 ; GFX10-NEXT: v_sub_f32_e32 v8, s0, v1
40 ; GFX10-NEXT: v_fma_f32 v7, -s2, v6, s6
41 ; GFX10-NEXT: v_fma_f32 v5, v6, v5, 1.0
42 ; GFX10-NEXT: v_mad_f32 v10, s2, v6, v2
43 ; GFX10-NEXT: s_mov_b32 s0, 0x3c23d70a
44 ; GFX10-NEXT: v_fmac_f32_e32 v1, v6, v8
45 ; GFX10-NEXT: v_fmac_f32_e32 v10, v7, v6
46 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
47 ; GFX10-NEXT: v_mul_f32_e32 v9, s10, v0
48 ; GFX10-NEXT: v_fma_f32 v0, -v0, s10, s14
49 ; GFX10-NEXT: v_mul_f32_e32 v8, s18, v2
50 ; GFX10-NEXT: v_mul_f32_e32 v3, s22, v3
51 ; GFX10-NEXT: v_fmac_f32_e32 v9, v0, v6
52 ; GFX10-NEXT: v_sub_f32_e32 v0, v1, v5
53 ; GFX10-NEXT: v_mul_f32_e32 v1, v8, v6
54 ; GFX10-NEXT: v_mul_f32_e32 v7, v6, v3
55 ; GFX10-NEXT: v_fma_f32 v3, -v6, v3, v9
56 ; GFX10-NEXT: v_fmac_f32_e32 v5, v0, v6
57 ; GFX10-NEXT: v_fma_f32 v0, v2, s26, -v1
58 ; GFX10-NEXT: v_fmac_f32_e32 v7, v3, v6
59 ; GFX10-NEXT: v_fmac_f32_e32 v1, v0, v6
60 ; GFX10-NEXT: v_mul_f32_e32 v0, v2, v6
61 ; GFX10-NEXT: s_waitcnt vmcnt(0)
62 ; GFX10-NEXT: v_add_f32_e32 v4, v4, v10
63 ; GFX10-NEXT: v_mul_f32_e32 v3, v4, v6
64 ; GFX10-NEXT: v_fmaak_f32 v4, s0, v5, 0x3ca3d70a
65 ; GFX10-NEXT: v_mul_f32_e32 v1, v3, v1
66 ; GFX10-NEXT: v_mul_f32_e32 v2, v7, v4
67 ; GFX10-NEXT: v_fmac_f32_e32 v1, v2, v0
68 ; GFX10-NEXT: v_max_f32_e32 v0, 0, v1
69 ; GFX10-NEXT: ; return to shader part epilog
70 ;
71 ; GFX11-LABEL: _amdgpu_ps_main:
72 ; GFX11: ; %bb.0: ; %.entry
73 ; GFX11-NEXT: image_sample v[0:1], v[0:1], s[0:7], s[0:3] dmask:0x3 dim:SQ_RSRC_IMG_2D
74 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
75 ; GFX11-NEXT: s_waitcnt vmcnt(0)
76 ; GFX11-NEXT: s_clause 0x1
77 ; GFX11-NEXT: image_sample v2, v[0:1], s[0:7], s[0:3] dmask:0x4 dim:SQ_RSRC_IMG_2D
78 ; GFX11-NEXT: image_sample v3, v[0:1], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
79 ; GFX11-NEXT: s_waitcnt vmcnt(0)
80 ; GFX11-NEXT: image_load_mip v4, v[2:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
81 ; GFX11-NEXT: s_clause 0x3
82 ; GFX11-NEXT: s_buffer_load_b32 s24, s[0:3], 0x5c
83 ; GFX11-NEXT: s_buffer_load_b32 s28, s[0:3], 0x7c
84 ; GFX11-NEXT: s_buffer_load_b32 s29, s[0:3], 0xc0
85 ; GFX11-NEXT: s_buffer_load_b128 s[0:3], s[0:3], 0x40
86 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
87 ; GFX11-NEXT: s_clause 0x1
88 ; GFX11-NEXT: s_buffer_load_b128 s[4:7], s[0:3], 0x50
89 ; GFX11-NEXT: s_buffer_load_b32 s0, s[0:3], 0x2c
90 ; GFX11-NEXT: v_sub_f32_e64 v5, s24, s28
91 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
92 ; GFX11-NEXT: s_clause 0x3
93 ; GFX11-NEXT: s_buffer_load_b128 s[8:11], s[0:3], 0x60
94 ; GFX11-NEXT: s_buffer_load_b128 s[12:15], s[0:3], 0x20
95 ; GFX11-NEXT: s_buffer_load_b128 s[16:19], s[0:3], 0x0
96 ; GFX11-NEXT: s_buffer_load_b128 s[20:23], s[0:3], 0x70
97 ; GFX11-NEXT: v_fma_f32 v1, v1, v5, s28
98 ; GFX11-NEXT: v_max_f32_e64 v6, s0, s0 clamp
99 ; GFX11-NEXT: s_buffer_load_b128 s[24:27], s[0:3], 0x10
100 ; GFX11-NEXT: v_add_f32_e64 v5, s29, -1.0
101 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
102 ; GFX11-NEXT: v_sub_f32_e32 v8, s0, v1
103 ; GFX11-NEXT: v_fma_f32 v7, -s2, v6, s6
104 ; GFX11-NEXT: v_fma_f32 v10, s2, v6, v2
105 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
106 ; GFX11-NEXT: v_fma_f32 v5, v6, v5, 1.0
107 ; GFX11-NEXT: s_mov_b32 s0, 0x3c23d70a
108 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
109 ; GFX11-NEXT: v_mul_f32_e32 v9, s10, v0
110 ; GFX11-NEXT: v_fma_f32 v0, -v0, s10, s14
111 ; GFX11-NEXT: v_mul_f32_e32 v3, s22, v3
112 ; GFX11-NEXT: v_dual_fmac_f32 v1, v6, v8 :: v_dual_mul_f32 v8, s18, v2
113 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
114 ; GFX11-NEXT: v_fmac_f32_e32 v9, v0, v6
115 ; GFX11-NEXT: v_dual_fmac_f32 v10, v7, v6 :: v_dual_mul_f32 v7, v6, v3
116 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
117 ; GFX11-NEXT: v_sub_f32_e32 v0, v1, v5
118 ; GFX11-NEXT: v_fma_f32 v3, -v6, v3, v9
119 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
120 ; GFX11-NEXT: v_fmac_f32_e32 v7, v3, v6
121 ; GFX11-NEXT: v_fmac_f32_e32 v5, v0, v6
122 ; GFX11-NEXT: v_mul_f32_e32 v1, v8, v6
123 ; GFX11-NEXT: s_waitcnt vmcnt(0)
124 ; GFX11-NEXT: v_add_f32_e32 v4, v4, v10
125 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
126 ; GFX11-NEXT: v_dual_mul_f32 v3, v4, v6 :: v_dual_fmaak_f32 v4, s0, v5, 0x3ca3d70a
127 ; GFX11-NEXT: v_fma_f32 v0, v2, s26, -v1
128 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
129 ; GFX11-NEXT: v_fmac_f32_e32 v1, v0, v6
130 ; GFX11-NEXT: v_mul_f32_e32 v0, v2, v6
131 ; GFX11-NEXT: v_mul_f32_e32 v2, v7, v4
132 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
133 ; GFX11-NEXT: v_mul_f32_e32 v1, v3, v1
134 ; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v0
135 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
136 ; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
137 ; GFX11-NEXT: ; return to shader part epilog
138 .entry:
139 %0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
140 %.i2243 = extractelement <3 x float> %0, i32 2
141 %1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 0, i32 0)
142 %2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
143 %3 = bitcast <4 x i32> %2 to <4 x float>
144 %.i2248 = extractelement <4 x float> %3, i32 2
145 %.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
146 %4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
147 %5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
148 %.i2333 = extractelement <3 x float> %5, i32 2
149 %6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
150 %7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
151 %.i1408 = extractelement <2 x float> %7, i32 1
152 %.i0364 = extractelement <2 x float> %7, i32 0
153 %8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
154 %9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 112, i32 0)
155 %10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
156 %11 = bitcast <4 x i32> %10 to <4 x float>
157 %.i2360 = extractelement <4 x float> %11, i32 2
158 %.i2363 = fmul reassoc nnan nsz arcp contract afn float %.i2360, %8
159 %12 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 96, i32 0)
160 %13 = shufflevector <3 x i32> %12, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
161 %14 = bitcast <4 x i32> %13 to <4 x float>
162 %.i2367 = extractelement <4 x float> %14, i32 2
163 %.i2370 = fmul reassoc nnan nsz arcp contract afn float %.i0364, %.i2367
164 %15 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 32, i32 0)
165 %16 = shufflevector <3 x i32> %15, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
166 %17 = bitcast <4 x i32> %16 to <4 x float>
167 %.i2373 = extractelement <4 x float> %17, i32 2
168 %.i2376 = fsub reassoc nnan nsz arcp contract afn float %.i2373, %.i2370
169 %.i2383 = fmul reassoc nnan nsz arcp contract afn float %.i2376, %6
170 %.i2386 = fadd reassoc nnan nsz arcp contract afn float %.i2370, %.i2383
171 %18 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
172 %19 = fmul reassoc nnan nsz arcp contract afn float %18, %.i2363
173 %.i2394 = fsub reassoc nnan nsz arcp contract afn float %.i2386, %19
174 %.i2397 = fmul reassoc nnan nsz arcp contract afn float %.i2363, %18
175 %.i2404 = fmul reassoc nnan nsz arcp contract afn float %.i2394, %4
176 %.i2407 = fadd reassoc nnan nsz arcp contract afn float %.i2397, %.i2404
177 %20 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 92, i32 0)
178 %21 = bitcast i32 %20 to float
179 %22 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 124, i32 0)
180 %23 = bitcast i32 %22 to float
181 %24 = fsub reassoc nnan nsz arcp contract afn float %21, %23
182 %25 = fmul reassoc nnan nsz arcp contract afn float %.i1408, %24
183 %26 = fadd reassoc nnan nsz arcp contract afn float %25, %23
184 %27 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 44, i32 0)
185 %28 = bitcast i32 %27 to float
186 %29 = fsub reassoc nnan nsz arcp contract afn float %28, %26
187 %30 = fmul reassoc nnan nsz arcp contract afn float %6, %29
188 %31 = fadd reassoc nnan nsz arcp contract afn float %26, %30
189 %32 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> undef, i32 192, i32 0)
190 %33 = bitcast i32 %32 to float
191 %34 = fadd reassoc nnan nsz arcp contract afn float %33, -1.000000e+00
192 %35 = fmul reassoc nnan nsz arcp contract afn float %18, %34
193 %36 = fadd reassoc nnan nsz arcp contract afn float %35, 1.000000e+00
194 %37 = fsub reassoc nnan nsz arcp contract afn float %31, %36
195 %38 = fmul reassoc nnan nsz arcp contract afn float %37, %4
196 %39 = fadd reassoc nnan nsz arcp contract afn float %36, %38
197 %40 = fmul reassoc nnan nsz arcp contract afn float %39, 0x3F847AE140000000
198 %41 = fadd reassoc nnan nsz arcp contract afn float %40, 0x3F947AE140000000
199 %.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
200 %42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> undef, i32 0, i32 0)
201 %.i2521 = extractelement <3 x float> %42, i32 2
202 %43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
203 %44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
204 %.i2465 = extractelement <3 x float> %44, i32 2
205 %.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
206 %.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
207 %45 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 64, i32 0)
208 %46 = shufflevector <3 x i32> %45, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
209 %47 = bitcast <4 x i32> %46 to <4 x float>
210 %.i2476 = extractelement <4 x float> %47, i32 2
211 %.i2479 = fmul reassoc nnan nsz arcp contract afn float %.i2476, %18
212 %48 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 80, i32 0)
213 %49 = shufflevector <3 x i32> %48, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
214 %50 = bitcast <4 x i32> %49 to <4 x float>
215 %.i2482 = extractelement <4 x float> %50, i32 2
216 %.i2485 = fsub reassoc nnan nsz arcp contract afn float %.i2482, %.i2479
217 %.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
218 %.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
219 %.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
220 %51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
221 %.i2515 = extractelement <3 x float> %51, i32 2
222 %.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
223 %.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516
224 %.i2525 = fmul reassoc nnan nsz arcp contract afn float %.i2522, %43
225 %52 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> undef, i32 16, i32 0)
226 %53 = shufflevector <3 x i32> %52, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
227 %54 = bitcast <4 x i32> %53 to <4 x float>
228 %.i2530 = extractelement <4 x float> %54, i32 2
229 %.i2531 = fmul reassoc nnan nsz arcp contract afn float %.i2333, %.i2530
230 %.i2536 = fsub reassoc nnan nsz arcp contract afn float %.i2531, %.i2488
231 %.i2539 = fmul reassoc nnan nsz arcp contract afn float %.i2536, %4
232 %.i2542 = fadd reassoc nnan nsz arcp contract afn float %.i2488, %.i2539
233 %.i2545 = fmul reassoc nnan nsz arcp contract afn float %.i2525, %.i2542
234 %.i2548 = fadd reassoc nnan nsz arcp contract afn float %.i2469, %.i2545
235 %.i2551 = call reassoc nnan nsz arcp contract afn float @llvm.maxnum.f32(float %.i2548, float 0.000000e+00)
236 ret float %.i2551
237 }
239 define float @fmac_sequence_simple(float %a, float %b, float %c, float %d, float %e) #0 {
240 ; GFX10-LABEL: fmac_sequence_simple:
241 ; GFX10: ; %bb.0:
242 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
243 ; GFX10-NEXT: v_fma_f32 v2, v2, v3, v4
244 ; GFX10-NEXT: v_fmac_f32_e32 v2, v0, v1
245 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
246 ; GFX10-NEXT: s_setpc_b64 s[30:31]
247 ;
248 ; GFX11-LABEL: fmac_sequence_simple:
249 ; GFX11: ; %bb.0:
250 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
251 ; GFX11-NEXT: v_fma_f32 v2, v2, v3, v4
252 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
253 ; GFX11-NEXT: v_fmac_f32_e32 v2, v0, v1
254 ; GFX11-NEXT: v_mov_b32_e32 v0, v2
255 ; GFX11-NEXT: s_setpc_b64 s[30:31]
256 %t0 = fmul fast float %a, %b
257 %t1 = fmul fast float %c, %d
258 %t2 = fadd fast float %t0, %t1
259 %t5 = fadd fast float %t2, %e
260 ret float %t5
261 }
263 define float @fmac_sequence_innermost_fmul(float %a, float %b, float %c, float %d, float %e, float %f, float %g) #0 {
264 ; GFX10-LABEL: fmac_sequence_innermost_fmul:
265 ; GFX10: ; %bb.0:
266 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
267 ; GFX10-NEXT: v_mad_f32 v2, v2, v3, v6
268 ; GFX10-NEXT: v_fmac_f32_e32 v2, v0, v1
269 ; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v5
270 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
271 ; GFX10-NEXT: s_setpc_b64 s[30:31]
272 ;
273 ; GFX11-LABEL: fmac_sequence_innermost_fmul:
274 ; GFX11: ; %bb.0:
275 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
276 ; GFX11-NEXT: v_fma_f32 v2, v2, v3, v6
277 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
278 ; GFX11-NEXT: v_fmac_f32_e32 v2, v0, v1
279 ; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v5
280 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
281 ; GFX11-NEXT: v_mov_b32_e32 v0, v2
282 ; GFX11-NEXT: s_setpc_b64 s[30:31]
283 %t0 = fmul fast float %a, %b
284 %t1 = fmul fast float %c, %d
285 %t2 = fadd fast float %t0, %t1
286 %t3 = fmul fast float %e, %f
287 %t4 = fadd fast float %t2, %t3
288 %t5 = fadd fast float %t4, %g
289 ret float %t5
290 }
292 define float @fmac_sequence_innermost_fmul_swapped_operands(float %a, float %b, float %c, float %d, float %e, float %f, float %g) #0 {
293 ; GFX10-LABEL: fmac_sequence_innermost_fmul_swapped_operands:
294 ; GFX10: ; %bb.0:
295 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
296 ; GFX10-NEXT: v_mad_f32 v2, v2, v3, v6
297 ; GFX10-NEXT: v_fmac_f32_e32 v2, v0, v1
298 ; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v5
299 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
300 ; GFX10-NEXT: s_setpc_b64 s[30:31]
301 ;
302 ; GFX11-LABEL: fmac_sequence_innermost_fmul_swapped_operands:
303 ; GFX11: ; %bb.0:
304 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
305 ; GFX11-NEXT: v_fma_f32 v2, v2, v3, v6
306 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
307 ; GFX11-NEXT: v_fmac_f32_e32 v2, v0, v1
308 ; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v5
309 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
310 ; GFX11-NEXT: v_mov_b32_e32 v0, v2
311 ; GFX11-NEXT: s_setpc_b64 s[30:31]
312 %t0 = fmul fast float %a, %b
313 %t1 = fmul fast float %c, %d
314 %t2 = fadd fast float %t0, %t1
315 %t3 = fmul fast float %e, %f
316 %t4 = fadd fast float %t2, %t3
317 %t5 = fadd fast float %g, %t4
318 ret float %t5
319 }
321 define amdgpu_ps float @fmac_sequence_innermost_fmul_sgpr(float inreg %a, float inreg %b, float inreg %c, float inreg %d, float inreg %e, float inreg %f, float %g) #0 {
322 ; GFX10-LABEL: fmac_sequence_innermost_fmul_sgpr:
323 ; GFX10: ; %bb.0:
324 ; GFX10-NEXT: v_mac_f32_e64 v0, s2, s3
325 ; GFX10-NEXT: v_fmac_f32_e64 v0, s0, s1
326 ; GFX10-NEXT: v_fmac_f32_e64 v0, s4, s5
327 ; GFX10-NEXT: ; return to shader part epilog
328 ;
329 ; GFX11-LABEL: fmac_sequence_innermost_fmul_sgpr:
330 ; GFX11: ; %bb.0:
331 ; GFX11-NEXT: v_fmac_f32_e64 v0, s2, s3
332 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
333 ; GFX11-NEXT: v_fmac_f32_e64 v0, s0, s1
334 ; GFX11-NEXT: v_fmac_f32_e64 v0, s4, s5
335 ; GFX11-NEXT: ; return to shader part epilog
336 %t0 = fmul fast float %a, %b
337 %t1 = fmul fast float %c, %d
338 %t2 = fadd fast float %t0, %t1
339 %t3 = fmul fast float %e, %f
340 %t4 = fadd fast float %t2, %t3
341 %t5 = fadd fast float %t4, %g
342 ret float %t5
343 }
345 define amdgpu_ps float @fmac_sequence_innermost_fmul_multiple_use(float inreg %a, float inreg %b, float inreg %c, float inreg %d, float inreg %e, float inreg %f, float %g) #0 {
346 ; GFX10-LABEL: fmac_sequence_innermost_fmul_multiple_use:
347 ; GFX10: ; %bb.0:
348 ; GFX10-NEXT: v_mul_f32_e64 v1, s2, s3
349 ; GFX10-NEXT: v_fmac_f32_e64 v1, s0, s1
350 ; GFX10-NEXT: v_fma_f32 v2, s5, s4, v1
351 ; GFX10-NEXT: v_fmac_f32_e32 v1, s5, v2
352 ; GFX10-NEXT: v_add_f32_e32 v0, v1, v0
353 ; GFX10-NEXT: ; return to shader part epilog
354 ;
355 ; GFX11-LABEL: fmac_sequence_innermost_fmul_multiple_use:
356 ; GFX11: ; %bb.0:
357 ; GFX11-NEXT: v_mul_f32_e64 v1, s2, s3
358 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
359 ; GFX11-NEXT: v_fmac_f32_e64 v1, s0, s1
360 ; GFX11-NEXT: v_fma_f32 v2, s5, s4, v1
361 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
362 ; GFX11-NEXT: v_fmac_f32_e32 v1, s5, v2
363 ; GFX11-NEXT: v_add_f32_e32 v0, v1, v0
364 ; GFX11-NEXT: ; return to shader part epilog
365 %t0 = fmul fast float %a, %b
366 %t1 = fmul fast float %c, %d
367 %t2 = fadd fast float %t0, %t1
368 %t3 = fmul fast float %e, %f
369 %t4 = fadd fast float %t2, %t3
370 %t5 = fmul fast float %f, %t4
371 %t6 = fadd fast float %t5, %t2
372 %t7 = fadd fast float %t6, %g
373 ret float %t7
374 }
376 ; "fmul %m, 2.0" could select to an FMA instruction, but it is no better than
377 ; selecting it as a multiply. In some cases the multiply is better because
378 ; SIFoldOperands can fold it into a previous instruction as an output modifier.
379 define amdgpu_ps float @fma_vs_output_modifier(float %x, i32 %n) #0 {
380 ; GFX10-LABEL: fma_vs_output_modifier:
381 ; GFX10: ; %bb.0:
382 ; GFX10-NEXT: v_cvt_f32_i32_e64 v1, v1 mul:2
383 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v0
384 ; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
385 ; GFX10-NEXT: ; return to shader part epilog
386 ;
387 ; GFX11-LABEL: fma_vs_output_modifier:
388 ; GFX11: ; %bb.0:
389 ; GFX11-NEXT: v_cvt_f32_i32_e64 v1, v1 mul:2
390 ; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
391 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
392 ; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
393 ; GFX11-NEXT: ; return to shader part epilog
394 %s = sitofp i32 %n to float
395 %m = fmul contract float %x, %x
396 %a = fmul contract float %m, 2.0
397 %r = fmul reassoc nsz float %a, %s
398 ret float %r
399 }
401 define amdgpu_ps float @fma_vs_output_modifier_2(float %x) #0 {
402 ; GCN-LABEL: fma_vs_output_modifier_2:
403 ; GCN: ; %bb.0:
404 ; GCN-NEXT: v_mul_f32_e64 v0, v0, v0 mul:2
405 ; GCN-NEXT: ; return to shader part epilog
406 %m = fmul contract float %x, %x
407 %a = fadd nsz contract float %m, %m
408 ret float %a
409 }
411 ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
412 declare float @llvm.maxnum.f32(float, float) #1
414 ; Function Attrs: nounwind readnone speculatable willreturn
415 declare float @llvm.amdgcn.fmed3.f32(float, float, float) #2
417 ; Function Attrs: nounwind readonly willreturn
418 declare <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
420 ; Function Attrs: nounwind readonly willreturn
421 declare float @llvm.amdgcn.image.sample.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
423 ; Function Attrs: nounwind readonly willreturn
424 declare <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
426 ; Function Attrs: nounwind readonly willreturn
427 declare <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #3
429 ; Function Attrs: nounwind readnone willreturn
430 declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #3
432 ; Function Attrs: nounwind readnone willreturn
433 declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32 immarg) #3
435 attributes #0 = { "denormal-fp-math-f32"="preserve-sign" }
436 attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
437 attributes #2 = { nounwind readnone speculatable willreturn }
438 attributes #3 = { nounwind readonly willreturn }