| blob | 44d1cfb96146eb79191f48869a6593e8383ac605 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,SDAG-GFX10 %s
5 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
6 ; RUN: FileCheck --check-prefix=ERR %s < %t
7 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX10,GISEL-GFX10 %s
8 ; RUN: FileCheck --check-prefix=ERR %s < %t
10 ; Note: GlobalISel abort is disabled so we don't crash on i1 inputs.
11 ; They are allowed in DAGISel but we (intentionally) don't support them
12 ; in GlobalISel.
14 ; ERR: warning: Instruction selection used fallback path for v_icmp_i1_ne0
16 declare i32 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
17 declare i32 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
18 declare i32 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
19 declare i32 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
21 define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
22 ; SDAG-GFX11-LABEL: v_icmp_i32_eq:
23 ; SDAG-GFX11: ; %bb.0:
24 ; SDAG-GFX11-NEXT: s_clause 0x1
25 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
26 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
27 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
28 ; SDAG-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
29 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
30 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
31 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
32 ; SDAG-GFX11-NEXT: s_nop 0
33 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
34 ; SDAG-GFX11-NEXT: s_endpgm
35 ;
36 ; SDAG-GFX10-LABEL: v_icmp_i32_eq:
37 ; SDAG-GFX10: ; %bb.0:
38 ; SDAG-GFX10-NEXT: s_clause 0x1
39 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
40 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
41 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
42 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
43 ; SDAG-GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0x64, s4
44 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
45 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
46 ; SDAG-GFX10-NEXT: s_endpgm
47 ;
48 ; GISEL-GFX11-LABEL: v_icmp_i32_eq:
49 ; GISEL-GFX11: ; %bb.0:
50 ; GISEL-GFX11-NEXT: s_clause 0x1
51 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
52 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
53 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
54 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
55 ; GISEL-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
56 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
57 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
58 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
59 ; GISEL-GFX11-NEXT: s_nop 0
60 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
61 ; GISEL-GFX11-NEXT: s_endpgm
62 ;
63 ; GISEL-GFX10-LABEL: v_icmp_i32_eq:
64 ; GISEL-GFX10: ; %bb.0:
65 ; GISEL-GFX10-NEXT: s_clause 0x1
66 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
67 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
68 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
69 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
70 ; GISEL-GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0x64, s4
71 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
72 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
73 ; GISEL-GFX10-NEXT: s_endpgm
74 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 32)
75 store i32 %result, ptr addrspace(1) %out
76 ret void
77 }
79 define amdgpu_kernel void @v_icmp_i32(ptr addrspace(1) %out, i32 %src) {
80 ; SDAG-GFX11-LABEL: v_icmp_i32:
81 ; SDAG-GFX11: ; %bb.0:
82 ; SDAG-GFX11-NEXT: s_endpgm
83 ;
84 ; SDAG-GFX10-LABEL: v_icmp_i32:
85 ; SDAG-GFX10: ; %bb.0:
86 ; SDAG-GFX10-NEXT: s_endpgm
87 ;
88 ; GISEL-GFX11-LABEL: v_icmp_i32:
89 ; GISEL-GFX11: ; %bb.0:
90 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
91 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
92 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
93 ; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
94 ; GISEL-GFX11-NEXT: s_nop 0
95 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
96 ; GISEL-GFX11-NEXT: s_endpgm
97 ;
98 ; GISEL-GFX10-LABEL: v_icmp_i32:
99 ; GISEL-GFX10: ; %bb.0:
100 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
101 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
102 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
103 ; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
104 ; GISEL-GFX10-NEXT: s_endpgm
105 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 30)
106 store i32 %result, ptr addrspace(1) %out
107 ret void
108 }
110 define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
111 ; SDAG-GFX11-LABEL: v_icmp_i32_ne:
112 ; SDAG-GFX11: ; %bb.0:
113 ; SDAG-GFX11-NEXT: s_clause 0x1
114 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
115 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
116 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
117 ; SDAG-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
118 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
119 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
120 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
121 ; SDAG-GFX11-NEXT: s_nop 0
122 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
123 ; SDAG-GFX11-NEXT: s_endpgm
124 ;
125 ; SDAG-GFX10-LABEL: v_icmp_i32_ne:
126 ; SDAG-GFX10: ; %bb.0:
127 ; SDAG-GFX10-NEXT: s_clause 0x1
128 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
129 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
130 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
131 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
132 ; SDAG-GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0x64, s4
133 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
134 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
135 ; SDAG-GFX10-NEXT: s_endpgm
136 ;
137 ; GISEL-GFX11-LABEL: v_icmp_i32_ne:
138 ; GISEL-GFX11: ; %bb.0:
139 ; GISEL-GFX11-NEXT: s_clause 0x1
140 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
141 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
142 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
143 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
144 ; GISEL-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
145 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
146 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
147 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
148 ; GISEL-GFX11-NEXT: s_nop 0
149 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
150 ; GISEL-GFX11-NEXT: s_endpgm
151 ;
152 ; GISEL-GFX10-LABEL: v_icmp_i32_ne:
153 ; GISEL-GFX10: ; %bb.0:
154 ; GISEL-GFX10-NEXT: s_clause 0x1
155 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
156 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
157 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
158 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
159 ; GISEL-GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0x64, s4
160 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
161 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
162 ; GISEL-GFX10-NEXT: s_endpgm
163 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 33)
164 store i32 %result, ptr addrspace(1) %out
165 ret void
166 }
168 define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
169 ; SDAG-GFX11-LABEL: v_icmp_i32_ugt:
170 ; SDAG-GFX11: ; %bb.0:
171 ; SDAG-GFX11-NEXT: s_clause 0x1
172 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
173 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
174 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
175 ; SDAG-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
176 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
177 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
178 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
179 ; SDAG-GFX11-NEXT: s_nop 0
180 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
181 ; SDAG-GFX11-NEXT: s_endpgm
182 ;
183 ; SDAG-GFX10-LABEL: v_icmp_i32_ugt:
184 ; SDAG-GFX10: ; %bb.0:
185 ; SDAG-GFX10-NEXT: s_clause 0x1
186 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
187 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
188 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
189 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
190 ; SDAG-GFX10-NEXT: v_cmp_lt_u32_e64 s0, 0x64, s4
191 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
192 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
193 ; SDAG-GFX10-NEXT: s_endpgm
194 ;
195 ; GISEL-GFX11-LABEL: v_icmp_i32_ugt:
196 ; GISEL-GFX11: ; %bb.0:
197 ; GISEL-GFX11-NEXT: s_clause 0x1
198 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
199 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
200 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
201 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
202 ; GISEL-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
203 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
204 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
205 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
206 ; GISEL-GFX11-NEXT: s_nop 0
207 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
208 ; GISEL-GFX11-NEXT: s_endpgm
209 ;
210 ; GISEL-GFX10-LABEL: v_icmp_i32_ugt:
211 ; GISEL-GFX10: ; %bb.0:
212 ; GISEL-GFX10-NEXT: s_clause 0x1
213 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
214 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
215 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
216 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
217 ; GISEL-GFX10-NEXT: v_cmp_lt_u32_e64 s0, 0x64, s4
218 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
219 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
220 ; GISEL-GFX10-NEXT: s_endpgm
221 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 34)
222 store i32 %result, ptr addrspace(1) %out
223 ret void
224 }
226 define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
227 ; SDAG-GFX11-LABEL: v_icmp_i32_uge:
228 ; SDAG-GFX11: ; %bb.0:
229 ; SDAG-GFX11-NEXT: s_clause 0x1
230 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
231 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
232 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
233 ; SDAG-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
234 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
235 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
236 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
237 ; SDAG-GFX11-NEXT: s_nop 0
238 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
239 ; SDAG-GFX11-NEXT: s_endpgm
240 ;
241 ; SDAG-GFX10-LABEL: v_icmp_i32_uge:
242 ; SDAG-GFX10: ; %bb.0:
243 ; SDAG-GFX10-NEXT: s_clause 0x1
244 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
245 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
246 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
247 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
248 ; SDAG-GFX10-NEXT: v_cmp_le_u32_e64 s0, 0x64, s4
249 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
250 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
251 ; SDAG-GFX10-NEXT: s_endpgm
252 ;
253 ; GISEL-GFX11-LABEL: v_icmp_i32_uge:
254 ; GISEL-GFX11: ; %bb.0:
255 ; GISEL-GFX11-NEXT: s_clause 0x1
256 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
257 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
258 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
259 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
260 ; GISEL-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
261 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
262 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
263 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
264 ; GISEL-GFX11-NEXT: s_nop 0
265 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
266 ; GISEL-GFX11-NEXT: s_endpgm
267 ;
268 ; GISEL-GFX10-LABEL: v_icmp_i32_uge:
269 ; GISEL-GFX10: ; %bb.0:
270 ; GISEL-GFX10-NEXT: s_clause 0x1
271 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
272 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
273 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
274 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
275 ; GISEL-GFX10-NEXT: v_cmp_le_u32_e64 s0, 0x64, s4
276 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
277 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
278 ; GISEL-GFX10-NEXT: s_endpgm
279 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 35)
280 store i32 %result, ptr addrspace(1) %out
281 ret void
282 }
284 define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
285 ; SDAG-GFX11-LABEL: v_icmp_i32_ult:
286 ; SDAG-GFX11: ; %bb.0:
287 ; SDAG-GFX11-NEXT: s_clause 0x1
288 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
289 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
290 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
291 ; SDAG-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
292 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
293 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
294 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
295 ; SDAG-GFX11-NEXT: s_nop 0
296 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
297 ; SDAG-GFX11-NEXT: s_endpgm
298 ;
299 ; SDAG-GFX10-LABEL: v_icmp_i32_ult:
300 ; SDAG-GFX10: ; %bb.0:
301 ; SDAG-GFX10-NEXT: s_clause 0x1
302 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
303 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
304 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
305 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
306 ; SDAG-GFX10-NEXT: v_cmp_gt_u32_e64 s0, 0x64, s4
307 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
308 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
309 ; SDAG-GFX10-NEXT: s_endpgm
310 ;
311 ; GISEL-GFX11-LABEL: v_icmp_i32_ult:
312 ; GISEL-GFX11: ; %bb.0:
313 ; GISEL-GFX11-NEXT: s_clause 0x1
314 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
315 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
316 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
317 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
318 ; GISEL-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
319 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
320 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
321 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
322 ; GISEL-GFX11-NEXT: s_nop 0
323 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
324 ; GISEL-GFX11-NEXT: s_endpgm
325 ;
326 ; GISEL-GFX10-LABEL: v_icmp_i32_ult:
327 ; GISEL-GFX10: ; %bb.0:
328 ; GISEL-GFX10-NEXT: s_clause 0x1
329 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
330 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
331 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
332 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
333 ; GISEL-GFX10-NEXT: v_cmp_gt_u32_e64 s0, 0x64, s4
334 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
335 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
336 ; GISEL-GFX10-NEXT: s_endpgm
337 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 36)
338 store i32 %result, ptr addrspace(1) %out
339 ret void
340 }
342 define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
343 ; SDAG-GFX11-LABEL: v_icmp_i32_ule:
344 ; SDAG-GFX11: ; %bb.0:
345 ; SDAG-GFX11-NEXT: s_clause 0x1
346 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
347 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
348 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
349 ; SDAG-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
350 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
351 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
352 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
353 ; SDAG-GFX11-NEXT: s_nop 0
354 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
355 ; SDAG-GFX11-NEXT: s_endpgm
356 ;
357 ; SDAG-GFX10-LABEL: v_icmp_i32_ule:
358 ; SDAG-GFX10: ; %bb.0:
359 ; SDAG-GFX10-NEXT: s_clause 0x1
360 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
361 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
362 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
363 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
364 ; SDAG-GFX10-NEXT: v_cmp_ge_u32_e64 s0, 0x64, s4
365 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
366 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
367 ; SDAG-GFX10-NEXT: s_endpgm
368 ;
369 ; GISEL-GFX11-LABEL: v_icmp_i32_ule:
370 ; GISEL-GFX11: ; %bb.0:
371 ; GISEL-GFX11-NEXT: s_clause 0x1
372 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
373 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
374 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
375 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
376 ; GISEL-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
377 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
378 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
379 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
380 ; GISEL-GFX11-NEXT: s_nop 0
381 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
382 ; GISEL-GFX11-NEXT: s_endpgm
383 ;
384 ; GISEL-GFX10-LABEL: v_icmp_i32_ule:
385 ; GISEL-GFX10: ; %bb.0:
386 ; GISEL-GFX10-NEXT: s_clause 0x1
387 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
388 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
389 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
390 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
391 ; GISEL-GFX10-NEXT: v_cmp_ge_u32_e64 s0, 0x64, s4
392 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
393 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
394 ; GISEL-GFX10-NEXT: s_endpgm
395 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 37)
396 store i32 %result, ptr addrspace(1) %out
397 ret void
398 }
400 define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
401 ; SDAG-GFX11-LABEL: v_icmp_i32_sgt:
402 ; SDAG-GFX11: ; %bb.0:
403 ; SDAG-GFX11-NEXT: s_clause 0x1
404 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
405 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
406 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
407 ; SDAG-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
408 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
409 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
410 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
411 ; SDAG-GFX11-NEXT: s_nop 0
412 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
413 ; SDAG-GFX11-NEXT: s_endpgm
414 ;
415 ; SDAG-GFX10-LABEL: v_icmp_i32_sgt:
416 ; SDAG-GFX10: ; %bb.0:
417 ; SDAG-GFX10-NEXT: s_clause 0x1
418 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
419 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
420 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
421 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
422 ; SDAG-GFX10-NEXT: v_cmp_lt_i32_e64 s0, 0x64, s4
423 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
424 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
425 ; SDAG-GFX10-NEXT: s_endpgm
426 ;
427 ; GISEL-GFX11-LABEL: v_icmp_i32_sgt:
428 ; GISEL-GFX11: ; %bb.0:
429 ; GISEL-GFX11-NEXT: s_clause 0x1
430 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
431 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
432 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
433 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
434 ; GISEL-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
435 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
436 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
437 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
438 ; GISEL-GFX11-NEXT: s_nop 0
439 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
440 ; GISEL-GFX11-NEXT: s_endpgm
441 ;
442 ; GISEL-GFX10-LABEL: v_icmp_i32_sgt:
443 ; GISEL-GFX10: ; %bb.0:
444 ; GISEL-GFX10-NEXT: s_clause 0x1
445 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
446 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
447 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
448 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
449 ; GISEL-GFX10-NEXT: v_cmp_lt_i32_e64 s0, 0x64, s4
450 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
451 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
452 ; GISEL-GFX10-NEXT: s_endpgm
453 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 38)
454 store i32 %result, ptr addrspace(1) %out
455 ret void
456 }
458 define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
459 ; SDAG-GFX11-LABEL: v_icmp_i32_sge:
460 ; SDAG-GFX11: ; %bb.0:
461 ; SDAG-GFX11-NEXT: s_clause 0x1
462 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
463 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
464 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
465 ; SDAG-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
466 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
467 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
468 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
469 ; SDAG-GFX11-NEXT: s_nop 0
470 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
471 ; SDAG-GFX11-NEXT: s_endpgm
472 ;
473 ; SDAG-GFX10-LABEL: v_icmp_i32_sge:
474 ; SDAG-GFX10: ; %bb.0:
475 ; SDAG-GFX10-NEXT: s_clause 0x1
476 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
477 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
478 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
479 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
480 ; SDAG-GFX10-NEXT: v_cmp_le_i32_e64 s0, 0x64, s4
481 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
482 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
483 ; SDAG-GFX10-NEXT: s_endpgm
484 ;
485 ; GISEL-GFX11-LABEL: v_icmp_i32_sge:
486 ; GISEL-GFX11: ; %bb.0:
487 ; GISEL-GFX11-NEXT: s_clause 0x1
488 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
489 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
490 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
491 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
492 ; GISEL-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
493 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
494 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
495 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
496 ; GISEL-GFX11-NEXT: s_nop 0
497 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
498 ; GISEL-GFX11-NEXT: s_endpgm
499 ;
500 ; GISEL-GFX10-LABEL: v_icmp_i32_sge:
501 ; GISEL-GFX10: ; %bb.0:
502 ; GISEL-GFX10-NEXT: s_clause 0x1
503 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
504 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
505 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
506 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
507 ; GISEL-GFX10-NEXT: v_cmp_le_i32_e64 s0, 0x64, s4
508 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
509 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
510 ; GISEL-GFX10-NEXT: s_endpgm
511 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 39)
512 store i32 %result, ptr addrspace(1) %out
513 ret void
514 }
516 define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
517 ; SDAG-GFX11-LABEL: v_icmp_i32_slt:
518 ; SDAG-GFX11: ; %bb.0:
519 ; SDAG-GFX11-NEXT: s_clause 0x1
520 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
521 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
522 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
523 ; SDAG-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
524 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
525 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
526 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
527 ; SDAG-GFX11-NEXT: s_nop 0
528 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
529 ; SDAG-GFX11-NEXT: s_endpgm
530 ;
531 ; SDAG-GFX10-LABEL: v_icmp_i32_slt:
532 ; SDAG-GFX10: ; %bb.0:
533 ; SDAG-GFX10-NEXT: s_clause 0x1
534 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
535 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
536 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
537 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
538 ; SDAG-GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0x64, s4
539 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
540 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
541 ; SDAG-GFX10-NEXT: s_endpgm
542 ;
543 ; GISEL-GFX11-LABEL: v_icmp_i32_slt:
544 ; GISEL-GFX11: ; %bb.0:
545 ; GISEL-GFX11-NEXT: s_clause 0x1
546 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
547 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
548 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
549 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
550 ; GISEL-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
551 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
552 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
553 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
554 ; GISEL-GFX11-NEXT: s_nop 0
555 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
556 ; GISEL-GFX11-NEXT: s_endpgm
557 ;
558 ; GISEL-GFX10-LABEL: v_icmp_i32_slt:
559 ; GISEL-GFX10: ; %bb.0:
560 ; GISEL-GFX10-NEXT: s_clause 0x1
561 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
562 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
563 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
564 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
565 ; GISEL-GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0x64, s4
566 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
567 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
568 ; GISEL-GFX10-NEXT: s_endpgm
569 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 40)
570 store i32 %result, ptr addrspace(1) %out
571 ret void
572 }
574 define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
575 ; SDAG-GFX11-LABEL: v_icmp_i32_sle:
576 ; SDAG-GFX11: ; %bb.0:
577 ; SDAG-GFX11-NEXT: s_clause 0x1
578 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
579 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
580 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
581 ; SDAG-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
582 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
583 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
584 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
585 ; SDAG-GFX11-NEXT: s_nop 0
586 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
587 ; SDAG-GFX11-NEXT: s_endpgm
588 ;
589 ; SDAG-GFX10-LABEL: v_icmp_i32_sle:
590 ; SDAG-GFX10: ; %bb.0:
591 ; SDAG-GFX10-NEXT: s_clause 0x1
592 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
593 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
594 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
595 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
596 ; SDAG-GFX10-NEXT: v_cmp_ge_i32_e64 s0, 0x64, s4
597 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
598 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
599 ; SDAG-GFX10-NEXT: s_endpgm
600 ;
601 ; GISEL-GFX11-LABEL: v_icmp_i32_sle:
602 ; GISEL-GFX11: ; %bb.0:
603 ; GISEL-GFX11-NEXT: s_clause 0x1
604 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
605 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
606 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
607 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
608 ; GISEL-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
609 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
610 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
611 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
612 ; GISEL-GFX11-NEXT: s_nop 0
613 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
614 ; GISEL-GFX11-NEXT: s_endpgm
615 ;
616 ; GISEL-GFX10-LABEL: v_icmp_i32_sle:
617 ; GISEL-GFX10: ; %bb.0:
618 ; GISEL-GFX10-NEXT: s_clause 0x1
619 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
620 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
621 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
622 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
623 ; GISEL-GFX10-NEXT: v_cmp_ge_i32_e64 s0, 0x64, s4
624 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
625 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
626 ; GISEL-GFX10-NEXT: s_endpgm
627 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 41)
628 store i32 %result, ptr addrspace(1) %out
629 ret void
630 }
632 define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
633 ; SDAG-GFX11-LABEL: v_icmp_i64_eq:
634 ; SDAG-GFX11: ; %bb.0:
635 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
636 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
637 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
638 ; SDAG-GFX11-NEXT: v_cmp_eq_u64_e64 s2, s[2:3], s[4:5]
639 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
640 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
641 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
642 ; SDAG-GFX11-NEXT: s_nop 0
643 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
644 ; SDAG-GFX11-NEXT: s_endpgm
645 ;
646 ; SDAG-GFX10-LABEL: v_icmp_i64_eq:
647 ; SDAG-GFX10: ; %bb.0:
648 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
649 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
650 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
651 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
652 ; SDAG-GFX10-NEXT: v_cmp_eq_u64_e64 s2, s[2:3], s[4:5]
653 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
654 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
655 ; SDAG-GFX10-NEXT: s_endpgm
656 ;
657 ; GISEL-GFX11-LABEL: v_icmp_i64_eq:
658 ; GISEL-GFX11: ; %bb.0:
659 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
660 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
661 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
662 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
663 ; GISEL-GFX11-NEXT: v_cmp_eq_u64_e64 s2, s[2:3], s[4:5]
664 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
665 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
666 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
667 ; GISEL-GFX11-NEXT: s_nop 0
668 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
669 ; GISEL-GFX11-NEXT: s_endpgm
670 ;
671 ; GISEL-GFX10-LABEL: v_icmp_i64_eq:
672 ; GISEL-GFX10: ; %bb.0:
673 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
674 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
675 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
676 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
677 ; GISEL-GFX10-NEXT: v_cmp_eq_u64_e64 s2, s[2:3], s[4:5]
678 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
679 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
680 ; GISEL-GFX10-NEXT: s_endpgm
681 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 32)
682 store i32 %result, ptr addrspace(1) %out
683 ret void
684 }
686 define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
687 ; SDAG-GFX11-LABEL: v_icmp_i64_ne:
688 ; SDAG-GFX11: ; %bb.0:
689 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
690 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
691 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
692 ; SDAG-GFX11-NEXT: v_cmp_ne_u64_e64 s2, s[2:3], s[4:5]
693 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
694 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
695 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
696 ; SDAG-GFX11-NEXT: s_nop 0
697 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
698 ; SDAG-GFX11-NEXT: s_endpgm
699 ;
700 ; SDAG-GFX10-LABEL: v_icmp_i64_ne:
701 ; SDAG-GFX10: ; %bb.0:
702 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
703 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
704 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
705 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
706 ; SDAG-GFX10-NEXT: v_cmp_ne_u64_e64 s2, s[2:3], s[4:5]
707 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
708 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
709 ; SDAG-GFX10-NEXT: s_endpgm
710 ;
711 ; GISEL-GFX11-LABEL: v_icmp_i64_ne:
712 ; GISEL-GFX11: ; %bb.0:
713 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
714 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
715 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
716 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
717 ; GISEL-GFX11-NEXT: v_cmp_ne_u64_e64 s2, s[2:3], s[4:5]
718 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
719 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
720 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
721 ; GISEL-GFX11-NEXT: s_nop 0
722 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
723 ; GISEL-GFX11-NEXT: s_endpgm
724 ;
725 ; GISEL-GFX10-LABEL: v_icmp_i64_ne:
726 ; GISEL-GFX10: ; %bb.0:
727 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
728 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
729 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
730 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
731 ; GISEL-GFX10-NEXT: v_cmp_ne_u64_e64 s2, s[2:3], s[4:5]
732 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
733 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
734 ; GISEL-GFX10-NEXT: s_endpgm
735 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 33)
736 store i32 %result, ptr addrspace(1) %out
737 ret void
738 }
740 define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
741 ; SDAG-GFX11-LABEL: v_icmp_u64_ugt:
742 ; SDAG-GFX11: ; %bb.0:
743 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
744 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
745 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
746 ; SDAG-GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[4:5]
747 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
748 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
749 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
750 ; SDAG-GFX11-NEXT: s_nop 0
751 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
752 ; SDAG-GFX11-NEXT: s_endpgm
753 ;
754 ; SDAG-GFX10-LABEL: v_icmp_u64_ugt:
755 ; SDAG-GFX10: ; %bb.0:
756 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
757 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
758 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
759 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
760 ; SDAG-GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[4:5]
761 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
762 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
763 ; SDAG-GFX10-NEXT: s_endpgm
764 ;
765 ; GISEL-GFX11-LABEL: v_icmp_u64_ugt:
766 ; GISEL-GFX11: ; %bb.0:
767 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
768 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
769 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
770 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
771 ; GISEL-GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[4:5]
772 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
773 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
774 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
775 ; GISEL-GFX11-NEXT: s_nop 0
776 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
777 ; GISEL-GFX11-NEXT: s_endpgm
778 ;
779 ; GISEL-GFX10-LABEL: v_icmp_u64_ugt:
780 ; GISEL-GFX10: ; %bb.0:
781 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
782 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
783 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
784 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
785 ; GISEL-GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[2:3], s[4:5]
786 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
787 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
788 ; GISEL-GFX10-NEXT: s_endpgm
789 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 34)
790 store i32 %result, ptr addrspace(1) %out
791 ret void
792 }
794 define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
795 ; SDAG-GFX11-LABEL: v_icmp_u64_uge:
796 ; SDAG-GFX11: ; %bb.0:
797 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
798 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
799 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
800 ; SDAG-GFX11-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[4:5]
801 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
802 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
803 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
804 ; SDAG-GFX11-NEXT: s_nop 0
805 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
806 ; SDAG-GFX11-NEXT: s_endpgm
807 ;
808 ; SDAG-GFX10-LABEL: v_icmp_u64_uge:
809 ; SDAG-GFX10: ; %bb.0:
810 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
811 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
812 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
813 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
814 ; SDAG-GFX10-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[4:5]
815 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
816 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
817 ; SDAG-GFX10-NEXT: s_endpgm
818 ;
819 ; GISEL-GFX11-LABEL: v_icmp_u64_uge:
820 ; GISEL-GFX11: ; %bb.0:
821 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
822 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
823 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
824 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
825 ; GISEL-GFX11-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[4:5]
826 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
827 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
828 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
829 ; GISEL-GFX11-NEXT: s_nop 0
830 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
831 ; GISEL-GFX11-NEXT: s_endpgm
832 ;
833 ; GISEL-GFX10-LABEL: v_icmp_u64_uge:
834 ; GISEL-GFX10: ; %bb.0:
835 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
836 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
837 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
838 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
839 ; GISEL-GFX10-NEXT: v_cmp_ge_u64_e64 s2, s[2:3], s[4:5]
840 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
841 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
842 ; GISEL-GFX10-NEXT: s_endpgm
843 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 35)
844 store i32 %result, ptr addrspace(1) %out
845 ret void
846 }
848 define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
849 ; SDAG-GFX11-LABEL: v_icmp_u64_ult:
850 ; SDAG-GFX11: ; %bb.0:
851 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
852 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
853 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
854 ; SDAG-GFX11-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[4:5]
855 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
856 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
857 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
858 ; SDAG-GFX11-NEXT: s_nop 0
859 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
860 ; SDAG-GFX11-NEXT: s_endpgm
861 ;
862 ; SDAG-GFX10-LABEL: v_icmp_u64_ult:
863 ; SDAG-GFX10: ; %bb.0:
864 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
865 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
866 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
867 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
868 ; SDAG-GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[4:5]
869 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
870 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
871 ; SDAG-GFX10-NEXT: s_endpgm
872 ;
873 ; GISEL-GFX11-LABEL: v_icmp_u64_ult:
874 ; GISEL-GFX11: ; %bb.0:
875 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
876 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
877 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
878 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
879 ; GISEL-GFX11-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[4:5]
880 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
881 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
882 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
883 ; GISEL-GFX11-NEXT: s_nop 0
884 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
885 ; GISEL-GFX11-NEXT: s_endpgm
886 ;
887 ; GISEL-GFX10-LABEL: v_icmp_u64_ult:
888 ; GISEL-GFX10: ; %bb.0:
889 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
890 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
891 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
892 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
893 ; GISEL-GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[4:5]
894 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
895 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
896 ; GISEL-GFX10-NEXT: s_endpgm
897 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 36)
898 store i32 %result, ptr addrspace(1) %out
899 ret void
900 }
902 define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
903 ; SDAG-GFX11-LABEL: v_icmp_u64_ule:
904 ; SDAG-GFX11: ; %bb.0:
905 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
906 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
907 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
908 ; SDAG-GFX11-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[4:5]
909 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
910 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
911 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
912 ; SDAG-GFX11-NEXT: s_nop 0
913 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
914 ; SDAG-GFX11-NEXT: s_endpgm
915 ;
916 ; SDAG-GFX10-LABEL: v_icmp_u64_ule:
917 ; SDAG-GFX10: ; %bb.0:
918 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
919 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
920 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
921 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
922 ; SDAG-GFX10-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[4:5]
923 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
924 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
925 ; SDAG-GFX10-NEXT: s_endpgm
926 ;
927 ; GISEL-GFX11-LABEL: v_icmp_u64_ule:
928 ; GISEL-GFX11: ; %bb.0:
929 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
930 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
931 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
932 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
933 ; GISEL-GFX11-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[4:5]
934 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
935 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
936 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
937 ; GISEL-GFX11-NEXT: s_nop 0
938 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
939 ; GISEL-GFX11-NEXT: s_endpgm
940 ;
941 ; GISEL-GFX10-LABEL: v_icmp_u64_ule:
942 ; GISEL-GFX10: ; %bb.0:
943 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
944 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
945 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
946 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
947 ; GISEL-GFX10-NEXT: v_cmp_le_u64_e64 s2, s[2:3], s[4:5]
948 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
949 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
950 ; GISEL-GFX10-NEXT: s_endpgm
951 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 37)
952 store i32 %result, ptr addrspace(1) %out
953 ret void
954 }
956 define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
957 ; SDAG-GFX11-LABEL: v_icmp_i64_sgt:
958 ; SDAG-GFX11: ; %bb.0:
959 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
960 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
961 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
962 ; SDAG-GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[4:5]
963 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
964 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
965 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
966 ; SDAG-GFX11-NEXT: s_nop 0
967 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
968 ; SDAG-GFX11-NEXT: s_endpgm
969 ;
970 ; SDAG-GFX10-LABEL: v_icmp_i64_sgt:
971 ; SDAG-GFX10: ; %bb.0:
972 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
973 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
974 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
975 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
976 ; SDAG-GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[4:5]
977 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
978 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
979 ; SDAG-GFX10-NEXT: s_endpgm
980 ;
981 ; GISEL-GFX11-LABEL: v_icmp_i64_sgt:
982 ; GISEL-GFX11: ; %bb.0:
983 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
984 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
985 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
986 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
987 ; GISEL-GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[4:5]
988 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
989 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
990 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
991 ; GISEL-GFX11-NEXT: s_nop 0
992 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
993 ; GISEL-GFX11-NEXT: s_endpgm
994 ;
995 ; GISEL-GFX10-LABEL: v_icmp_i64_sgt:
996 ; GISEL-GFX10: ; %bb.0:
997 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
998 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
999 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1000 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1001 ; GISEL-GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], s[4:5]
1002 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1003 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1004 ; GISEL-GFX10-NEXT: s_endpgm
1005 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 38)
1006 store i32 %result, ptr addrspace(1) %out
1007 ret void
1008 }
1010 define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
1011 ; SDAG-GFX11-LABEL: v_icmp_i64_sge:
1012 ; SDAG-GFX11: ; %bb.0:
1013 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1014 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1015 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1016 ; SDAG-GFX11-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[4:5]
1017 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1018 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1019 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1020 ; SDAG-GFX11-NEXT: s_nop 0
1021 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1022 ; SDAG-GFX11-NEXT: s_endpgm
1023 ;
1024 ; SDAG-GFX10-LABEL: v_icmp_i64_sge:
1025 ; SDAG-GFX10: ; %bb.0:
1026 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1027 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1028 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1029 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1030 ; SDAG-GFX10-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[4:5]
1031 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1032 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1033 ; SDAG-GFX10-NEXT: s_endpgm
1034 ;
1035 ; GISEL-GFX11-LABEL: v_icmp_i64_sge:
1036 ; GISEL-GFX11: ; %bb.0:
1037 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1038 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1039 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1040 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1041 ; GISEL-GFX11-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[4:5]
1042 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1043 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1044 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1045 ; GISEL-GFX11-NEXT: s_nop 0
1046 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1047 ; GISEL-GFX11-NEXT: s_endpgm
1048 ;
1049 ; GISEL-GFX10-LABEL: v_icmp_i64_sge:
1050 ; GISEL-GFX10: ; %bb.0:
1051 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1052 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1053 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1054 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1055 ; GISEL-GFX10-NEXT: v_cmp_ge_i64_e64 s2, s[2:3], s[4:5]
1056 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1057 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1058 ; GISEL-GFX10-NEXT: s_endpgm
1059 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 39)
1060 store i32 %result, ptr addrspace(1) %out
1061 ret void
1062 }
1064 define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
1065 ; SDAG-GFX11-LABEL: v_icmp_i64_slt:
1066 ; SDAG-GFX11: ; %bb.0:
1067 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1068 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1069 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1070 ; SDAG-GFX11-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[4:5]
1071 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1072 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1073 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1074 ; SDAG-GFX11-NEXT: s_nop 0
1075 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1076 ; SDAG-GFX11-NEXT: s_endpgm
1077 ;
1078 ; SDAG-GFX10-LABEL: v_icmp_i64_slt:
1079 ; SDAG-GFX10: ; %bb.0:
1080 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1081 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1082 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1083 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1084 ; SDAG-GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[4:5]
1085 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1086 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1087 ; SDAG-GFX10-NEXT: s_endpgm
1088 ;
1089 ; GISEL-GFX11-LABEL: v_icmp_i64_slt:
1090 ; GISEL-GFX11: ; %bb.0:
1091 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1092 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1093 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1094 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1095 ; GISEL-GFX11-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[4:5]
1096 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1097 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1098 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1099 ; GISEL-GFX11-NEXT: s_nop 0
1100 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1101 ; GISEL-GFX11-NEXT: s_endpgm
1102 ;
1103 ; GISEL-GFX10-LABEL: v_icmp_i64_slt:
1104 ; GISEL-GFX10: ; %bb.0:
1105 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1106 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1107 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1108 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1109 ; GISEL-GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[2:3], s[4:5]
1110 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1111 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1112 ; GISEL-GFX10-NEXT: s_endpgm
1113 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 40)
1114 store i32 %result, ptr addrspace(1) %out
1115 ret void
1116 }
1118 define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
1119 ; SDAG-GFX11-LABEL: v_icmp_i64_sle:
1120 ; SDAG-GFX11: ; %bb.0:
1121 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1122 ; SDAG-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1123 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1124 ; SDAG-GFX11-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[4:5]
1125 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1126 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1127 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1128 ; SDAG-GFX11-NEXT: s_nop 0
1129 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1130 ; SDAG-GFX11-NEXT: s_endpgm
1131 ;
1132 ; SDAG-GFX10-LABEL: v_icmp_i64_sle:
1133 ; SDAG-GFX10: ; %bb.0:
1134 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1135 ; SDAG-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1136 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1137 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1138 ; SDAG-GFX10-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[4:5]
1139 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1140 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1141 ; SDAG-GFX10-NEXT: s_endpgm
1142 ;
1143 ; GISEL-GFX11-LABEL: v_icmp_i64_sle:
1144 ; GISEL-GFX11: ; %bb.0:
1145 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1146 ; GISEL-GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1147 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1148 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1149 ; GISEL-GFX11-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[4:5]
1150 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1151 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1152 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1153 ; GISEL-GFX11-NEXT: s_nop 0
1154 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1155 ; GISEL-GFX11-NEXT: s_endpgm
1156 ;
1157 ; GISEL-GFX10-LABEL: v_icmp_i64_sle:
1158 ; GISEL-GFX10: ; %bb.0:
1159 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1160 ; GISEL-GFX10-NEXT: s_mov_b64 s[4:5], 0x64
1161 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1162 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1163 ; GISEL-GFX10-NEXT: v_cmp_le_i64_e64 s2, s[2:3], s[4:5]
1164 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1165 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1166 ; GISEL-GFX10-NEXT: s_endpgm
1167 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 41)
1168 store i32 %result, ptr addrspace(1) %out
1169 ret void
1170 }
1172 define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
1173 ; SDAG-GFX11-LABEL: v_icmp_i16_eq:
1174 ; SDAG-GFX11: ; %bb.0:
1175 ; SDAG-GFX11-NEXT: s_clause 0x1
1176 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1177 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1178 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1179 ; SDAG-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
1180 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1181 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1182 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1183 ; SDAG-GFX11-NEXT: s_nop 0
1184 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1185 ; SDAG-GFX11-NEXT: s_endpgm
1186 ;
1187 ; SDAG-GFX10-LABEL: v_icmp_i16_eq:
1188 ; SDAG-GFX10: ; %bb.0:
1189 ; SDAG-GFX10-NEXT: s_clause 0x1
1190 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1191 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1192 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1193 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1194 ; SDAG-GFX10-NEXT: v_cmp_eq_u16_e64 s0, 0x64, s4
1195 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1196 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1197 ; SDAG-GFX10-NEXT: s_endpgm
1198 ;
1199 ; GISEL-GFX11-LABEL: v_icmp_i16_eq:
1200 ; GISEL-GFX11: ; %bb.0:
1201 ; GISEL-GFX11-NEXT: s_clause 0x1
1202 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1203 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1204 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1205 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1206 ; GISEL-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
1207 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1208 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1209 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1210 ; GISEL-GFX11-NEXT: s_nop 0
1211 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1212 ; GISEL-GFX11-NEXT: s_endpgm
1213 ;
1214 ; GISEL-GFX10-LABEL: v_icmp_i16_eq:
1215 ; GISEL-GFX10: ; %bb.0:
1216 ; GISEL-GFX10-NEXT: s_clause 0x1
1217 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1218 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1219 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1220 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1221 ; GISEL-GFX10-NEXT: v_cmp_eq_u16_e64 s0, 0x64, s4
1222 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1223 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1224 ; GISEL-GFX10-NEXT: s_endpgm
1225 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 32)
1226 store i32 %result, ptr addrspace(1) %out
1227 ret void
1228 }
1230 define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
1231 ; SDAG-GFX11-LABEL: v_icmp_i16:
1232 ; SDAG-GFX11: ; %bb.0:
1233 ; SDAG-GFX11-NEXT: s_endpgm
1234 ;
1235 ; SDAG-GFX10-LABEL: v_icmp_i16:
1236 ; SDAG-GFX10: ; %bb.0:
1237 ; SDAG-GFX10-NEXT: s_endpgm
1238 ;
1239 ; GISEL-GFX11-LABEL: v_icmp_i16:
1240 ; GISEL-GFX11: ; %bb.0:
1241 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1242 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
1243 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1244 ; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
1245 ; GISEL-GFX11-NEXT: s_nop 0
1246 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1247 ; GISEL-GFX11-NEXT: s_endpgm
1248 ;
1249 ; GISEL-GFX10-LABEL: v_icmp_i16:
1250 ; GISEL-GFX10: ; %bb.0:
1251 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1252 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
1253 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1254 ; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
1255 ; GISEL-GFX10-NEXT: s_endpgm
1256 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 30)
1257 store i32 %result, ptr addrspace(1) %out
1258 ret void
1259 }
1261 define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
1262 ; SDAG-GFX11-LABEL: v_icmp_i16_ne:
1263 ; SDAG-GFX11: ; %bb.0:
1264 ; SDAG-GFX11-NEXT: s_clause 0x1
1265 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1266 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1267 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1268 ; SDAG-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
1269 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1270 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1271 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1272 ; SDAG-GFX11-NEXT: s_nop 0
1273 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1274 ; SDAG-GFX11-NEXT: s_endpgm
1275 ;
1276 ; SDAG-GFX10-LABEL: v_icmp_i16_ne:
1277 ; SDAG-GFX10: ; %bb.0:
1278 ; SDAG-GFX10-NEXT: s_clause 0x1
1279 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1280 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1281 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1282 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1283 ; SDAG-GFX10-NEXT: v_cmp_ne_u16_e64 s0, 0x64, s4
1284 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1285 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1286 ; SDAG-GFX10-NEXT: s_endpgm
1287 ;
1288 ; GISEL-GFX11-LABEL: v_icmp_i16_ne:
1289 ; GISEL-GFX11: ; %bb.0:
1290 ; GISEL-GFX11-NEXT: s_clause 0x1
1291 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1292 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1293 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1294 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1295 ; GISEL-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
1296 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1297 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1298 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1299 ; GISEL-GFX11-NEXT: s_nop 0
1300 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1301 ; GISEL-GFX11-NEXT: s_endpgm
1302 ;
1303 ; GISEL-GFX10-LABEL: v_icmp_i16_ne:
1304 ; GISEL-GFX10: ; %bb.0:
1305 ; GISEL-GFX10-NEXT: s_clause 0x1
1306 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1307 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1308 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1309 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1310 ; GISEL-GFX10-NEXT: v_cmp_ne_u16_e64 s0, 0x64, s4
1311 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1312 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1313 ; GISEL-GFX10-NEXT: s_endpgm
1314 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 33)
1315 store i32 %result, ptr addrspace(1) %out
1316 ret void
1317 }
1319 define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
1320 ; SDAG-GFX11-LABEL: v_icmp_i16_ugt:
1321 ; SDAG-GFX11: ; %bb.0:
1322 ; SDAG-GFX11-NEXT: s_clause 0x1
1323 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1324 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1325 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1326 ; SDAG-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
1327 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1328 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1329 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1330 ; SDAG-GFX11-NEXT: s_nop 0
1331 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1332 ; SDAG-GFX11-NEXT: s_endpgm
1333 ;
1334 ; SDAG-GFX10-LABEL: v_icmp_i16_ugt:
1335 ; SDAG-GFX10: ; %bb.0:
1336 ; SDAG-GFX10-NEXT: s_clause 0x1
1337 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1338 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1339 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1340 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1341 ; SDAG-GFX10-NEXT: v_cmp_lt_u16_e64 s0, 0x64, s4
1342 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1343 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1344 ; SDAG-GFX10-NEXT: s_endpgm
1345 ;
1346 ; GISEL-GFX11-LABEL: v_icmp_i16_ugt:
1347 ; GISEL-GFX11: ; %bb.0:
1348 ; GISEL-GFX11-NEXT: s_clause 0x1
1349 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1350 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1351 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1352 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1353 ; GISEL-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
1354 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1355 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1356 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1357 ; GISEL-GFX11-NEXT: s_nop 0
1358 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1359 ; GISEL-GFX11-NEXT: s_endpgm
1360 ;
1361 ; GISEL-GFX10-LABEL: v_icmp_i16_ugt:
1362 ; GISEL-GFX10: ; %bb.0:
1363 ; GISEL-GFX10-NEXT: s_clause 0x1
1364 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1365 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1366 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1367 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1368 ; GISEL-GFX10-NEXT: v_cmp_lt_u16_e64 s0, 0x64, s4
1369 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1370 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1371 ; GISEL-GFX10-NEXT: s_endpgm
1372 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 34)
1373 store i32 %result, ptr addrspace(1) %out
1374 ret void
1375 }
1377 define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
1378 ; SDAG-GFX11-LABEL: v_icmp_i16_uge:
1379 ; SDAG-GFX11: ; %bb.0:
1380 ; SDAG-GFX11-NEXT: s_clause 0x1
1381 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1382 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1383 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1384 ; SDAG-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
1385 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1386 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1387 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1388 ; SDAG-GFX11-NEXT: s_nop 0
1389 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1390 ; SDAG-GFX11-NEXT: s_endpgm
1391 ;
1392 ; SDAG-GFX10-LABEL: v_icmp_i16_uge:
1393 ; SDAG-GFX10: ; %bb.0:
1394 ; SDAG-GFX10-NEXT: s_clause 0x1
1395 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1396 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1397 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1398 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1399 ; SDAG-GFX10-NEXT: v_cmp_le_u16_e64 s0, 0x64, s4
1400 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1401 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1402 ; SDAG-GFX10-NEXT: s_endpgm
1403 ;
1404 ; GISEL-GFX11-LABEL: v_icmp_i16_uge:
1405 ; GISEL-GFX11: ; %bb.0:
1406 ; GISEL-GFX11-NEXT: s_clause 0x1
1407 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1408 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1409 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1410 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1411 ; GISEL-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
1412 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1413 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1414 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1415 ; GISEL-GFX11-NEXT: s_nop 0
1416 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1417 ; GISEL-GFX11-NEXT: s_endpgm
1418 ;
1419 ; GISEL-GFX10-LABEL: v_icmp_i16_uge:
1420 ; GISEL-GFX10: ; %bb.0:
1421 ; GISEL-GFX10-NEXT: s_clause 0x1
1422 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1423 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1424 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1425 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1426 ; GISEL-GFX10-NEXT: v_cmp_le_u16_e64 s0, 0x64, s4
1427 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1428 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1429 ; GISEL-GFX10-NEXT: s_endpgm
1430 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 35)
1431 store i32 %result, ptr addrspace(1) %out
1432 ret void
1433 }
1435 define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
1436 ; SDAG-GFX11-LABEL: v_icmp_i16_ult:
1437 ; SDAG-GFX11: ; %bb.0:
1438 ; SDAG-GFX11-NEXT: s_clause 0x1
1439 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1440 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1441 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1442 ; SDAG-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
1443 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1444 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1445 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1446 ; SDAG-GFX11-NEXT: s_nop 0
1447 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1448 ; SDAG-GFX11-NEXT: s_endpgm
1449 ;
1450 ; SDAG-GFX10-LABEL: v_icmp_i16_ult:
1451 ; SDAG-GFX10: ; %bb.0:
1452 ; SDAG-GFX10-NEXT: s_clause 0x1
1453 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1454 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1455 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1456 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1457 ; SDAG-GFX10-NEXT: v_cmp_gt_u16_e64 s0, 0x64, s4
1458 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1459 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1460 ; SDAG-GFX10-NEXT: s_endpgm
1461 ;
1462 ; GISEL-GFX11-LABEL: v_icmp_i16_ult:
1463 ; GISEL-GFX11: ; %bb.0:
1464 ; GISEL-GFX11-NEXT: s_clause 0x1
1465 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1466 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1467 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1468 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1469 ; GISEL-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
1470 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1471 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1472 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1473 ; GISEL-GFX11-NEXT: s_nop 0
1474 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1475 ; GISEL-GFX11-NEXT: s_endpgm
1476 ;
1477 ; GISEL-GFX10-LABEL: v_icmp_i16_ult:
1478 ; GISEL-GFX10: ; %bb.0:
1479 ; GISEL-GFX10-NEXT: s_clause 0x1
1480 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1481 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1482 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1483 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1484 ; GISEL-GFX10-NEXT: v_cmp_gt_u16_e64 s0, 0x64, s4
1485 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1486 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1487 ; GISEL-GFX10-NEXT: s_endpgm
1488 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 36)
1489 store i32 %result, ptr addrspace(1) %out
1490 ret void
1491 }
1493 define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
1494 ; SDAG-GFX11-LABEL: v_icmp_i16_ule:
1495 ; SDAG-GFX11: ; %bb.0:
1496 ; SDAG-GFX11-NEXT: s_clause 0x1
1497 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1498 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1499 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1500 ; SDAG-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
1501 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1502 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1503 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1504 ; SDAG-GFX11-NEXT: s_nop 0
1505 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1506 ; SDAG-GFX11-NEXT: s_endpgm
1507 ;
1508 ; SDAG-GFX10-LABEL: v_icmp_i16_ule:
1509 ; SDAG-GFX10: ; %bb.0:
1510 ; SDAG-GFX10-NEXT: s_clause 0x1
1511 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1512 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1513 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1514 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1515 ; SDAG-GFX10-NEXT: v_cmp_ge_u16_e64 s0, 0x64, s4
1516 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1517 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1518 ; SDAG-GFX10-NEXT: s_endpgm
1519 ;
1520 ; GISEL-GFX11-LABEL: v_icmp_i16_ule:
1521 ; GISEL-GFX11: ; %bb.0:
1522 ; GISEL-GFX11-NEXT: s_clause 0x1
1523 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1524 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1525 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1526 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1527 ; GISEL-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
1528 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1529 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1530 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1531 ; GISEL-GFX11-NEXT: s_nop 0
1532 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1533 ; GISEL-GFX11-NEXT: s_endpgm
1534 ;
1535 ; GISEL-GFX10-LABEL: v_icmp_i16_ule:
1536 ; GISEL-GFX10: ; %bb.0:
1537 ; GISEL-GFX10-NEXT: s_clause 0x1
1538 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1539 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1540 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1541 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1542 ; GISEL-GFX10-NEXT: v_cmp_ge_u16_e64 s0, 0x64, s4
1543 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1544 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1545 ; GISEL-GFX10-NEXT: s_endpgm
1546 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 37)
1547 store i32 %result, ptr addrspace(1) %out
1548 ret void
1549 }
1551 define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
1552 ; SDAG-GFX11-LABEL: v_icmp_i16_sgt:
1553 ; SDAG-GFX11: ; %bb.0:
1554 ; SDAG-GFX11-NEXT: s_clause 0x1
1555 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1556 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1557 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1558 ; SDAG-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
1559 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1560 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1561 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1562 ; SDAG-GFX11-NEXT: s_nop 0
1563 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1564 ; SDAG-GFX11-NEXT: s_endpgm
1565 ;
1566 ; SDAG-GFX10-LABEL: v_icmp_i16_sgt:
1567 ; SDAG-GFX10: ; %bb.0:
1568 ; SDAG-GFX10-NEXT: s_clause 0x1
1569 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1570 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1571 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1572 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1573 ; SDAG-GFX10-NEXT: v_cmp_lt_i16_e64 s0, 0x64, s4
1574 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1575 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1576 ; SDAG-GFX10-NEXT: s_endpgm
1577 ;
1578 ; GISEL-GFX11-LABEL: v_icmp_i16_sgt:
1579 ; GISEL-GFX11: ; %bb.0:
1580 ; GISEL-GFX11-NEXT: s_clause 0x1
1581 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1582 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1583 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1584 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1585 ; GISEL-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
1586 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1587 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1588 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1589 ; GISEL-GFX11-NEXT: s_nop 0
1590 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1591 ; GISEL-GFX11-NEXT: s_endpgm
1592 ;
1593 ; GISEL-GFX10-LABEL: v_icmp_i16_sgt:
1594 ; GISEL-GFX10: ; %bb.0:
1595 ; GISEL-GFX10-NEXT: s_clause 0x1
1596 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1597 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1598 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1599 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1600 ; GISEL-GFX10-NEXT: v_cmp_lt_i16_e64 s0, 0x64, s4
1601 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1602 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1603 ; GISEL-GFX10-NEXT: s_endpgm
1604 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 38)
1605 store i32 %result, ptr addrspace(1) %out
1606 ret void
1607 }
1609 define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
1610 ; SDAG-GFX11-LABEL: v_icmp_i16_sge:
1611 ; SDAG-GFX11: ; %bb.0:
1612 ; SDAG-GFX11-NEXT: s_clause 0x1
1613 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1614 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1615 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1616 ; SDAG-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
1617 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1618 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1619 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1620 ; SDAG-GFX11-NEXT: s_nop 0
1621 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1622 ; SDAG-GFX11-NEXT: s_endpgm
1623 ;
1624 ; SDAG-GFX10-LABEL: v_icmp_i16_sge:
1625 ; SDAG-GFX10: ; %bb.0:
1626 ; SDAG-GFX10-NEXT: s_clause 0x1
1627 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1628 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1629 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1630 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1631 ; SDAG-GFX10-NEXT: v_cmp_le_i16_e64 s0, 0x64, s4
1632 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1633 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1634 ; SDAG-GFX10-NEXT: s_endpgm
1635 ;
1636 ; GISEL-GFX11-LABEL: v_icmp_i16_sge:
1637 ; GISEL-GFX11: ; %bb.0:
1638 ; GISEL-GFX11-NEXT: s_clause 0x1
1639 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1640 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1641 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1642 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1643 ; GISEL-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
1644 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1645 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1646 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1647 ; GISEL-GFX11-NEXT: s_nop 0
1648 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1649 ; GISEL-GFX11-NEXT: s_endpgm
1650 ;
1651 ; GISEL-GFX10-LABEL: v_icmp_i16_sge:
1652 ; GISEL-GFX10: ; %bb.0:
1653 ; GISEL-GFX10-NEXT: s_clause 0x1
1654 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1655 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1656 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1657 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1658 ; GISEL-GFX10-NEXT: v_cmp_le_i16_e64 s0, 0x64, s4
1659 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1660 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1661 ; GISEL-GFX10-NEXT: s_endpgm
1662 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 39)
1663 store i32 %result, ptr addrspace(1) %out
1664 ret void
1665 }
1667 define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
1668 ; SDAG-GFX11-LABEL: v_icmp_i16_slt:
1669 ; SDAG-GFX11: ; %bb.0:
1670 ; SDAG-GFX11-NEXT: s_clause 0x1
1671 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1672 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1673 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1674 ; SDAG-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
1675 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1676 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1677 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1678 ; SDAG-GFX11-NEXT: s_nop 0
1679 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1680 ; SDAG-GFX11-NEXT: s_endpgm
1681 ;
1682 ; SDAG-GFX10-LABEL: v_icmp_i16_slt:
1683 ; SDAG-GFX10: ; %bb.0:
1684 ; SDAG-GFX10-NEXT: s_clause 0x1
1685 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1686 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1687 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1688 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1689 ; SDAG-GFX10-NEXT: v_cmp_gt_i16_e64 s0, 0x64, s4
1690 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1691 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1692 ; SDAG-GFX10-NEXT: s_endpgm
1693 ;
1694 ; GISEL-GFX11-LABEL: v_icmp_i16_slt:
1695 ; GISEL-GFX11: ; %bb.0:
1696 ; GISEL-GFX11-NEXT: s_clause 0x1
1697 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1698 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1699 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1700 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1701 ; GISEL-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
1702 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1703 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1704 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1705 ; GISEL-GFX11-NEXT: s_nop 0
1706 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1707 ; GISEL-GFX11-NEXT: s_endpgm
1708 ;
1709 ; GISEL-GFX10-LABEL: v_icmp_i16_slt:
1710 ; GISEL-GFX10: ; %bb.0:
1711 ; GISEL-GFX10-NEXT: s_clause 0x1
1712 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1713 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1714 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1715 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1716 ; GISEL-GFX10-NEXT: v_cmp_gt_i16_e64 s0, 0x64, s4
1717 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1718 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1719 ; GISEL-GFX10-NEXT: s_endpgm
1720 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 40)
1721 store i32 %result, ptr addrspace(1) %out
1722 ret void
1723 }
1725 define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
1726 ; SDAG-GFX11-LABEL: v_icmp_i16_sle:
1727 ; SDAG-GFX11: ; %bb.0:
1728 ; SDAG-GFX11-NEXT: s_clause 0x1
1729 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1730 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1731 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1732 ; SDAG-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
1733 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1734 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1735 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1736 ; SDAG-GFX11-NEXT: s_nop 0
1737 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1738 ; SDAG-GFX11-NEXT: s_endpgm
1739 ;
1740 ; SDAG-GFX10-LABEL: v_icmp_i16_sle:
1741 ; SDAG-GFX10: ; %bb.0:
1742 ; SDAG-GFX10-NEXT: s_clause 0x1
1743 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1744 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1745 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1746 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1747 ; SDAG-GFX10-NEXT: v_cmp_ge_i16_e64 s0, 0x64, s4
1748 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1749 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1750 ; SDAG-GFX10-NEXT: s_endpgm
1751 ;
1752 ; GISEL-GFX11-LABEL: v_icmp_i16_sle:
1753 ; GISEL-GFX11: ; %bb.0:
1754 ; GISEL-GFX11-NEXT: s_clause 0x1
1755 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1756 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1757 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1758 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1759 ; GISEL-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
1760 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1761 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1762 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1763 ; GISEL-GFX11-NEXT: s_nop 0
1764 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1765 ; GISEL-GFX11-NEXT: s_endpgm
1766 ;
1767 ; GISEL-GFX10-LABEL: v_icmp_i16_sle:
1768 ; GISEL-GFX10: ; %bb.0:
1769 ; GISEL-GFX10-NEXT: s_clause 0x1
1770 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1771 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1772 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1773 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1774 ; GISEL-GFX10-NEXT: v_cmp_ge_i16_e64 s0, 0x64, s4
1775 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1776 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1777 ; GISEL-GFX10-NEXT: s_endpgm
1778 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
1779 store i32 %result, ptr addrspace(1) %out
1780 ret void
1781 }
1783 define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b) {
1784 ; GFX11-LABEL: v_icmp_i1_ne0:
1785 ; GFX11: ; %bb.0:
1786 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1787 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1788 ; GFX11-NEXT: s_cmp_gt_u32 s2, 1
1789 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
1790 ; GFX11-NEXT: s_cmp_gt_u32 s3, 2
1791 ; GFX11-NEXT: s_cselect_b32 s3, -1, 0
1792 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
1793 ; GFX11-NEXT: s_and_b32 s2, s2, s3
1794 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1795 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1796 ; GFX11-NEXT: s_nop 0
1797 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1798 ; GFX11-NEXT: s_endpgm
1799 ;
1800 ; GFX10-LABEL: v_icmp_i1_ne0:
1801 ; GFX10: ; %bb.0:
1802 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1803 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
1804 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1805 ; GFX10-NEXT: s_cmp_gt_u32 s2, 1
1806 ; GFX10-NEXT: s_cselect_b32 s2, -1, 0
1807 ; GFX10-NEXT: s_cmp_gt_u32 s3, 2
1808 ; GFX10-NEXT: s_cselect_b32 s3, -1, 0
1809 ; GFX10-NEXT: s_and_b32 s2, s2, s3
1810 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
1811 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1812 ; GFX10-NEXT: s_endpgm
1813 %c0 = icmp ugt i32 %a, 1
1814 %c1 = icmp ugt i32 %b, 2
1815 %src = and i1 %c0, %c1
1816 %result = call i32 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
1817 store i32 %result, ptr addrspace(1) %out
1818 ret void
1819 }
1821 define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(ptr addrspace(1) %out, i32 %src) {
1822 ; SDAG-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
1823 ; SDAG-GFX11: ; %bb.0:
1824 ; SDAG-GFX11-NEXT: s_endpgm
1825 ;
1826 ; SDAG-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
1827 ; SDAG-GFX10: ; %bb.0:
1828 ; SDAG-GFX10-NEXT: s_endpgm
1829 ;
1830 ; GISEL-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
1831 ; GISEL-GFX11: ; %bb.0:
1832 ; GISEL-GFX11-NEXT: global_store_b32 v[0:1], v0, off
1833 ; GISEL-GFX11-NEXT: s_nop 0
1834 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1835 ; GISEL-GFX11-NEXT: s_endpgm
1836 ;
1837 ; GISEL-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
1838 ; GISEL-GFX10: ; %bb.0:
1839 ; GISEL-GFX10-NEXT: global_store_dword v[0:1], v0, off
1840 ; GISEL-GFX10-NEXT: s_endpgm
1841 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 9999)
1842 store i32 %result, ptr addrspace(1) %out
1843 ret void
1844 }
1846 attributes #0 = { nounwind readnone convergent }
1847 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
1848 ; GCN: {{.*}}