| blob | 5d1aa7cbb9992bc6b7fb6642be91a1cb8629a3d9 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
3 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SDAG-VI %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,SDAG-GFX9 %s
6 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
7 ; RUN: FileCheck --check-prefix=ERR %s < %t
8 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,VI,GISEL-VI %s
9 ; RUN: FileCheck --check-prefix=ERR %s < %t
10 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX9,GISEL-GFX9 %s
11 ; RUN: FileCheck --check-prefix=ERR %s < %t
13 ; Note: GlobalISel abort is disabled so we don't crash on i1 inputs.
14 ; They are allowed in DAGISel but we (intentionally) don't support them
15 ; in GlobalISel.
17 ; ERR: warning: Instruction selection used fallback path for v_icmp_i1_ne0
19 declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
20 declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
21 declare i64 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
22 declare i64 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
24 define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
25 ; GFX11-LABEL: v_icmp_i32_eq:
26 ; GFX11: ; %bb.0:
27 ; GFX11-NEXT: s_clause 0x1
28 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
29 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
30 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
31 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
32 ; GFX11-NEXT: v_cmp_eq_u32_e64 s[2:3], 0x64, s2
33 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
34 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
35 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
36 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
37 ; GFX11-NEXT: s_nop 0
38 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
39 ; GFX11-NEXT: s_endpgm
40 ;
41 ; SDAG-VI-LABEL: v_icmp_i32_eq:
42 ; SDAG-VI: ; %bb.0:
43 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
44 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
45 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
46 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
47 ; SDAG-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
48 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
49 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
50 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
51 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
52 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
53 ; SDAG-VI-NEXT: s_endpgm
54 ;
55 ; GFX9-LABEL: v_icmp_i32_eq:
56 ; GFX9: ; %bb.0:
57 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
58 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
59 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
60 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
61 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
62 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, v0
63 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
64 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
65 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
66 ; GFX9-NEXT: s_endpgm
67 ;
68 ; GISEL-VI-LABEL: v_icmp_i32_eq:
69 ; GISEL-VI: ; %bb.0:
70 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
71 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
72 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
73 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
74 ; GISEL-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
75 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
76 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
77 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
78 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
79 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
80 ; GISEL-VI-NEXT: s_endpgm
81 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 32)
82 store i64 %result, ptr addrspace(1) %out
83 ret void
84 }
86 define amdgpu_kernel void @v_icmp_i32(ptr addrspace(1) %out, i32 %src) {
87 ; SDAG-GFX11-LABEL: v_icmp_i32:
88 ; SDAG-GFX11: ; %bb.0:
89 ; SDAG-GFX11-NEXT: s_endpgm
90 ;
91 ; SDAG-VI-LABEL: v_icmp_i32:
92 ; SDAG-VI: ; %bb.0:
93 ; SDAG-VI-NEXT: s_endpgm
94 ;
95 ; SDAG-GFX9-LABEL: v_icmp_i32:
96 ; SDAG-GFX9: ; %bb.0:
97 ; SDAG-GFX9-NEXT: s_endpgm
98 ;
99 ; GISEL-GFX11-LABEL: v_icmp_i32:
100 ; GISEL-GFX11: ; %bb.0:
101 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
102 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
103 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
104 ; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]
105 ; GISEL-GFX11-NEXT: s_nop 0
106 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
107 ; GISEL-GFX11-NEXT: s_endpgm
108 ;
109 ; GISEL-VI-LABEL: v_icmp_i32:
110 ; GISEL-VI: ; %bb.0:
111 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
112 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
113 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
114 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
115 ; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
116 ; GISEL-VI-NEXT: s_endpgm
117 ;
118 ; GISEL-GFX9-LABEL: v_icmp_i32:
119 ; GISEL-GFX9: ; %bb.0:
120 ; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
121 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0
122 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
123 ; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
124 ; GISEL-GFX9-NEXT: s_endpgm
125 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 30)
126 store i64 %result, ptr addrspace(1) %out
127 ret void
128 }
130 define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
131 ; GFX11-LABEL: v_icmp_i32_ne:
132 ; GFX11: ; %bb.0:
133 ; GFX11-NEXT: s_clause 0x1
134 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
135 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
136 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
137 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
138 ; GFX11-NEXT: v_cmp_ne_u32_e64 s[2:3], 0x64, s2
139 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
140 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
141 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
142 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
143 ; GFX11-NEXT: s_nop 0
144 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
145 ; GFX11-NEXT: s_endpgm
146 ;
147 ; SDAG-VI-LABEL: v_icmp_i32_ne:
148 ; SDAG-VI: ; %bb.0:
149 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
150 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
151 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
152 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
153 ; SDAG-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
154 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
155 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
156 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
157 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
158 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
159 ; SDAG-VI-NEXT: s_endpgm
160 ;
161 ; GFX9-LABEL: v_icmp_i32_ne:
162 ; GFX9: ; %bb.0:
163 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
164 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
165 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
166 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
167 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
168 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], s4, v0
169 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
170 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
171 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
172 ; GFX9-NEXT: s_endpgm
173 ;
174 ; GISEL-VI-LABEL: v_icmp_i32_ne:
175 ; GISEL-VI: ; %bb.0:
176 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
177 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
178 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
179 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
180 ; GISEL-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
181 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
182 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
183 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
184 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
185 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
186 ; GISEL-VI-NEXT: s_endpgm
187 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 33)
188 store i64 %result, ptr addrspace(1) %out
189 ret void
190 }
192 define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
193 ; GFX11-LABEL: v_icmp_i32_ugt:
194 ; GFX11: ; %bb.0:
195 ; GFX11-NEXT: s_clause 0x1
196 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
197 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
198 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
199 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
200 ; GFX11-NEXT: v_cmp_lt_u32_e64 s[2:3], 0x64, s2
201 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
202 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
203 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
204 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
205 ; GFX11-NEXT: s_nop 0
206 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
207 ; GFX11-NEXT: s_endpgm
208 ;
209 ; SDAG-VI-LABEL: v_icmp_i32_ugt:
210 ; SDAG-VI: ; %bb.0:
211 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
212 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
213 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
214 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
215 ; SDAG-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
216 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
217 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
218 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
219 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
220 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
221 ; SDAG-VI-NEXT: s_endpgm
222 ;
223 ; GFX9-LABEL: v_icmp_i32_ugt:
224 ; GFX9: ; %bb.0:
225 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
226 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
227 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
228 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
229 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
230 ; GFX9-NEXT: v_cmp_gt_u32_e64 s[0:1], s4, v0
231 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
232 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
233 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
234 ; GFX9-NEXT: s_endpgm
235 ;
236 ; GISEL-VI-LABEL: v_icmp_i32_ugt:
237 ; GISEL-VI: ; %bb.0:
238 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
239 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
240 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
241 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
242 ; GISEL-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
243 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
244 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
245 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
246 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
247 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
248 ; GISEL-VI-NEXT: s_endpgm
249 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 34)
250 store i64 %result, ptr addrspace(1) %out
251 ret void
252 }
254 define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
255 ; GFX11-LABEL: v_icmp_i32_uge:
256 ; GFX11: ; %bb.0:
257 ; GFX11-NEXT: s_clause 0x1
258 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
259 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
260 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
261 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
262 ; GFX11-NEXT: v_cmp_le_u32_e64 s[2:3], 0x64, s2
263 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
264 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
265 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
266 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
267 ; GFX11-NEXT: s_nop 0
268 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
269 ; GFX11-NEXT: s_endpgm
270 ;
271 ; SDAG-VI-LABEL: v_icmp_i32_uge:
272 ; SDAG-VI: ; %bb.0:
273 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
274 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
275 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
276 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
277 ; SDAG-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
278 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
279 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
280 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
281 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
282 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
283 ; SDAG-VI-NEXT: s_endpgm
284 ;
285 ; GFX9-LABEL: v_icmp_i32_uge:
286 ; GFX9: ; %bb.0:
287 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
288 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
289 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
290 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
291 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
292 ; GFX9-NEXT: v_cmp_ge_u32_e64 s[0:1], s4, v0
293 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
294 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
295 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
296 ; GFX9-NEXT: s_endpgm
297 ;
298 ; GISEL-VI-LABEL: v_icmp_i32_uge:
299 ; GISEL-VI: ; %bb.0:
300 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
301 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
302 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
303 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
304 ; GISEL-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
305 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
306 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
307 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
308 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
309 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
310 ; GISEL-VI-NEXT: s_endpgm
311 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 35)
312 store i64 %result, ptr addrspace(1) %out
313 ret void
314 }
316 define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
317 ; GFX11-LABEL: v_icmp_i32_ult:
318 ; GFX11: ; %bb.0:
319 ; GFX11-NEXT: s_clause 0x1
320 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
321 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
322 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
323 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
324 ; GFX11-NEXT: v_cmp_gt_u32_e64 s[2:3], 0x64, s2
325 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
326 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
327 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
328 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
329 ; GFX11-NEXT: s_nop 0
330 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
331 ; GFX11-NEXT: s_endpgm
332 ;
333 ; SDAG-VI-LABEL: v_icmp_i32_ult:
334 ; SDAG-VI: ; %bb.0:
335 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
336 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
337 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
338 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
339 ; SDAG-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
340 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
341 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
342 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
343 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
344 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
345 ; SDAG-VI-NEXT: s_endpgm
346 ;
347 ; GFX9-LABEL: v_icmp_i32_ult:
348 ; GFX9: ; %bb.0:
349 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
350 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
351 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
352 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
353 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
354 ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v0
355 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
356 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
357 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
358 ; GFX9-NEXT: s_endpgm
359 ;
360 ; GISEL-VI-LABEL: v_icmp_i32_ult:
361 ; GISEL-VI: ; %bb.0:
362 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
363 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
364 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
365 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
366 ; GISEL-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
367 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
368 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
369 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
370 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
371 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
372 ; GISEL-VI-NEXT: s_endpgm
373 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 36)
374 store i64 %result, ptr addrspace(1) %out
375 ret void
376 }
378 define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
379 ; GFX11-LABEL: v_icmp_i32_ule:
380 ; GFX11: ; %bb.0:
381 ; GFX11-NEXT: s_clause 0x1
382 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
383 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
384 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
385 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
386 ; GFX11-NEXT: v_cmp_ge_u32_e64 s[2:3], 0x64, s2
387 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
388 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
389 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
390 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
391 ; GFX11-NEXT: s_nop 0
392 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
393 ; GFX11-NEXT: s_endpgm
394 ;
395 ; SDAG-VI-LABEL: v_icmp_i32_ule:
396 ; SDAG-VI: ; %bb.0:
397 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
398 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
399 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
400 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
401 ; SDAG-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
402 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
403 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
404 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
405 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
406 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
407 ; SDAG-VI-NEXT: s_endpgm
408 ;
409 ; GFX9-LABEL: v_icmp_i32_ule:
410 ; GFX9: ; %bb.0:
411 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
412 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
413 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
414 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
415 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
416 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s4, v0
417 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
418 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
419 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
420 ; GFX9-NEXT: s_endpgm
421 ;
422 ; GISEL-VI-LABEL: v_icmp_i32_ule:
423 ; GISEL-VI: ; %bb.0:
424 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
425 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
426 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
427 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
428 ; GISEL-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
429 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
430 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
431 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
432 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
433 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
434 ; GISEL-VI-NEXT: s_endpgm
435 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 37)
436 store i64 %result, ptr addrspace(1) %out
437 ret void
438 }
440 define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
441 ; GFX11-LABEL: v_icmp_i32_sgt:
442 ; GFX11: ; %bb.0:
443 ; GFX11-NEXT: s_clause 0x1
444 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
445 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
446 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
447 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
448 ; GFX11-NEXT: v_cmp_lt_i32_e64 s[2:3], 0x64, s2
449 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
450 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
451 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
452 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
453 ; GFX11-NEXT: s_nop 0
454 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
455 ; GFX11-NEXT: s_endpgm
456 ;
457 ; SDAG-VI-LABEL: v_icmp_i32_sgt:
458 ; SDAG-VI: ; %bb.0:
459 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
460 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
461 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
462 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
463 ; SDAG-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
464 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
465 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
466 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
467 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
468 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
469 ; SDAG-VI-NEXT: s_endpgm
470 ;
471 ; GFX9-LABEL: v_icmp_i32_sgt:
472 ; GFX9: ; %bb.0:
473 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
474 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
475 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
476 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
477 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
478 ; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], s4, v0
479 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
480 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
481 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
482 ; GFX9-NEXT: s_endpgm
483 ;
484 ; GISEL-VI-LABEL: v_icmp_i32_sgt:
485 ; GISEL-VI: ; %bb.0:
486 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
487 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
488 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
489 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
490 ; GISEL-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
491 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
492 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
493 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
494 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
495 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
496 ; GISEL-VI-NEXT: s_endpgm
497 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 38)
498 store i64 %result, ptr addrspace(1) %out
499 ret void
500 }
502 define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
503 ; GFX11-LABEL: v_icmp_i32_sge:
504 ; GFX11: ; %bb.0:
505 ; GFX11-NEXT: s_clause 0x1
506 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
507 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
508 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
509 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
510 ; GFX11-NEXT: v_cmp_le_i32_e64 s[2:3], 0x64, s2
511 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
512 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
513 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
514 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
515 ; GFX11-NEXT: s_nop 0
516 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
517 ; GFX11-NEXT: s_endpgm
518 ;
519 ; SDAG-VI-LABEL: v_icmp_i32_sge:
520 ; SDAG-VI: ; %bb.0:
521 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
522 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
523 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
524 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
525 ; SDAG-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
526 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
527 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
528 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
529 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
530 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
531 ; SDAG-VI-NEXT: s_endpgm
532 ;
533 ; GFX9-LABEL: v_icmp_i32_sge:
534 ; GFX9: ; %bb.0:
535 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
536 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
537 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
538 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
539 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
540 ; GFX9-NEXT: v_cmp_ge_i32_e64 s[0:1], s4, v0
541 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
542 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
543 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
544 ; GFX9-NEXT: s_endpgm
545 ;
546 ; GISEL-VI-LABEL: v_icmp_i32_sge:
547 ; GISEL-VI: ; %bb.0:
548 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
549 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
550 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
551 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
552 ; GISEL-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
553 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
554 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
555 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
556 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
557 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
558 ; GISEL-VI-NEXT: s_endpgm
559 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 39)
560 store i64 %result, ptr addrspace(1) %out
561 ret void
562 }
564 define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
565 ; GFX11-LABEL: v_icmp_i32_slt:
566 ; GFX11: ; %bb.0:
567 ; GFX11-NEXT: s_clause 0x1
568 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
569 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
570 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
571 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
572 ; GFX11-NEXT: v_cmp_gt_i32_e64 s[2:3], 0x64, s2
573 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
574 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
575 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
576 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
577 ; GFX11-NEXT: s_nop 0
578 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
579 ; GFX11-NEXT: s_endpgm
580 ;
581 ; SDAG-VI-LABEL: v_icmp_i32_slt:
582 ; SDAG-VI: ; %bb.0:
583 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
584 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
585 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
586 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
587 ; SDAG-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
588 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
589 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
590 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
591 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
592 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
593 ; SDAG-VI-NEXT: s_endpgm
594 ;
595 ; GFX9-LABEL: v_icmp_i32_slt:
596 ; GFX9: ; %bb.0:
597 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
598 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
599 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
600 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
601 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
602 ; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], s4, v0
603 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
604 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
605 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
606 ; GFX9-NEXT: s_endpgm
607 ;
608 ; GISEL-VI-LABEL: v_icmp_i32_slt:
609 ; GISEL-VI: ; %bb.0:
610 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
611 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
612 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
613 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
614 ; GISEL-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
615 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
616 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
617 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
618 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
619 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
620 ; GISEL-VI-NEXT: s_endpgm
621 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 40)
622 store i64 %result, ptr addrspace(1) %out
623 ret void
624 }
626 define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
627 ; GFX11-LABEL: v_icmp_i32_sle:
628 ; GFX11: ; %bb.0:
629 ; GFX11-NEXT: s_clause 0x1
630 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
631 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
632 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
633 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
634 ; GFX11-NEXT: v_cmp_ge_i32_e64 s[2:3], 0x64, s2
635 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
636 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
637 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
638 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
639 ; GFX11-NEXT: s_nop 0
640 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
641 ; GFX11-NEXT: s_endpgm
642 ;
643 ; SDAG-VI-LABEL: v_icmp_i32_sle:
644 ; SDAG-VI: ; %bb.0:
645 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
646 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
647 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
648 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
649 ; SDAG-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
650 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
651 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
652 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
653 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
654 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
655 ; SDAG-VI-NEXT: s_endpgm
656 ;
657 ; GFX9-LABEL: v_icmp_i32_sle:
658 ; GFX9: ; %bb.0:
659 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
660 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
661 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
662 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
663 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
664 ; GFX9-NEXT: v_cmp_le_i32_e64 s[0:1], s4, v0
665 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
666 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
667 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
668 ; GFX9-NEXT: s_endpgm
669 ;
670 ; GISEL-VI-LABEL: v_icmp_i32_sle:
671 ; GISEL-VI: ; %bb.0:
672 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
673 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
674 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
675 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
676 ; GISEL-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
677 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
678 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
679 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
680 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
681 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
682 ; GISEL-VI-NEXT: s_endpgm
683 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 41)
684 store i64 %result, ptr addrspace(1) %out
685 ret void
686 }
688 define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
689 ; GFX11-LABEL: v_icmp_i64_eq:
690 ; GFX11: ; %bb.0:
691 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
692 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
693 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
694 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
695 ; GFX11-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], s[4:5]
696 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
697 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
698 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
699 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
700 ; GFX11-NEXT: s_nop 0
701 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
702 ; GFX11-NEXT: s_endpgm
703 ;
704 ; SDAG-VI-LABEL: v_icmp_i64_eq:
705 ; SDAG-VI: ; %bb.0:
706 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
707 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
708 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
709 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
710 ; SDAG-VI-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
711 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
712 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
713 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
714 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
715 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
716 ; SDAG-VI-NEXT: s_endpgm
717 ;
718 ; SDAG-GFX9-LABEL: v_icmp_i64_eq:
719 ; SDAG-GFX9: ; %bb.0:
720 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
721 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
722 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
723 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
724 ; SDAG-GFX9-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
725 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
726 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
727 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
728 ; SDAG-GFX9-NEXT: s_endpgm
729 ;
730 ; GISEL-VI-LABEL: v_icmp_i64_eq:
731 ; GISEL-VI: ; %bb.0:
732 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
733 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
734 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
735 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
736 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
737 ; GISEL-VI-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
738 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
739 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
740 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
741 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
742 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
743 ; GISEL-VI-NEXT: s_endpgm
744 ;
745 ; GISEL-GFX9-LABEL: v_icmp_i64_eq:
746 ; GISEL-GFX9: ; %bb.0:
747 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
748 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
749 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
750 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
751 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
752 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
753 ; GISEL-GFX9-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
754 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
755 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
756 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
757 ; GISEL-GFX9-NEXT: s_endpgm
758 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 32)
759 store i64 %result, ptr addrspace(1) %out
760 ret void
761 }
763 define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
764 ; GFX11-LABEL: v_icmp_i64_ne:
765 ; GFX11: ; %bb.0:
766 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
767 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
768 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
769 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
770 ; GFX11-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], s[4:5]
771 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
772 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
773 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
774 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
775 ; GFX11-NEXT: s_nop 0
776 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
777 ; GFX11-NEXT: s_endpgm
778 ;
779 ; SDAG-VI-LABEL: v_icmp_i64_ne:
780 ; SDAG-VI: ; %bb.0:
781 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
782 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
783 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
784 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
785 ; SDAG-VI-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
786 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
787 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
788 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
789 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
790 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
791 ; SDAG-VI-NEXT: s_endpgm
792 ;
793 ; SDAG-GFX9-LABEL: v_icmp_i64_ne:
794 ; SDAG-GFX9: ; %bb.0:
795 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
796 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
797 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
798 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
799 ; SDAG-GFX9-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
800 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
801 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
802 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
803 ; SDAG-GFX9-NEXT: s_endpgm
804 ;
805 ; GISEL-VI-LABEL: v_icmp_i64_ne:
806 ; GISEL-VI: ; %bb.0:
807 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
808 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
809 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
810 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
811 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
812 ; GISEL-VI-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
813 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
814 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
815 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
816 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
817 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
818 ; GISEL-VI-NEXT: s_endpgm
819 ;
820 ; GISEL-GFX9-LABEL: v_icmp_i64_ne:
821 ; GISEL-GFX9: ; %bb.0:
822 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
823 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
824 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
825 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
826 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
827 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
828 ; GISEL-GFX9-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
829 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
830 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
831 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
832 ; GISEL-GFX9-NEXT: s_endpgm
833 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 33)
834 store i64 %result, ptr addrspace(1) %out
835 ret void
836 }
838 define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
839 ; GFX11-LABEL: v_icmp_u64_ugt:
840 ; GFX11: ; %bb.0:
841 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
842 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
843 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
844 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
845 ; GFX11-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], s[4:5]
846 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
847 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
848 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
849 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
850 ; GFX11-NEXT: s_nop 0
851 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
852 ; GFX11-NEXT: s_endpgm
853 ;
854 ; SDAG-VI-LABEL: v_icmp_u64_ugt:
855 ; SDAG-VI: ; %bb.0:
856 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
857 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
858 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
859 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
860 ; SDAG-VI-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
861 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
862 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
863 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
864 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
865 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
866 ; SDAG-VI-NEXT: s_endpgm
867 ;
868 ; SDAG-GFX9-LABEL: v_icmp_u64_ugt:
869 ; SDAG-GFX9: ; %bb.0:
870 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
871 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
872 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
873 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
874 ; SDAG-GFX9-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
875 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
876 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
877 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
878 ; SDAG-GFX9-NEXT: s_endpgm
879 ;
880 ; GISEL-VI-LABEL: v_icmp_u64_ugt:
881 ; GISEL-VI: ; %bb.0:
882 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
883 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
884 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
885 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
886 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
887 ; GISEL-VI-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
888 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
889 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
890 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
891 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
892 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
893 ; GISEL-VI-NEXT: s_endpgm
894 ;
895 ; GISEL-GFX9-LABEL: v_icmp_u64_ugt:
896 ; GISEL-GFX9: ; %bb.0:
897 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
898 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
899 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
900 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
901 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
902 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
903 ; GISEL-GFX9-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
904 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
905 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
906 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
907 ; GISEL-GFX9-NEXT: s_endpgm
908 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 34)
909 store i64 %result, ptr addrspace(1) %out
910 ret void
911 }
913 define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
914 ; GFX11-LABEL: v_icmp_u64_uge:
915 ; GFX11: ; %bb.0:
916 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
917 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
918 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
919 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
920 ; GFX11-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], s[4:5]
921 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
922 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
923 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
924 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
925 ; GFX11-NEXT: s_nop 0
926 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
927 ; GFX11-NEXT: s_endpgm
928 ;
929 ; SDAG-VI-LABEL: v_icmp_u64_uge:
930 ; SDAG-VI: ; %bb.0:
931 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
932 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
933 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
934 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
935 ; SDAG-VI-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
936 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
937 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
938 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
939 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
940 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
941 ; SDAG-VI-NEXT: s_endpgm
942 ;
943 ; SDAG-GFX9-LABEL: v_icmp_u64_uge:
944 ; SDAG-GFX9: ; %bb.0:
945 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
946 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
947 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
948 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
949 ; SDAG-GFX9-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
950 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
951 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
952 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
953 ; SDAG-GFX9-NEXT: s_endpgm
954 ;
955 ; GISEL-VI-LABEL: v_icmp_u64_uge:
956 ; GISEL-VI: ; %bb.0:
957 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
958 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
959 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
960 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
961 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
962 ; GISEL-VI-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
963 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
964 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
965 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
966 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
967 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
968 ; GISEL-VI-NEXT: s_endpgm
969 ;
970 ; GISEL-GFX9-LABEL: v_icmp_u64_uge:
971 ; GISEL-GFX9: ; %bb.0:
972 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
973 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
974 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
975 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
976 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
977 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
978 ; GISEL-GFX9-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
979 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
980 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
981 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
982 ; GISEL-GFX9-NEXT: s_endpgm
983 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 35)
984 store i64 %result, ptr addrspace(1) %out
985 ret void
986 }
988 define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
989 ; GFX11-LABEL: v_icmp_u64_ult:
990 ; GFX11: ; %bb.0:
991 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
992 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
993 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
994 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
995 ; GFX11-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], s[4:5]
996 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
997 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
998 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
999 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1000 ; GFX11-NEXT: s_nop 0
1001 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1002 ; GFX11-NEXT: s_endpgm
1003 ;
1004 ; SDAG-VI-LABEL: v_icmp_u64_ult:
1005 ; SDAG-VI: ; %bb.0:
1006 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1007 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1008 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1009 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1010 ; SDAG-VI-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
1011 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1012 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1013 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1014 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1015 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1016 ; SDAG-VI-NEXT: s_endpgm
1017 ;
1018 ; SDAG-GFX9-LABEL: v_icmp_u64_ult:
1019 ; SDAG-GFX9: ; %bb.0:
1020 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1021 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1022 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1023 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1024 ; SDAG-GFX9-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
1025 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1026 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1027 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1028 ; SDAG-GFX9-NEXT: s_endpgm
1029 ;
1030 ; GISEL-VI-LABEL: v_icmp_u64_ult:
1031 ; GISEL-VI: ; %bb.0:
1032 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1033 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1034 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1035 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1036 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1037 ; GISEL-VI-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
1038 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1039 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1040 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1041 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1042 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1043 ; GISEL-VI-NEXT: s_endpgm
1044 ;
1045 ; GISEL-GFX9-LABEL: v_icmp_u64_ult:
1046 ; GISEL-GFX9: ; %bb.0:
1047 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1048 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1049 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1050 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1051 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1052 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1053 ; GISEL-GFX9-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
1054 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1055 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1056 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1057 ; GISEL-GFX9-NEXT: s_endpgm
1058 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 36)
1059 store i64 %result, ptr addrspace(1) %out
1060 ret void
1061 }
1063 define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
1064 ; GFX11-LABEL: v_icmp_u64_ule:
1065 ; GFX11: ; %bb.0:
1066 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1067 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1068 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1069 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1070 ; GFX11-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], s[4:5]
1071 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1072 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1073 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1074 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1075 ; GFX11-NEXT: s_nop 0
1076 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1077 ; GFX11-NEXT: s_endpgm
1078 ;
1079 ; SDAG-VI-LABEL: v_icmp_u64_ule:
1080 ; SDAG-VI: ; %bb.0:
1081 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1082 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1083 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1084 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1085 ; SDAG-VI-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
1086 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1087 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1088 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1089 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1090 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1091 ; SDAG-VI-NEXT: s_endpgm
1092 ;
1093 ; SDAG-GFX9-LABEL: v_icmp_u64_ule:
1094 ; SDAG-GFX9: ; %bb.0:
1095 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1096 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1097 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1098 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1099 ; SDAG-GFX9-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
1100 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1101 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1102 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1103 ; SDAG-GFX9-NEXT: s_endpgm
1104 ;
1105 ; GISEL-VI-LABEL: v_icmp_u64_ule:
1106 ; GISEL-VI: ; %bb.0:
1107 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1108 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1109 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1110 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1111 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1112 ; GISEL-VI-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
1113 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1114 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1115 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1116 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1117 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1118 ; GISEL-VI-NEXT: s_endpgm
1119 ;
1120 ; GISEL-GFX9-LABEL: v_icmp_u64_ule:
1121 ; GISEL-GFX9: ; %bb.0:
1122 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1123 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1124 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1125 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1126 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1127 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1128 ; GISEL-GFX9-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
1129 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1130 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1131 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1132 ; GISEL-GFX9-NEXT: s_endpgm
1133 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 37)
1134 store i64 %result, ptr addrspace(1) %out
1135 ret void
1136 }
1138 define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
1139 ; GFX11-LABEL: v_icmp_i64_sgt:
1140 ; GFX11: ; %bb.0:
1141 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1142 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1143 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1144 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1145 ; GFX11-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], s[4:5]
1146 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1147 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1148 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1149 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1150 ; GFX11-NEXT: s_nop 0
1151 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1152 ; GFX11-NEXT: s_endpgm
1153 ;
1154 ; SDAG-VI-LABEL: v_icmp_i64_sgt:
1155 ; SDAG-VI: ; %bb.0:
1156 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1157 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1158 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1159 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1160 ; SDAG-VI-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
1161 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1162 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1163 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1164 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1165 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1166 ; SDAG-VI-NEXT: s_endpgm
1167 ;
1168 ; SDAG-GFX9-LABEL: v_icmp_i64_sgt:
1169 ; SDAG-GFX9: ; %bb.0:
1170 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1171 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1172 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1173 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1174 ; SDAG-GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
1175 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1176 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1177 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1178 ; SDAG-GFX9-NEXT: s_endpgm
1179 ;
1180 ; GISEL-VI-LABEL: v_icmp_i64_sgt:
1181 ; GISEL-VI: ; %bb.0:
1182 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1183 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1184 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1185 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1186 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1187 ; GISEL-VI-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
1188 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1189 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1190 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1191 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1192 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1193 ; GISEL-VI-NEXT: s_endpgm
1194 ;
1195 ; GISEL-GFX9-LABEL: v_icmp_i64_sgt:
1196 ; GISEL-GFX9: ; %bb.0:
1197 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1198 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1199 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1200 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1201 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1202 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1203 ; GISEL-GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
1204 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1205 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1206 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1207 ; GISEL-GFX9-NEXT: s_endpgm
1208 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 38)
1209 store i64 %result, ptr addrspace(1) %out
1210 ret void
1211 }
1213 define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
1214 ; GFX11-LABEL: v_icmp_i64_sge:
1215 ; GFX11: ; %bb.0:
1216 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1217 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1218 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1219 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1220 ; GFX11-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], s[4:5]
1221 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1222 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1223 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1224 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1225 ; GFX11-NEXT: s_nop 0
1226 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1227 ; GFX11-NEXT: s_endpgm
1228 ;
1229 ; SDAG-VI-LABEL: v_icmp_i64_sge:
1230 ; SDAG-VI: ; %bb.0:
1231 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1232 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1233 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1234 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1235 ; SDAG-VI-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
1236 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1237 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1238 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1239 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1240 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1241 ; SDAG-VI-NEXT: s_endpgm
1242 ;
1243 ; SDAG-GFX9-LABEL: v_icmp_i64_sge:
1244 ; SDAG-GFX9: ; %bb.0:
1245 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1246 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1247 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1248 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1249 ; SDAG-GFX9-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
1250 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1251 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1252 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1253 ; SDAG-GFX9-NEXT: s_endpgm
1254 ;
1255 ; GISEL-VI-LABEL: v_icmp_i64_sge:
1256 ; GISEL-VI: ; %bb.0:
1257 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1258 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1259 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1260 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1261 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1262 ; GISEL-VI-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
1263 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1264 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1265 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1266 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1267 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1268 ; GISEL-VI-NEXT: s_endpgm
1269 ;
1270 ; GISEL-GFX9-LABEL: v_icmp_i64_sge:
1271 ; GISEL-GFX9: ; %bb.0:
1272 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1273 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1274 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1275 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1276 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1277 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1278 ; GISEL-GFX9-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
1279 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1280 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1281 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1282 ; GISEL-GFX9-NEXT: s_endpgm
1283 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 39)
1284 store i64 %result, ptr addrspace(1) %out
1285 ret void
1286 }
1288 define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
1289 ; GFX11-LABEL: v_icmp_i64_slt:
1290 ; GFX11: ; %bb.0:
1291 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1292 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1293 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1294 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1295 ; GFX11-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], s[4:5]
1296 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1297 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1298 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1299 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1300 ; GFX11-NEXT: s_nop 0
1301 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1302 ; GFX11-NEXT: s_endpgm
1303 ;
1304 ; SDAG-VI-LABEL: v_icmp_i64_slt:
1305 ; SDAG-VI: ; %bb.0:
1306 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1307 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1308 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1309 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1310 ; SDAG-VI-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
1311 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1312 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1313 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1314 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1315 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1316 ; SDAG-VI-NEXT: s_endpgm
1317 ;
1318 ; SDAG-GFX9-LABEL: v_icmp_i64_slt:
1319 ; SDAG-GFX9: ; %bb.0:
1320 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1321 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1322 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1323 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1324 ; SDAG-GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
1325 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1326 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1327 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1328 ; SDAG-GFX9-NEXT: s_endpgm
1329 ;
1330 ; GISEL-VI-LABEL: v_icmp_i64_slt:
1331 ; GISEL-VI: ; %bb.0:
1332 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1333 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1334 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1335 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1336 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1337 ; GISEL-VI-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
1338 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1339 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1340 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1341 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1342 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1343 ; GISEL-VI-NEXT: s_endpgm
1344 ;
1345 ; GISEL-GFX9-LABEL: v_icmp_i64_slt:
1346 ; GISEL-GFX9: ; %bb.0:
1347 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1348 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1349 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1350 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1351 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1352 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1353 ; GISEL-GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
1354 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1355 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1356 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1357 ; GISEL-GFX9-NEXT: s_endpgm
1358 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 40)
1359 store i64 %result, ptr addrspace(1) %out
1360 ret void
1361 }
1363 define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
1364 ; GFX11-LABEL: v_icmp_i64_sle:
1365 ; GFX11: ; %bb.0:
1366 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1367 ; GFX11-NEXT: s_mov_b64 s[4:5], 0x64
1368 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1369 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1370 ; GFX11-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], s[4:5]
1371 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1372 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1373 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1374 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1375 ; GFX11-NEXT: s_nop 0
1376 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1377 ; GFX11-NEXT: s_endpgm
1378 ;
1379 ; SDAG-VI-LABEL: v_icmp_i64_sle:
1380 ; SDAG-VI: ; %bb.0:
1381 ; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1382 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1383 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
1384 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1385 ; SDAG-VI-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
1386 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
1387 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
1388 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
1389 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
1390 ; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1391 ; SDAG-VI-NEXT: s_endpgm
1392 ;
1393 ; SDAG-GFX9-LABEL: v_icmp_i64_sle:
1394 ; SDAG-GFX9: ; %bb.0:
1395 ; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1396 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0
1397 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1398 ; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1399 ; SDAG-GFX9-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
1400 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s2
1401 ; SDAG-GFX9-NEXT: v_mov_b32_e32 v3, s3
1402 ; SDAG-GFX9-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
1403 ; SDAG-GFX9-NEXT: s_endpgm
1404 ;
1405 ; GISEL-VI-LABEL: v_icmp_i64_sle:
1406 ; GISEL-VI: ; %bb.0:
1407 ; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1408 ; GISEL-VI-NEXT: s_mov_b64 s[4:5], 0x64
1409 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4
1410 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5
1411 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1412 ; GISEL-VI-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
1413 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1414 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1415 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1416 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1417 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1418 ; GISEL-VI-NEXT: s_endpgm
1419 ;
1420 ; GISEL-GFX9-LABEL: v_icmp_i64_sle:
1421 ; GISEL-GFX9: ; %bb.0:
1422 ; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1423 ; GISEL-GFX9-NEXT: s_mov_b64 s[4:5], 0x64
1424 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4
1425 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5
1426 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
1427 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1428 ; GISEL-GFX9-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
1429 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
1430 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
1431 ; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
1432 ; GISEL-GFX9-NEXT: s_endpgm
1433 %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 41)
1434 store i64 %result, ptr addrspace(1) %out
1435 ret void
1436 }
1438 define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
1439 ; GFX11-LABEL: v_icmp_i16_eq:
1440 ; GFX11: ; %bb.0:
1441 ; GFX11-NEXT: s_clause 0x1
1442 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1443 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1444 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1445 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1446 ; GFX11-NEXT: v_cmp_eq_u16_e64 s[2:3], 0x64, s2
1447 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1448 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1449 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1450 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1451 ; GFX11-NEXT: s_nop 0
1452 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1453 ; GFX11-NEXT: s_endpgm
1454 ;
1455 ; SDAG-VI-LABEL: v_icmp_i16_eq:
1456 ; SDAG-VI: ; %bb.0:
1457 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1458 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1459 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1460 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1461 ; SDAG-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
1462 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1463 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1464 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1465 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1466 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1467 ; SDAG-VI-NEXT: s_endpgm
1468 ;
1469 ; GFX9-LABEL: v_icmp_i16_eq:
1470 ; GFX9: ; %bb.0:
1471 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1472 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1473 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1474 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1475 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1476 ; GFX9-NEXT: v_cmp_eq_u16_e64 s[0:1], s4, v0
1477 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1478 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1479 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1480 ; GFX9-NEXT: s_endpgm
1481 ;
1482 ; GISEL-VI-LABEL: v_icmp_i16_eq:
1483 ; GISEL-VI: ; %bb.0:
1484 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1485 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1486 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1487 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1488 ; GISEL-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
1489 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1490 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1491 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1492 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1493 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1494 ; GISEL-VI-NEXT: s_endpgm
1495 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 32)
1496 store i64 %result, ptr addrspace(1) %out
1497 ret void
1498 }
1500 define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
1501 ; SDAG-GFX11-LABEL: v_icmp_i16:
1502 ; SDAG-GFX11: ; %bb.0:
1503 ; SDAG-GFX11-NEXT: s_endpgm
1504 ;
1505 ; SDAG-VI-LABEL: v_icmp_i16:
1506 ; SDAG-VI: ; %bb.0:
1507 ; SDAG-VI-NEXT: s_endpgm
1508 ;
1509 ; SDAG-GFX9-LABEL: v_icmp_i16:
1510 ; SDAG-GFX9: ; %bb.0:
1511 ; SDAG-GFX9-NEXT: s_endpgm
1512 ;
1513 ; GISEL-GFX11-LABEL: v_icmp_i16:
1514 ; GISEL-GFX11: ; %bb.0:
1515 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1516 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
1517 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1518 ; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]
1519 ; GISEL-GFX11-NEXT: s_nop 0
1520 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1521 ; GISEL-GFX11-NEXT: s_endpgm
1522 ;
1523 ; GISEL-VI-LABEL: v_icmp_i16:
1524 ; GISEL-VI: ; %bb.0:
1525 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1526 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1527 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
1528 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
1529 ; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
1530 ; GISEL-VI-NEXT: s_endpgm
1531 ;
1532 ; GISEL-GFX9-LABEL: v_icmp_i16:
1533 ; GISEL-GFX9: ; %bb.0:
1534 ; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1535 ; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0
1536 ; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
1537 ; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
1538 ; GISEL-GFX9-NEXT: s_endpgm
1539 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 30)
1540 store i64 %result, ptr addrspace(1) %out
1541 ret void
1542 }
1544 define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
1545 ; GFX11-LABEL: v_icmp_i16_ne:
1546 ; GFX11: ; %bb.0:
1547 ; GFX11-NEXT: s_clause 0x1
1548 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1549 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1550 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1551 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1552 ; GFX11-NEXT: v_cmp_ne_u16_e64 s[2:3], 0x64, s2
1553 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1554 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1555 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1556 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1557 ; GFX11-NEXT: s_nop 0
1558 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1559 ; GFX11-NEXT: s_endpgm
1560 ;
1561 ; SDAG-VI-LABEL: v_icmp_i16_ne:
1562 ; SDAG-VI: ; %bb.0:
1563 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1564 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1565 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1566 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1567 ; SDAG-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
1568 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1569 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1570 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1571 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1572 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1573 ; SDAG-VI-NEXT: s_endpgm
1574 ;
1575 ; GFX9-LABEL: v_icmp_i16_ne:
1576 ; GFX9: ; %bb.0:
1577 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1578 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1579 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1580 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1581 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1582 ; GFX9-NEXT: v_cmp_ne_u16_e64 s[0:1], s4, v0
1583 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1584 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1585 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1586 ; GFX9-NEXT: s_endpgm
1587 ;
1588 ; GISEL-VI-LABEL: v_icmp_i16_ne:
1589 ; GISEL-VI: ; %bb.0:
1590 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1591 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1592 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1593 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1594 ; GISEL-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
1595 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1596 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1597 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1598 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1599 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1600 ; GISEL-VI-NEXT: s_endpgm
1601 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 33)
1602 store i64 %result, ptr addrspace(1) %out
1603 ret void
1604 }
1606 define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
1607 ; GFX11-LABEL: v_icmp_i16_ugt:
1608 ; GFX11: ; %bb.0:
1609 ; GFX11-NEXT: s_clause 0x1
1610 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1611 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1612 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1613 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1614 ; GFX11-NEXT: v_cmp_lt_u16_e64 s[2:3], 0x64, s2
1615 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1616 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1617 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1618 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1619 ; GFX11-NEXT: s_nop 0
1620 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1621 ; GFX11-NEXT: s_endpgm
1622 ;
1623 ; SDAG-VI-LABEL: v_icmp_i16_ugt:
1624 ; SDAG-VI: ; %bb.0:
1625 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1626 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1627 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1628 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1629 ; SDAG-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
1630 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1631 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1632 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1633 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1634 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1635 ; SDAG-VI-NEXT: s_endpgm
1636 ;
1637 ; GFX9-LABEL: v_icmp_i16_ugt:
1638 ; GFX9: ; %bb.0:
1639 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1640 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1641 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1642 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1643 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1644 ; GFX9-NEXT: v_cmp_gt_u16_e64 s[0:1], s4, v0
1645 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1646 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1647 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1648 ; GFX9-NEXT: s_endpgm
1649 ;
1650 ; GISEL-VI-LABEL: v_icmp_i16_ugt:
1651 ; GISEL-VI: ; %bb.0:
1652 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1653 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1654 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1655 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1656 ; GISEL-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
1657 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1658 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1659 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1660 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1661 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1662 ; GISEL-VI-NEXT: s_endpgm
1663 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 34)
1664 store i64 %result, ptr addrspace(1) %out
1665 ret void
1666 }
1668 define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
1669 ; GFX11-LABEL: v_icmp_i16_uge:
1670 ; GFX11: ; %bb.0:
1671 ; GFX11-NEXT: s_clause 0x1
1672 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1673 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1674 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1675 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1676 ; GFX11-NEXT: v_cmp_le_u16_e64 s[2:3], 0x64, s2
1677 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1678 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1679 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1680 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1681 ; GFX11-NEXT: s_nop 0
1682 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1683 ; GFX11-NEXT: s_endpgm
1684 ;
1685 ; SDAG-VI-LABEL: v_icmp_i16_uge:
1686 ; SDAG-VI: ; %bb.0:
1687 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1688 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1689 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1690 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1691 ; SDAG-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
1692 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1693 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1694 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1695 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1696 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1697 ; SDAG-VI-NEXT: s_endpgm
1698 ;
1699 ; GFX9-LABEL: v_icmp_i16_uge:
1700 ; GFX9: ; %bb.0:
1701 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1702 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1703 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1704 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1705 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1706 ; GFX9-NEXT: v_cmp_ge_u16_e64 s[0:1], s4, v0
1707 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1708 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1709 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1710 ; GFX9-NEXT: s_endpgm
1711 ;
1712 ; GISEL-VI-LABEL: v_icmp_i16_uge:
1713 ; GISEL-VI: ; %bb.0:
1714 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1715 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1716 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1717 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1718 ; GISEL-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
1719 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1720 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1721 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1722 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1723 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1724 ; GISEL-VI-NEXT: s_endpgm
1725 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 35)
1726 store i64 %result, ptr addrspace(1) %out
1727 ret void
1728 }
1730 define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
1731 ; GFX11-LABEL: v_icmp_i16_ult:
1732 ; GFX11: ; %bb.0:
1733 ; GFX11-NEXT: s_clause 0x1
1734 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1735 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1736 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1737 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1738 ; GFX11-NEXT: v_cmp_gt_u16_e64 s[2:3], 0x64, s2
1739 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1740 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1741 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1742 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1743 ; GFX11-NEXT: s_nop 0
1744 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1745 ; GFX11-NEXT: s_endpgm
1746 ;
1747 ; SDAG-VI-LABEL: v_icmp_i16_ult:
1748 ; SDAG-VI: ; %bb.0:
1749 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1750 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1751 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1752 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1753 ; SDAG-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
1754 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1755 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1756 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1757 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1758 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1759 ; SDAG-VI-NEXT: s_endpgm
1760 ;
1761 ; GFX9-LABEL: v_icmp_i16_ult:
1762 ; GFX9: ; %bb.0:
1763 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1764 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1765 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1766 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1767 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1768 ; GFX9-NEXT: v_cmp_lt_u16_e64 s[0:1], s4, v0
1769 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1770 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1771 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1772 ; GFX9-NEXT: s_endpgm
1773 ;
1774 ; GISEL-VI-LABEL: v_icmp_i16_ult:
1775 ; GISEL-VI: ; %bb.0:
1776 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1777 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1778 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1779 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1780 ; GISEL-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
1781 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1782 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1783 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1784 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1785 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1786 ; GISEL-VI-NEXT: s_endpgm
1787 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 36)
1788 store i64 %result, ptr addrspace(1) %out
1789 ret void
1790 }
1792 define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
1793 ; GFX11-LABEL: v_icmp_i16_ule:
1794 ; GFX11: ; %bb.0:
1795 ; GFX11-NEXT: s_clause 0x1
1796 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1797 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1798 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1799 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1800 ; GFX11-NEXT: v_cmp_ge_u16_e64 s[2:3], 0x64, s2
1801 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1802 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1803 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1804 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1805 ; GFX11-NEXT: s_nop 0
1806 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1807 ; GFX11-NEXT: s_endpgm
1808 ;
1809 ; SDAG-VI-LABEL: v_icmp_i16_ule:
1810 ; SDAG-VI: ; %bb.0:
1811 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1812 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1813 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1814 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1815 ; SDAG-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
1816 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1817 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1818 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1819 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1820 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1821 ; SDAG-VI-NEXT: s_endpgm
1822 ;
1823 ; GFX9-LABEL: v_icmp_i16_ule:
1824 ; GFX9: ; %bb.0:
1825 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1826 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1827 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1828 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1829 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1830 ; GFX9-NEXT: v_cmp_le_u16_e64 s[0:1], s4, v0
1831 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1832 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1833 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1834 ; GFX9-NEXT: s_endpgm
1835 ;
1836 ; GISEL-VI-LABEL: v_icmp_i16_ule:
1837 ; GISEL-VI: ; %bb.0:
1838 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1839 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1840 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1841 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1842 ; GISEL-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
1843 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1844 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1845 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1846 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1847 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1848 ; GISEL-VI-NEXT: s_endpgm
1849 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 37)
1850 store i64 %result, ptr addrspace(1) %out
1851 ret void
1852 }
1854 define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
1855 ; GFX11-LABEL: v_icmp_i16_sgt:
1856 ; GFX11: ; %bb.0:
1857 ; GFX11-NEXT: s_clause 0x1
1858 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1859 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1860 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1861 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1862 ; GFX11-NEXT: v_cmp_lt_i16_e64 s[2:3], 0x64, s2
1863 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1864 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1865 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1866 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1867 ; GFX11-NEXT: s_nop 0
1868 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1869 ; GFX11-NEXT: s_endpgm
1870 ;
1871 ; SDAG-VI-LABEL: v_icmp_i16_sgt:
1872 ; SDAG-VI: ; %bb.0:
1873 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1874 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1875 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1876 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1877 ; SDAG-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
1878 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1879 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1880 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1881 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1882 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1883 ; SDAG-VI-NEXT: s_endpgm
1884 ;
1885 ; GFX9-LABEL: v_icmp_i16_sgt:
1886 ; GFX9: ; %bb.0:
1887 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1888 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1889 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1890 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1891 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1892 ; GFX9-NEXT: v_cmp_gt_i16_e64 s[0:1], s4, v0
1893 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1894 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1895 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1896 ; GFX9-NEXT: s_endpgm
1897 ;
1898 ; GISEL-VI-LABEL: v_icmp_i16_sgt:
1899 ; GISEL-VI: ; %bb.0:
1900 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1901 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1902 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1903 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1904 ; GISEL-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
1905 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1906 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1907 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1908 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1909 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1910 ; GISEL-VI-NEXT: s_endpgm
1911 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 38)
1912 store i64 %result, ptr addrspace(1) %out
1913 ret void
1914 }
1916 define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
1917 ; GFX11-LABEL: v_icmp_i16_sge:
1918 ; GFX11: ; %bb.0:
1919 ; GFX11-NEXT: s_clause 0x1
1920 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1921 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1922 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1923 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1924 ; GFX11-NEXT: v_cmp_le_i16_e64 s[2:3], 0x64, s2
1925 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1926 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1927 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1928 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1929 ; GFX11-NEXT: s_nop 0
1930 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1931 ; GFX11-NEXT: s_endpgm
1932 ;
1933 ; SDAG-VI-LABEL: v_icmp_i16_sge:
1934 ; SDAG-VI: ; %bb.0:
1935 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1936 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1937 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
1938 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
1939 ; SDAG-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
1940 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
1941 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
1942 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
1943 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
1944 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
1945 ; SDAG-VI-NEXT: s_endpgm
1946 ;
1947 ; GFX9-LABEL: v_icmp_i16_sge:
1948 ; GFX9: ; %bb.0:
1949 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
1950 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1951 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
1952 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
1953 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
1954 ; GFX9-NEXT: v_cmp_ge_i16_e64 s[0:1], s4, v0
1955 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
1956 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
1957 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
1958 ; GFX9-NEXT: s_endpgm
1959 ;
1960 ; GISEL-VI-LABEL: v_icmp_i16_sge:
1961 ; GISEL-VI: ; %bb.0:
1962 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1963 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1964 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
1965 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
1966 ; GISEL-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
1967 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
1968 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
1969 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
1970 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
1971 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1972 ; GISEL-VI-NEXT: s_endpgm
1973 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 39)
1974 store i64 %result, ptr addrspace(1) %out
1975 ret void
1976 }
1978 define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
1979 ; GFX11-LABEL: v_icmp_i16_slt:
1980 ; GFX11: ; %bb.0:
1981 ; GFX11-NEXT: s_clause 0x1
1982 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1983 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1984 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
1985 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1986 ; GFX11-NEXT: v_cmp_gt_i16_e64 s[2:3], 0x64, s2
1987 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
1988 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
1989 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
1990 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
1991 ; GFX11-NEXT: s_nop 0
1992 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1993 ; GFX11-NEXT: s_endpgm
1994 ;
1995 ; SDAG-VI-LABEL: v_icmp_i16_slt:
1996 ; SDAG-VI: ; %bb.0:
1997 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
1998 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1999 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
2000 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
2001 ; SDAG-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
2002 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
2003 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
2004 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
2005 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
2006 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
2007 ; SDAG-VI-NEXT: s_endpgm
2008 ;
2009 ; GFX9-LABEL: v_icmp_i16_slt:
2010 ; GFX9: ; %bb.0:
2011 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
2012 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
2013 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
2014 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
2015 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
2016 ; GFX9-NEXT: v_cmp_lt_i16_e64 s[0:1], s4, v0
2017 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
2018 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
2019 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
2020 ; GFX9-NEXT: s_endpgm
2021 ;
2022 ; GISEL-VI-LABEL: v_icmp_i16_slt:
2023 ; GISEL-VI: ; %bb.0:
2024 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
2025 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
2026 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
2027 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
2028 ; GISEL-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
2029 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
2030 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
2031 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
2032 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
2033 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
2034 ; GISEL-VI-NEXT: s_endpgm
2035 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 40)
2036 store i64 %result, ptr addrspace(1) %out
2037 ret void
2038 }
2040 define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
2041 ; GFX11-LABEL: v_icmp_i16_sle:
2042 ; GFX11: ; %bb.0:
2043 ; GFX11-NEXT: s_clause 0x1
2044 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
2045 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
2046 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
2047 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
2048 ; GFX11-NEXT: v_cmp_ge_i16_e64 s[2:3], 0x64, s2
2049 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
2050 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
2051 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
2052 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
2053 ; GFX11-NEXT: s_nop 0
2054 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2055 ; GFX11-NEXT: s_endpgm
2056 ;
2057 ; SDAG-VI-LABEL: v_icmp_i16_sle:
2058 ; SDAG-VI: ; %bb.0:
2059 ; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
2060 ; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
2061 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
2062 ; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
2063 ; SDAG-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
2064 ; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
2065 ; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
2066 ; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
2067 ; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
2068 ; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
2069 ; SDAG-VI-NEXT: s_endpgm
2070 ;
2071 ; GFX9-LABEL: v_icmp_i16_sle:
2072 ; GFX9: ; %bb.0:
2073 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
2074 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
2075 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
2076 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
2077 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
2078 ; GFX9-NEXT: v_cmp_le_i16_e64 s[0:1], s4, v0
2079 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
2080 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
2081 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
2082 ; GFX9-NEXT: s_endpgm
2083 ;
2084 ; GISEL-VI-LABEL: v_icmp_i16_sle:
2085 ; GISEL-VI: ; %bb.0:
2086 ; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c
2087 ; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
2088 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
2089 ; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
2090 ; GISEL-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
2091 ; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
2092 ; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
2093 ; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
2094 ; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
2095 ; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
2096 ; GISEL-VI-NEXT: s_endpgm
2097 %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
2098 store i64 %result, ptr addrspace(1) %out
2099 ret void
2100 }
2102 define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b) {
2103 ; GFX11-LABEL: v_icmp_i1_ne0:
2104 ; GFX11: ; %bb.0:
2105 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
2106 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
2107 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
2108 ; GFX11-NEXT: s_cmp_gt_u32 s2, 1
2109 ; GFX11-NEXT: s_cselect_b64 s[4:5], -1, 0
2110 ; GFX11-NEXT: s_cmp_gt_u32 s3, 2
2111 ; GFX11-NEXT: s_cselect_b64 s[2:3], -1, 0
2112 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
2113 ; GFX11-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
2114 ; GFX11-NEXT: v_mov_b32_e32 v0, s2
2115 ; GFX11-NEXT: v_mov_b32_e32 v1, s3
2116 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
2117 ; GFX11-NEXT: s_nop 0
2118 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2119 ; GFX11-NEXT: s_endpgm
2120 ;
2121 ; VI-LABEL: v_icmp_i1_ne0:
2122 ; VI: ; %bb.0:
2123 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
2124 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2125 ; VI-NEXT: s_cmp_gt_u32 s2, 1
2126 ; VI-NEXT: s_cselect_b64 s[4:5], -1, 0
2127 ; VI-NEXT: s_cmp_gt_u32 s3, 2
2128 ; VI-NEXT: s_cselect_b64 s[2:3], -1, 0
2129 ; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
2130 ; VI-NEXT: v_mov_b32_e32 v0, s0
2131 ; VI-NEXT: v_mov_b32_e32 v2, s2
2132 ; VI-NEXT: v_mov_b32_e32 v1, s1
2133 ; VI-NEXT: v_mov_b32_e32 v3, s3
2134 ; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
2135 ; VI-NEXT: s_endpgm
2136 ;
2137 ; GFX9-LABEL: v_icmp_i1_ne0:
2138 ; GFX9: ; %bb.0:
2139 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
2140 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
2141 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
2142 ; GFX9-NEXT: s_cmp_gt_u32 s2, 1
2143 ; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
2144 ; GFX9-NEXT: s_cmp_gt_u32 s3, 2
2145 ; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0
2146 ; GFX9-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
2147 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
2148 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
2149 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
2150 ; GFX9-NEXT: s_endpgm
2151 %c0 = icmp ugt i32 %a, 1
2152 %c1 = icmp ugt i32 %b, 2
2153 %src = and i1 %c0, %c1
2154 %result = call i64 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
2155 store i64 %result, ptr addrspace(1) %out
2156 ret void
2157 }
2159 define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(ptr addrspace(1) %out, i32 %src) {
2160 ; SDAG-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
2161 ; SDAG-GFX11: ; %bb.0:
2162 ; SDAG-GFX11-NEXT: s_endpgm
2163 ;
2164 ; SDAG-VI-LABEL: test_intr_icmp_i32_invalid_cc:
2165 ; SDAG-VI: ; %bb.0:
2166 ; SDAG-VI-NEXT: s_endpgm
2167 ;
2168 ; SDAG-GFX9-LABEL: test_intr_icmp_i32_invalid_cc:
2169 ; SDAG-GFX9: ; %bb.0:
2170 ; SDAG-GFX9-NEXT: s_endpgm
2171 ;
2172 ; GISEL-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
2173 ; GISEL-GFX11: ; %bb.0:
2174 ; GISEL-GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
2175 ; GISEL-GFX11-NEXT: s_nop 0
2176 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
2177 ; GISEL-GFX11-NEXT: s_endpgm
2178 ;
2179 ; GISEL-VI-LABEL: test_intr_icmp_i32_invalid_cc:
2180 ; GISEL-VI: ; %bb.0:
2181 ; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
2182 ; GISEL-VI-NEXT: s_endpgm
2183 ;
2184 ; GISEL-GFX9-LABEL: test_intr_icmp_i32_invalid_cc:
2185 ; GISEL-GFX9: ; %bb.0:
2186 ; GISEL-GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
2187 ; GISEL-GFX9-NEXT: s_endpgm
2188 %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 9999)
2189 store i64 %result, ptr addrspace(1) %out
2190 ret void
2191 }
2193 attributes #0 = { nounwind readnone convergent }
2194 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2195 ; GCN: {{.*}}