[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / CodeGen / AMDGPU / peephole-fold-imm.mir
blob099aaa449b1c9e4261dffb50025a8bccf225cea5
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck -check-prefix=GCN %s
4 ---
5 name:            fold_simm_virtual
6 body:             |
7   bb.0:
9     ; GCN-LABEL: name: fold_simm_virtual
10     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
11     ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
12     ; GCN-NEXT: SI_RETURN_TO_EPILOG
13     %0:sreg_32 = S_MOV_B32 0
14     %1:sreg_32 = COPY killed %0
15     SI_RETURN_TO_EPILOG
17 ...
19 ---
20 name:            fold_simm_physical
21 body:             |
22   bb.0:
24     ; GCN-LABEL: name: fold_simm_physical
25     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
26     ; GCN-NEXT: $sgpr1 = S_MOV_B32 0
27     ; GCN-NEXT: SI_RETURN_TO_EPILOG
28     %0:sreg_32 = S_MOV_B32 0
29     $sgpr1 = COPY killed %0
30     SI_RETURN_TO_EPILOG
32 ...
34 ---
35 name:            dont_fold_simm_scc
36 body:             |
37   bb.0:
39     ; GCN-LABEL: name: dont_fold_simm_scc
40     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
41     ; GCN-NEXT: $scc = COPY killed [[S_MOV_B32_]]
42     ; GCN-NEXT: SI_RETURN_TO_EPILOG
43     %0:sreg_32 = S_MOV_B32 0
44     $scc = COPY killed %0
45     SI_RETURN_TO_EPILOG
47 ...
49 ---
50 name:            fold_simm_16_sub_to_lo
51 body:             |
52   bb.0:
54     ; GCN-LABEL: name: fold_simm_16_sub_to_lo
55     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
56     ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
57     ; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]
58     %0:sreg_32 = S_MOV_B32 2048
59     %1:sgpr_lo16 = COPY killed %0.lo16
60     SI_RETURN_TO_EPILOG %1
62 ...
64 ---
65 name:            fold_simm_16_sub_to_phys
66 body:             |
67   bb.0:
69     ; GCN-LABEL: name: fold_simm_16_sub_to_phys
70     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
71     ; GCN-NEXT: $sgpr0 = S_MOV_B32 2048
72     ; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
73     %0:sreg_32 = S_MOV_B32 2048
74     $sgpr0_lo16 = COPY killed %0.lo16
75     SI_RETURN_TO_EPILOG $sgpr0_lo16
77 ...
79 ---
80 name:            fold_aimm_16_sub_to_phys
81 body:             |
82   bb.0:
84     ; GCN-LABEL: name: fold_aimm_16_sub_to_phys
85     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
86     ; GCN-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
87     ; GCN-NEXT: SI_RETURN_TO_EPILOG $agpr0_lo16
88     %0:sreg_32 = S_MOV_B32 0
89     $agpr0_lo16 = COPY killed %0.lo16
90     SI_RETURN_TO_EPILOG $agpr0_lo16
92 ...
94 ---
95 name:            fold_vimm_16_sub_to_lo
96 body:             |
97   bb.0:
99     ; GCN-LABEL: name: fold_vimm_16_sub_to_lo
100     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
101     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
102     ; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]
103     %0:sreg_32 = S_MOV_B32 2048
104     %1:vgpr_lo16 = COPY killed %0.lo16
105     SI_RETURN_TO_EPILOG %1
110 name:            fold_vimm_16_sub_to_phys
111 body:             |
112   bb.0:
114     ; GCN-LABEL: name: fold_vimm_16_sub_to_phys
115     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
116     ; GCN-NEXT: $vgpr0_lo16 = COPY killed [[S_MOV_B32_]].lo16
117     ; GCN-NEXT: SI_RETURN_TO_EPILOG $vgpr0_lo16
118     %0:sreg_32 = S_MOV_B32 2048
119     $vgpr0_lo16 = COPY killed %0.lo16
120     SI_RETURN_TO_EPILOG $vgpr0_lo16