llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-lower-sgpr-spills -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
   3
   4 # A simple SGPR spill. Implicit def for lane VGPR should be inserted just before the spill instruction.
   5 ---
   6 name:            sgpr32_spill
   7 tracksRegLiveness: true
   8 frameInfo:
   9   maxAlignment:    4
  10 stack:
  11   - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
  12 machineFunctionInfo:
  13   isEntryFunction: false
  14   scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
  15   stackPtrOffsetReg: '$sgpr32'
  16   frameOffsetReg: '$sgpr33'
  17   hasSpilledSGPRs: true
  18 body:             |
  19   bb.0:
  20     liveins: $sgpr30_sgpr31, $sgpr10
  21     ; GCN-LABEL: name: sgpr32_spill
  22     ; GCN: liveins: $sgpr30_sgpr31, $sgpr10
  23     ; GCN-NEXT: {{  $}}
  24     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  25     ; GCN-NEXT: S_NOP 0
  26     ; GCN-NEXT: [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr10, 0, [[V_WRITELANE_B32_]]
  27     ; GCN-NEXT: $sgpr10 = V_READLANE_B32 [[V_WRITELANE_B32_]], 0
  28     ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr31
  29     S_NOP 0
  30     SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
  31     renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
  32     S_SETPC_B64 $sgpr30_sgpr31
  33 ...
  34
  35 # Needed an additional virtual lane register as the lanes of current register are fully occupied while spilling a wide SGPR tuple.
  36 # There must be two implicit def for the two lane VGPRs.
  37
  38 ---
  39 name:            sgpr_spill_lane_crossover
  40 tracksRegLiveness: true
  41 frameInfo:
  42   maxAlignment:    4
  43 stack:
  44   - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
  45   - { id: 1, type: spill-slot, size: 128, alignment: 4, stack-id: sgpr-spill }
  46 machineFunctionInfo:
  47   isEntryFunction: false
  48   scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
  49   stackPtrOffsetReg: '$sgpr32'
  50   frameOffsetReg: '$sgpr33'
  51   hasSpilledSGPRs: true
  52 body:             |
  53   bb.0:
  54     liveins: $sgpr30_sgpr31, $sgpr10, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
  55     ; GCN-LABEL: name: sgpr_spill_lane_crossover
  56     ; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $vgpr0, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
  57     ; GCN-NEXT: {{  $}}
  58     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  59     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr64, 0, $vgpr0
  60     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr65, 1, $vgpr0
  61     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr66, 2, $vgpr0
  62     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr67, 3, $vgpr0
  63     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr68, 4, $vgpr0
  64     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr69, 5, $vgpr0
  65     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr70, 6, $vgpr0
  66     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr71, 7, $vgpr0
  67     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr72, 8, $vgpr0
  68     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr73, 9, $vgpr0
  69     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr74, 10, $vgpr0
  70     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr75, 11, $vgpr0
  71     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr76, 12, $vgpr0
  72     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr77, 13, $vgpr0
  73     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr78, 14, $vgpr0
  74     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr79, 15, $vgpr0
  75     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr80, 16, $vgpr0
  76     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr81, 17, $vgpr0
  77     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr82, 18, $vgpr0
  78     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr83, 19, $vgpr0
  79     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr84, 20, $vgpr0
  80     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr85, 21, $vgpr0
  81     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr86, 22, $vgpr0
  82     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr87, 23, $vgpr0
  83     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr88, 24, $vgpr0
  84     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr89, 25, $vgpr0
  85     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr90, 26, $vgpr0
  86     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr91, 27, $vgpr0
  87     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr92, 28, $vgpr0
  88     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr93, 29, $vgpr0
  89     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr94, 30, $vgpr0
  90     ; GCN-NEXT: $vgpr0 = V_WRITELANE_B32 killed $sgpr95, 31, $vgpr0
  91     ; GCN-NEXT: S_NOP 0
  92     ; GCN-NEXT: [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr10, 0, [[V_WRITELANE_B32_]]
  93     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr64, 1, [[V_WRITELANE_B32_1]], implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
  94     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr65, 2, [[V_WRITELANE_B32_1]]
  95     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr66, 3, [[V_WRITELANE_B32_1]]
  96     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr67, 4, [[V_WRITELANE_B32_1]]
  97     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr68, 5, [[V_WRITELANE_B32_1]]
  98     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr69, 6, [[V_WRITELANE_B32_1]]
  99     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr70, 7, [[V_WRITELANE_B32_1]]
 100     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr71, 8, [[V_WRITELANE_B32_1]]
 101     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr72, 9, [[V_WRITELANE_B32_1]]
 102     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr73, 10, [[V_WRITELANE_B32_1]]
 103     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr74, 11, [[V_WRITELANE_B32_1]]
 104     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr75, 12, [[V_WRITELANE_B32_1]]
 105     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr76, 13, [[V_WRITELANE_B32_1]]
 106     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr77, 14, [[V_WRITELANE_B32_1]]
 107     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr78, 15, [[V_WRITELANE_B32_1]]
 108     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr79, 16, [[V_WRITELANE_B32_1]]
 109     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr80, 17, [[V_WRITELANE_B32_1]]
 110     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr81, 18, [[V_WRITELANE_B32_1]]
 111     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr82, 19, [[V_WRITELANE_B32_1]]
 112     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr83, 20, [[V_WRITELANE_B32_1]]
 113     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr84, 21, [[V_WRITELANE_B32_1]]
 114     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr85, 22, [[V_WRITELANE_B32_1]]
 115     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr86, 23, [[V_WRITELANE_B32_1]]
 116     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr87, 24, [[V_WRITELANE_B32_1]]
 117     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr88, 25, [[V_WRITELANE_B32_1]]
 118     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr89, 26, [[V_WRITELANE_B32_1]]
 119     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr90, 27, [[V_WRITELANE_B32_1]]
 120     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr91, 28, [[V_WRITELANE_B32_1]]
 121     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr92, 29, [[V_WRITELANE_B32_1]]
 122     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr93, 30, [[V_WRITELANE_B32_1]]
 123     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr94, 31, [[V_WRITELANE_B32_1]]
 124     ; GCN-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr95, 32, [[V_WRITELANE_B32_1]], implicit killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
 125     ; GCN-NEXT: S_NOP 0
 126     ; GCN-NEXT: $sgpr64 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 1, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
 127     ; GCN-NEXT: $sgpr65 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 2
 128     ; GCN-NEXT: $sgpr66 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 3
 129     ; GCN-NEXT: $sgpr67 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 4
 130     ; GCN-NEXT: $sgpr68 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 5
 131     ; GCN-NEXT: $sgpr69 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 6
 132     ; GCN-NEXT: $sgpr70 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 7
 133     ; GCN-NEXT: $sgpr71 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 8
 134     ; GCN-NEXT: $sgpr72 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 9
 135     ; GCN-NEXT: $sgpr73 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 10
 136     ; GCN-NEXT: $sgpr74 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 11
 137     ; GCN-NEXT: $sgpr75 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 12
 138     ; GCN-NEXT: $sgpr76 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 13
 139     ; GCN-NEXT: $sgpr77 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 14
 140     ; GCN-NEXT: $sgpr78 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 15
 141     ; GCN-NEXT: $sgpr79 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 16
 142     ; GCN-NEXT: $sgpr80 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 17
 143     ; GCN-NEXT: $sgpr81 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 18
 144     ; GCN-NEXT: $sgpr82 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 19
 145     ; GCN-NEXT: $sgpr83 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 20
 146     ; GCN-NEXT: $sgpr84 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 21
 147     ; GCN-NEXT: $sgpr85 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 22
 148     ; GCN-NEXT: $sgpr86 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 23
 149     ; GCN-NEXT: $sgpr87 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 24
 150     ; GCN-NEXT: $sgpr88 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 25
 151     ; GCN-NEXT: $sgpr89 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 26
 152     ; GCN-NEXT: $sgpr90 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 27
 153     ; GCN-NEXT: $sgpr91 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 28
 154     ; GCN-NEXT: $sgpr92 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 29
 155     ; GCN-NEXT: $sgpr93 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 30
 156     ; GCN-NEXT: $sgpr94 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 31
 157     ; GCN-NEXT: $sgpr95 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 32
 158     ; GCN-NEXT: $sgpr10 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 0
 159     ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr31
 160     S_NOP 0
 161     SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 162     SI_SPILL_S1024_SAVE killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 163     S_NOP 0
 164     renamable $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 = SI_SPILL_S1024_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 165     renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 166     S_SETPC_B64 $sgpr30_sgpr31
 167 ...
 168
 169 # The implicit def for the lane VGPR should be inserted at the common dominator block (the entry block here).
 170
 171 ---
 172 name:            lane_vgpr_implicit_def_at_common_dominator_block
 173 tracksRegLiveness: true
 174 frameInfo:
 175   maxAlignment:    4
 176 stack:
 177   - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
 178 machineFunctionInfo:
 179   isEntryFunction: false
 180   scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
 181   stackPtrOffsetReg: '$sgpr32'
 182   frameOffsetReg: '$sgpr33'
 183   hasSpilledSGPRs: true
 184 body:             |
 185   ; GCN-LABEL: name: lane_vgpr_implicit_def_at_common_dominator_block
 186   ; GCN: bb.0:
 187   ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
 188   ; GCN-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 189   ; GCN-NEXT: {{  $}}
 190   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 191   ; GCN-NEXT:   S_NOP 0
 192   ; GCN-NEXT:   S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
 193   ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
 194   ; GCN-NEXT: {{  $}}
 195   ; GCN-NEXT: bb.1:
 196   ; GCN-NEXT:   successors: %bb.3(0x80000000)
 197   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 198   ; GCN-NEXT: {{  $}}
 199   ; GCN-NEXT:   $sgpr10 = S_MOV_B32 10
 200   ; GCN-NEXT:   [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr10, 0, [[V_WRITELANE_B32_]]
 201   ; GCN-NEXT:   S_BRANCH %bb.3
 202   ; GCN-NEXT: {{  $}}
 203   ; GCN-NEXT: bb.2:
 204   ; GCN-NEXT:   successors: %bb.3(0x80000000)
 205   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 206   ; GCN-NEXT: {{  $}}
 207   ; GCN-NEXT:   $sgpr10 = S_MOV_B32 20
 208   ; GCN-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr10, 0, [[V_WRITELANE_B32_1]]
 209   ; GCN-NEXT:   S_BRANCH %bb.3
 210   ; GCN-NEXT: {{  $}}
 211   ; GCN-NEXT: bb.3:
 212   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 213   ; GCN-NEXT: {{  $}}
 214   ; GCN-NEXT:   $sgpr10 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 0
 215   ; GCN-NEXT:   S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10
 216   bb.0:
 217     liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 218     S_NOP 0
 219     S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
 220     S_CBRANCH_SCC1 %bb.2, implicit killed $scc
 221   bb.1:
 222     liveins: $sgpr10, $sgpr30_sgpr31
 223     $sgpr10 = S_MOV_B32 10
 224     SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 225     S_BRANCH %bb.3
 226   bb.2:
 227     liveins: $sgpr10, $sgpr30_sgpr31
 228     $sgpr10 = S_MOV_B32 20
 229     SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 230     S_BRANCH %bb.3
 231   bb.3:
 232     liveins: $sgpr10, $sgpr30_sgpr31
 233     renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 234     S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10
 235 ...
 236
 237 # The common dominator block is visited only at the end. The insertion point was initially identified to the
 238 # terminator instruction in the dominator block which later becomes the point where a spill get inserted in the same block.
 239
 240 ---
 241 name:            dominator_block_follows_the_successors_bbs
 242 tracksRegLiveness: true
 243 frameInfo:
 244   maxAlignment:    4
 245 stack:
 246   - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
 247 machineFunctionInfo:
 248   isEntryFunction: false
 249   scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
 250   stackPtrOffsetReg: '$sgpr32'
 251   frameOffsetReg: '$sgpr33'
 252   hasSpilledSGPRs: true
 253 body:             |
 254   ; GCN-LABEL: name: dominator_block_follows_the_successors_bbs
 255   ; GCN: bb.0:
 256   ; GCN-NEXT:   successors: %bb.3(0x80000000)
 257   ; GCN-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 258   ; GCN-NEXT: {{  $}}
 259   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 260   ; GCN-NEXT:   S_NOP 0
 261   ; GCN-NEXT:   S_BRANCH %bb.3
 262   ; GCN-NEXT: {{  $}}
 263   ; GCN-NEXT: bb.1:
 264   ; GCN-NEXT:   successors: %bb.2(0x80000000)
 265   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 266   ; GCN-NEXT: {{  $}}
 267   ; GCN-NEXT:   $sgpr10 = V_READLANE_B32 [[DEF]], 0
 268   ; GCN-NEXT:   $sgpr10 = S_ADD_I32 $sgpr10, 15, implicit-def dead $scc
 269   ; GCN-NEXT:   S_BRANCH %bb.2
 270   ; GCN-NEXT: {{  $}}
 271   ; GCN-NEXT: bb.2:
 272   ; GCN-NEXT:   successors: %bb.3(0x80000000)
 273   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 274   ; GCN-NEXT: {{  $}}
 275   ; GCN-NEXT:   $sgpr10 = V_READLANE_B32 [[DEF]], 0
 276   ; GCN-NEXT:   $sgpr10 = S_ADD_I32 $sgpr10, 20, implicit-def dead $scc
 277   ; GCN-NEXT:   S_BRANCH %bb.3
 278   ; GCN-NEXT: {{  $}}
 279   ; GCN-NEXT: bb.3:
 280   ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
 281   ; GCN-NEXT:   liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 282   ; GCN-NEXT: {{  $}}
 283   ; GCN-NEXT:   $sgpr10 = S_MOV_B32 10
 284   ; GCN-NEXT:   [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr10, 0, [[V_WRITELANE_B32_]]
 285   ; GCN-NEXT:   S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
 286   ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
 287   ; GCN-NEXT:   S_BRANCH %bb.1
 288   ; GCN-NEXT: {{  $}}
 289   ; GCN-NEXT: bb.4:
 290   ; GCN-NEXT:   liveins: $sgpr10, $sgpr30_sgpr31
 291   ; GCN-NEXT: {{  $}}
 292   ; GCN-NEXT:   S_NOP 0
 293   ; GCN-NEXT:   S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10
 294   bb.0:
 295     liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 296     S_NOP 0
 297     S_BRANCH %bb.3
 298   bb.1:
 299     liveins: $sgpr10, $sgpr30_sgpr31
 300     renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 301     $sgpr10 = S_ADD_I32 $sgpr10, 15, implicit-def dead $scc
 302     S_BRANCH %bb.2
 303   bb.2:
 304     liveins: $sgpr10, $sgpr30_sgpr31
 305     renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 306     $sgpr10 = S_ADD_I32 $sgpr10, 20, implicit-def dead $scc
 307     S_BRANCH %bb.3
 308   bb.3:
 309     liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
 310     $sgpr10 = S_MOV_B32 10
 311     SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
 312     S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
 313     S_CBRANCH_SCC1 %bb.2, implicit killed $scc
 314     S_BRANCH %bb.1
 315   bb.4:
 316     liveins: $sgpr10, $sgpr30_sgpr31
 317     S_NOP 0
 318     S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10
 319 ...