llvm/test/CodeGen/AMDGPU/spill352.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
   3 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
   4
   5 # Make sure spill/restore of 352 bit registers works.
   6
   7 ---
   8 name: spill_restore_sgpr352
   9 tracksRegLiveness: true
  10 machineFunctionInfo:
  11   scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
  12   stackPtrOffsetReg: $sgpr32
  13 body: |
  14   ; SPILLED-LABEL: name: spill_restore_sgpr352
  15   ; SPILLED: bb.0:
  16   ; SPILLED-NEXT:   successors: %bb.1(0x80000000)
  17   ; SPILLED-NEXT: {{  $}}
  18   ; SPILLED-NEXT:   S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  19   ; SPILLED-NEXT:   SI_SPILL_S352_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s352) into %stack.0, align 4, addrspace 5)
  20   ; SPILLED-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit undef $scc
  21   ; SPILLED-NEXT: {{  $}}
  22   ; SPILLED-NEXT: bb.1:
  23   ; SPILLED-NEXT:   successors: %bb.2(0x80000000)
  24   ; SPILLED-NEXT: {{  $}}
  25   ; SPILLED-NEXT:   S_NOP 1
  26   ; SPILLED-NEXT: {{  $}}
  27   ; SPILLED-NEXT: bb.2:
  28   ; SPILLED-NEXT:   $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14 = SI_SPILL_S352_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s352) from %stack.0, align 4, addrspace 5)
  29   ; SPILLED-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  30   ; EXPANDED-LABEL: name: spill_restore_sgpr352
  31   ; EXPANDED: bb.0:
  32   ; EXPANDED-NEXT:   successors: %bb.1(0x80000000)
  33   ; EXPANDED-NEXT: {{  $}}
  34   ; EXPANDED-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  35   ; EXPANDED-NEXT:   S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  36   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr4, 0, [[V_WRITELANE_B32_]], implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  37   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr5, 1, [[V_WRITELANE_B32_1]]
  38   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr6, 2, [[V_WRITELANE_B32_1]]
  39   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr7, 3, [[V_WRITELANE_B32_1]]
  40   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr8, 4, [[V_WRITELANE_B32_1]]
  41   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr9, 5, [[V_WRITELANE_B32_1]]
  42   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr10, 6, [[V_WRITELANE_B32_1]]
  43   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr11, 7, [[V_WRITELANE_B32_1]]
  44   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr12, 8, [[V_WRITELANE_B32_1]]
  45   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr13, 9, [[V_WRITELANE_B32_1]]
  46   ; EXPANDED-NEXT:   [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr14, 10, [[V_WRITELANE_B32_1]], implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  47   ; EXPANDED-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit undef $scc
  48   ; EXPANDED-NEXT: {{  $}}
  49   ; EXPANDED-NEXT: bb.1:
  50   ; EXPANDED-NEXT:   successors: %bb.2(0x80000000)
  51   ; EXPANDED-NEXT: {{  $}}
  52   ; EXPANDED-NEXT:   S_NOP 1
  53   ; EXPANDED-NEXT: {{  $}}
  54   ; EXPANDED-NEXT: bb.2:
  55   ; EXPANDED-NEXT:   $sgpr4 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  56   ; EXPANDED-NEXT:   $sgpr5 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 1
  57   ; EXPANDED-NEXT:   $sgpr6 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 2
  58   ; EXPANDED-NEXT:   $sgpr7 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 3
  59   ; EXPANDED-NEXT:   $sgpr8 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 4
  60   ; EXPANDED-NEXT:   $sgpr9 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 5
  61   ; EXPANDED-NEXT:   $sgpr10 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 6
  62   ; EXPANDED-NEXT:   $sgpr11 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 7
  63   ; EXPANDED-NEXT:   $sgpr12 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 8
  64   ; EXPANDED-NEXT:   $sgpr13 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 9
  65   ; EXPANDED-NEXT:   $sgpr14 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 10
  66   ; EXPANDED-NEXT:   S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
  67   bb.0:
  68     S_NOP 0, implicit-def %0:sgpr_352
  69     S_CBRANCH_SCC1 implicit undef $scc, %bb.1
  70
  71   bb.1:
  72     S_NOP 1
  73
  74   bb.2:
  75     S_NOP 0, implicit %0
  76 ...
  77
  78 ---
  79 name: spill_restore_vgpr352
  80 tracksRegLiveness: true
  81 machineFunctionInfo:
  82   scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
  83   stackPtrOffsetReg: $sgpr32
  84 body: |
  85   ; SPILLED-LABEL: name: spill_restore_vgpr352
  86   ; SPILLED: bb.0:
  87   ; SPILLED-NEXT:   successors: %bb.1(0x80000000)
  88   ; SPILLED-NEXT: {{  $}}
  89   ; SPILLED-NEXT:   S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
  90   ; SPILLED-NEXT:   SI_SPILL_V352_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10, %stack.0, $sgpr32, 0, implicit $exec :: (store (s352) into %stack.0, align 4, addrspace 5)
  91   ; SPILLED-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit undef $scc
  92   ; SPILLED-NEXT: {{  $}}
  93   ; SPILLED-NEXT: bb.1:
  94   ; SPILLED-NEXT:   successors: %bb.2(0x80000000)
  95   ; SPILLED-NEXT: {{  $}}
  96   ; SPILLED-NEXT:   S_NOP 1
  97   ; SPILLED-NEXT: {{  $}}
  98   ; SPILLED-NEXT: bb.2:
  99   ; SPILLED-NEXT:   $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 = SI_SPILL_V352_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s352) from %stack.0, align 4, addrspace 5)
 100   ; SPILLED-NEXT:   S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
 101   ; EXPANDED-LABEL: name: spill_restore_vgpr352
 102   ; EXPANDED: bb.0:
 103   ; EXPANDED-NEXT:   successors: %bb.1(0x80000000)
 104   ; EXPANDED-NEXT: {{  $}}
 105   ; EXPANDED-NEXT:   S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
 106   ; EXPANDED-NEXT:   SI_SPILL_V352_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10, %stack.0, $sgpr32, 0, implicit $exec :: (store (s352) into %stack.0, align 4, addrspace 5)
 107   ; EXPANDED-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit undef $scc
 108   ; EXPANDED-NEXT: {{  $}}
 109   ; EXPANDED-NEXT: bb.1:
 110   ; EXPANDED-NEXT:   successors: %bb.2(0x80000000)
 111   ; EXPANDED-NEXT: {{  $}}
 112   ; EXPANDED-NEXT:   S_NOP 1
 113   ; EXPANDED-NEXT: {{  $}}
 114   ; EXPANDED-NEXT: bb.2:
 115   ; EXPANDED-NEXT:   $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 = SI_SPILL_V352_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s352) from %stack.0, align 4, addrspace 5)
 116   ; EXPANDED-NEXT:   S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
 117   bb.0:
 118     S_NOP 0, implicit-def %0:vreg_352
 119     S_CBRANCH_SCC1 implicit undef $scc, %bb.1
 120
 121   bb.1:
 122     S_NOP 1
 123
 124   bb.2:
 125     S_NOP 0, implicit %0
 126 ...