[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / ExecutionEngine / RuntimeDyld / AArch64 / COFF_AArch64.s
blob9a31952b69973e185a678564202cbf2d97a8a51a
1 // RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
2 // RUN: llvm-rtdyld -triple aarch64-windows -dummy-extern dummy=0x79563413 -dummy-extern dummyA=0x78566879 -target-addr-start=40960000000000 -verify -check %s %t.obj
4 .text
5 .def _bnamed
6 .scl 2
7 .type 32
8 .endef
10 .globl _bnamed
11 .align 2
12 _bnamed:
13 ret
15 .def _foo
16 .scl 2
17 .type 32
18 .endef
19 .globl _foo
20 .align 2
21 _foo:
22 movz w0, #0
23 ret
25 .globl _test_adr_relocation
26 .align 2
28 # IMAGE_REL_ARM64_REL21
29 # rtdyld-check: decode_operand(adr1, 1) = (_const[20:0] - adr1[20:0])
30 _test_adr_relocation:
31 adr1:
32 adr x0, _const
33 ret
35 .globl _test_branch26_reloc
36 .align 2
38 # IMAGE_REL_ARM64_BRANCH26, test long branch
39 # rtdyld-check: decode_operand(brel, 0)[25:0] = (stub_addr(COFF_AArch64.s.tmp.obj/.text, dummy) - brel)[27:2]
40 _test_branch26_reloc:
41 brel:
42 b dummy
43 ret
45 .globl _test_branch19_reloc
46 .align 2
48 # IMAGE_REL_ARM64_BRANCH19
49 # rtdyld-check: decode_operand(bcond, 1)[18:0] = (_foo - bcond)[20:2]
50 _test_branch19_reloc:
51 mov x0, #3
52 cmp x0, #2
53 bcond:
54 bne _foo
55 ret
57 .globl _test_branch14_reloc
58 .align 2
60 # IMAGE_REL_ARM64_BRANCH14
61 # rtdyld-check: decode_operand(tbz_branch, 2)[13:0] = (_bnamed - tbz_branch)[15:2]
62 _test_branch14_reloc:
63 mov x1, #0
64 tbz_branch:
65 tbz x1, #0, _bnamed
66 ret
68 .globl _test_adrp_ldr_reloc
69 .align 2
71 # IMAGE_REL_ARM64_PAGEBASE_REL21
72 # rtdyld-check: decode_operand(adrp1, 1) = (_const[32:12] - adrp1[32:12])
73 _test_adrp_ldr_reloc:
74 adrp1:
75 adrp x0, _const
77 # IMAGE_REL_ARM64_PAGEOFFSET_12L
78 # rtdyld-check: decode_operand(ldr1, 2) = _const[11:3]
79 ldr1:
80 ldr x0, [x0, #:lo12:_const]
81 ret
83 .globl _test_add_reloc
84 .align 2
86 # IMAGE_REL_ARM64_PAGEOFFSET_12A
87 # rtdyld-check: decode_operand(add1, 2) = (tgt+4)[11:0]
88 _test_add_reloc:
89 add1:
90 add x0, x0, tgt@PAGEOFF+4
91 ret
93 .section .data
94 .globl _test_addr64_reloc
95 .align 2
97 # IMAGE_REL_ARM64_ADDR64
98 # rtdyld-check: *{8}addr64 = tgt+4
99 _test_addr64_reloc:
100 addr64:
101 .quad tgt+4
103 # IMAGE_REL_ARM64_ADDR32
104 # rtdyld-check: *{4}_test_addr32_reloc = 0x78566879
105 _test_addr32_reloc:
106 .long dummyA
108 .globl _relocations
109 .align 2
111 # IMAGE_REL_ARM64_ADDR32NB, RVA of the target
112 # rtdyld-check: *{4}_relocations = _foo - 40960000000000
113 _relocations:
114 .long _foo@IMGREL
116 # IMAGE_REL_ARM64_ADDR32NB
117 # rtdyld-check: *{4}imgrel2 = _string - 40960000000000+5
118 imgrel2:
119 .long _string@IMGREL+5
121 # IMAGE_REL_ARM64_SECTION
122 # rtdyld-check: *{2}secindex = 1
123 secindex:
124 .secidx _test_addr32_reloc
126 # IMAGE_REL_ARM64_SECREL
127 # rtdyld-check: *{4}secrel = string - section_addr(COFF_AArch64.s.tmp.obj, .data)
128 secrel:
129 .secrel32 string
131 .globl _const
132 .align 3
133 _const:
134 .quad 4614256650576692846
136 tgt:
137 .word 1
138 .word 2
139 .word 3
140 .word 4
141 .word 5
143 .globl string
144 .align 2
145 string:
146 .asciz "Hello World\n"
148 .section .rdata,"dr"
149 .globl _string
150 .align 2
151 _string:
152 .asciz "Hello World\n"