[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / CSSC / smin_64_reg.s
blob6dec536d5f9c72793b0d03cab7813e34a0128f74
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+v9.4a < %s \
6 // RUN: | llvm-objdump -d --mattr=+v9.4a - | FileCheck %s --check-prefix=CHECK-INST
7 // Disassemble encoding and check the re-encoding (-show-encoding) matches.
8 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \
9 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
10 // RUN: | llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble -show-encoding \
11 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
13 smin x0, x0, x0
14 // CHECK-INST: smin x0, x0, x0
15 // CHECK-ENCODING: [0x00,0x68,0xc0,0x9a]
16 // CHECK-ERROR: instruction requires: cssc
18 smin x21, x10, x21
19 // CHECK-INST: smin x21, x10, x21
20 // CHECK-ENCODING: [0x55,0x69,0xd5,0x9a]
21 // CHECK-ERROR: instruction requires: cssc
23 smin x23, x13, x8
24 // CHECK-INST: smin x23, x13, x8
25 // CHECK-ENCODING: [0xb7,0x69,0xc8,0x9a]
26 // CHECK-ERROR: instruction requires: cssc
28 smin xzr, xzr, xzr
29 // CHECK-INST: smin xzr, xzr, xzr
30 // CHECK-ENCODING: [0xff,0x6b,0xdf,0x9a]
31 // CHECK-ERROR: instruction requires: cssc