llvm/test/MC/AArch64/SME2/fmlal-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 fmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: fmlal za.s[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z17.h}, z7.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 fmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  18 // CHECK-NEXT: fmlal za.s[w10, 2:3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid indexed-vector register
  23
  24 fmlal za.s[w8, 0:1], z0.h, z16.h[0]
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  26 // CHECK-NEXT: fmlal za.s[w8, 0:1], z0.h, z16.h[0]
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 fmlal za.s[w8, 0:1], z0.h, z30.h
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  31 // CHECK-NEXT: fmlal za.s[w8, 0:1], z0.h, z30.h
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 // --------------------------------------------------------------------------//
  35 // Invalid vector select register
  36
  37 fmlal za.s[w3, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  39 // CHECK-NEXT: fmlal za.s[w3, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 // --------------------------------------------------------------------------//
  43 // Invalid vector select offset
  44
  45 fmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  47 // CHECK-NEXT: fmlal za.s[w8, 6:9, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 fmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
  52 // CHECK-NEXT: fmlal za.s[w8, 9:10, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 // --------------------------------------------------------------------------//
  56 // Invalid Register Suffix
  57
  58 fmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  59 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
  60 // CHECK-NEXT: fmlal za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  61 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  62
  63 // --------------------------------------------------------------------------//
  64 // Invalid vector lane index
  65
  66 fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
  67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  68 // CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[8]
  69 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  70
  71 fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
  72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  73 // CHECK-NEXT: fmlal za.s[w11, 6:7, vgx4], {z12.h-z15.h}, z8.h[-1]
  74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: