[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / abs.s
blob87350dc8a1b55ec08c3dedbeb02e01eb1b944bab
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 abs z0.b, p0/m, z0.b
13 // CHECK-INST: abs z0.b, p0/m, z0.b
14 // CHECK-ENCODING: [0x00,0xa0,0x16,0x04]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 0416a000 <unknown>
18 abs z0.h, p0/m, z0.h
19 // CHECK-INST: abs z0.h, p0/m, z0.h
20 // CHECK-ENCODING: [0x00,0xa0,0x56,0x04]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 0456a000 <unknown>
24 abs z0.s, p0/m, z0.s
25 // CHECK-INST: abs z0.s, p0/m, z0.s
26 // CHECK-ENCODING: [0x00,0xa0,0x96,0x04]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 0496a000 <unknown>
30 abs z0.d, p0/m, z0.d
31 // CHECK-INST: abs z0.d, p0/m, z0.d
32 // CHECK-ENCODING: [0x00,0xa0,0xd6,0x04]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 04d6a000 <unknown>
36 abs z31.b, p7/m, z31.b
37 // CHECK-INST: abs z31.b, p7/m, z31.b
38 // CHECK-ENCODING: [0xff,0xbf,0x16,0x04]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 0416bfff <unknown>
42 abs z31.h, p7/m, z31.h
43 // CHECK-INST: abs z31.h, p7/m, z31.h
44 // CHECK-ENCODING: [0xff,0xbf,0x56,0x04]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 0456bfff <unknown>
48 abs z31.s, p7/m, z31.s
49 // CHECK-INST: abs z31.s, p7/m, z31.s
50 // CHECK-ENCODING: [0xff,0xbf,0x96,0x04]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 0496bfff <unknown>
54 abs z31.d, p7/m, z31.d
55 // CHECK-INST: abs z31.d, p7/m, z31.d
56 // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 04d6bfff <unknown>
61 // --------------------------------------------------------------------------//
62 // Test compatibility with MOVPRFX instruction.
64 movprfx z4.d, p7/z, z6.d
65 // CHECK-INST: movprfx z4.d, p7/z, z6.d
66 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
67 // CHECK-ERROR: instruction requires: sve or sme
68 // CHECK-UNKNOWN: 04d03cc4 <unknown>
70 abs z4.d, p7/m, z31.d
71 // CHECK-INST: abs z4.d, p7/m, z31.d
72 // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
73 // CHECK-ERROR: instruction requires: sve or sme
74 // CHECK-UNKNOWN: 04d6bfe4 <unknown>
76 movprfx z4, z6
77 // CHECK-INST: movprfx z4, z6
78 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
79 // CHECK-ERROR: instruction requires: sve or sme
80 // CHECK-UNKNOWN: 0420bcc4 <unknown>
82 abs z4.d, p7/m, z31.d
83 // CHECK-INST: abs z4.d, p7/m, z31.d
84 // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
85 // CHECK-ERROR: instruction requires: sve or sme
86 // CHECK-UNKNOWN: 04d6bfe4 <unknown>