[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / andv.s
blobf734e984bad8fc18f739dde36647c4187153d07e
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 andv b0, p7, z31.b
13 // CHECK-INST: andv b0, p7, z31.b
14 // CHECK-ENCODING: [0xe0,0x3f,0x1a,0x04]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 041a3fe0 <unknown>
18 andv h0, p7, z31.h
19 // CHECK-INST: andv h0, p7, z31.h
20 // CHECK-ENCODING: [0xe0,0x3f,0x5a,0x04]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 045a3fe0 <unknown>
24 andv s0, p7, z31.s
25 // CHECK-INST: andv s0, p7, z31.s
26 // CHECK-ENCODING: [0xe0,0x3f,0x9a,0x04]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 049a3fe0 <unknown>
30 andv d0, p7, z31.d
31 // CHECK-INST: andv d0, p7, z31.d
32 // CHECK-ENCODING: [0xe0,0x3f,0xda,0x04]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 04da3fe0 <unknown>