[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / asrr.s
blob9b90bfd1e9c27855e5ae3077458830e35cca30b0
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 asrr z0.b, p0/m, z0.b, z0.b
13 // CHECK-INST: asrr z0.b, p0/m, z0.b, z0.b
14 // CHECK-ENCODING: [0x00,0x80,0x14,0x04]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 04148000 <unknown>
18 asrr z0.h, p0/m, z0.h, z0.h
19 // CHECK-INST: asrr z0.h, p0/m, z0.h, z0.h
20 // CHECK-ENCODING: [0x00,0x80,0x54,0x04]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 04548000 <unknown>
24 asrr z0.s, p0/m, z0.s, z0.s
25 // CHECK-INST: asrr z0.s, p0/m, z0.s, z0.s
26 // CHECK-ENCODING: [0x00,0x80,0x94,0x04]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 04948000 <unknown>
30 asrr z0.d, p0/m, z0.d, z0.d
31 // CHECK-INST: asrr z0.d, p0/m, z0.d, z0.d
32 // CHECK-ENCODING: [0x00,0x80,0xd4,0x04]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 04d48000 <unknown>
37 // --------------------------------------------------------------------------//
38 // Test compatibility with MOVPRFX instruction.
40 movprfx z5.d, p0/z, z7.d
41 // CHECK-INST: movprfx z5.d, p0/z, z7.d
42 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
43 // CHECK-ERROR: instruction requires: sve or sme
44 // CHECK-UNKNOWN: 04d020e5 <unknown>
46 asrr z5.d, p0/m, z5.d, z0.d
47 // CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d
48 // CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
49 // CHECK-ERROR: instruction requires: sve or sme
50 // CHECK-UNKNOWN: 04d48005 <unknown>
52 movprfx z5, z7
53 // CHECK-INST: movprfx z5, z7
54 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
55 // CHECK-ERROR: instruction requires: sve or sme
56 // CHECK-UNKNOWN: 0420bce5 <unknown>
58 asrr z5.d, p0/m, z5.d, z0.d
59 // CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d
60 // CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
61 // CHECK-ERROR: instruction requires: sve or sme
62 // CHECK-UNKNOWN: 04d48005 <unknown>