llvm/test/MC/AArch64/SVE/bfcvtnt-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -mattr=+sve,bf16  2>&1 < %s| FileCheck %s
   2
   3 bfcvtnt z0.s, p0/m, z1.s
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   5 // CHECK-NEXT: bfcvtnt z0.s, p0/m, z1.s
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8 bfcvtnt z0.h, p0/m, z1.h
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  10 // CHECK-NEXT: bfcvtnt z0.h, p0/m, z1.h
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13 bfcvtnt z0.h, p0/z, z1.s
  14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  15 // CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.s
  16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  17
  18 bfcvtnt z0.h, p8/m, z1.s
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  20 // CHECK-NEXT: bfcvtnt z0.h, p8/m, z1.s
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 movprfx z0.h, p0/m, z7.h
  24 bfcvtnt z0.h, p0/m, z1.s
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
  26 // CHECK-NEXT: bfcvtnt z0.h, p0/m, z1.s
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: