[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / clastb.s
blobe9dd34b0d4b221b2beaa92f81f2e665ec31956b9
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 clastb w0, p7, w0, z31.b
13 // CHECK-INST: clastb w0, p7, w0, z31.b
14 // CHECK-ENCODING: [0xe0,0xbf,0x31,0x05]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 0531bfe0 <unknown>
18 clastb w0, p7, w0, z31.h
19 // CHECK-INST: clastb w0, p7, w0, z31.h
20 // CHECK-ENCODING: [0xe0,0xbf,0x71,0x05]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 0571bfe0 <unknown>
24 clastb w0, p7, w0, z31.s
25 // CHECK-INST: clastb w0, p7, w0, z31.s
26 // CHECK-ENCODING: [0xe0,0xbf,0xb1,0x05]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 05b1bfe0 <unknown>
30 clastb x0, p7, x0, z31.d
31 // CHECK-INST: clastb x0, p7, x0, z31.d
32 // CHECK-ENCODING: [0xe0,0xbf,0xf1,0x05]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 05f1bfe0 <unknown>
36 clastb b0, p7, b0, z31.b
37 // CHECK-INST: clastb b0, p7, b0, z31.b
38 // CHECK-ENCODING: [0xe0,0x9f,0x2b,0x05]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 052b9fe0 <unknown>
42 clastb h0, p7, h0, z31.h
43 // CHECK-INST: clastb h0, p7, h0, z31.h
44 // CHECK-ENCODING: [0xe0,0x9f,0x6b,0x05]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 056b9fe0 <unknown>
48 clastb s0, p7, s0, z31.s
49 // CHECK-INST: clastb s0, p7, s0, z31.s
50 // CHECK-ENCODING: [0xe0,0x9f,0xab,0x05]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 05ab9fe0 <unknown>
54 clastb d0, p7, d0, z31.d
55 // CHECK-INST: clastb d0, p7, d0, z31.d
56 // CHECK-ENCODING: [0xe0,0x9f,0xeb,0x05]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 05eb9fe0 <unknown>
60 clastb z0.b, p7, z0.b, z31.b
61 // CHECK-INST: clastb z0.b, p7, z0.b, z31.b
62 // CHECK-ENCODING: [0xe0,0x9f,0x29,0x05]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 05299fe0 <unknown>
66 clastb z0.h, p7, z0.h, z31.h
67 // CHECK-INST: clastb z0.h, p7, z0.h, z31.h
68 // CHECK-ENCODING: [0xe0,0x9f,0x69,0x05]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 05699fe0 <unknown>
72 clastb z0.s, p7, z0.s, z31.s
73 // CHECK-INST: clastb z0.s, p7, z0.s, z31.s
74 // CHECK-ENCODING: [0xe0,0x9f,0xa9,0x05]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 05a99fe0 <unknown>
78 clastb z0.d, p7, z0.d, z31.d
79 // CHECK-INST: clastb z0.d, p7, z0.d, z31.d
80 // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 05e99fe0 <unknown>
85 // --------------------------------------------------------------------------//
86 // Test compatibility with MOVPRFX instruction.
88 movprfx z0, z7
89 // CHECK-INST: movprfx z0, z7
90 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
91 // CHECK-ERROR: instruction requires: sve or sme
92 // CHECK-UNKNOWN: 0420bce0 <unknown>
94 clastb z0.d, p7, z0.d, z31.d
95 // CHECK-INST: clastb z0.d, p7, z0.d, z31.d
96 // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
97 // CHECK-ERROR: instruction requires: sve or sme
98 // CHECK-UNKNOWN: 05e99fe0 <unknown>