[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / decp.s
blob9c6ae5e49bbcd2df6a73778ac0bb833ce05df49f
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 decp x0, p0.b
13 // CHECK-INST: decp x0, p0.b
14 // CHECK-ENCODING: [0x00,0x88,0x2d,0x25]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 252d8800 <unknown>
18 decp x0, p0.h
19 // CHECK-INST: decp x0, p0.h
20 // CHECK-ENCODING: [0x00,0x88,0x6d,0x25]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 256d8800 <unknown>
24 decp x0, p0.s
25 // CHECK-INST: decp x0, p0.s
26 // CHECK-ENCODING: [0x00,0x88,0xad,0x25]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 25ad8800 <unknown>
30 decp x0, p0.d
31 // CHECK-INST: decp x0, p0.d
32 // CHECK-ENCODING: [0x00,0x88,0xed,0x25]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 25ed8800 <unknown>
36 decp xzr, p15.b
37 // CHECK-INST: decp xzr, p15.b
38 // CHECK-ENCODING: [0xff,0x89,0x2d,0x25]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 252d89ff <unknown>
42 decp xzr, p15.h
43 // CHECK-INST: decp xzr, p15.h
44 // CHECK-ENCODING: [0xff,0x89,0x6d,0x25]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 256d89ff <unknown>
48 decp xzr, p15.s
49 // CHECK-INST: decp xzr, p15.s
50 // CHECK-ENCODING: [0xff,0x89,0xad,0x25]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 25ad89ff <unknown>
54 decp xzr, p15.d
55 // CHECK-INST: decp xzr, p15.d
56 // CHECK-ENCODING: [0xff,0x89,0xed,0x25]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 25ed89ff <unknown>
60 decp z31.h, p15
61 // CHECK-INST: decp z31.h, p15.h
62 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 256d81ff <unknown>
66 decp z31.h, p15.h
67 // CHECK-INST: decp z31.h, p15.h
68 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 256d81ff <unknown>
72 decp z31.s, p15
73 // CHECK-INST: decp z31.s, p15.s
74 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 25ad81ff <unknown>
78 decp z31.s, p15.s
79 // CHECK-INST: decp z31.s, p15.s
80 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 25ad81ff <unknown>
84 decp z31.d, p15
85 // CHECK-INST: decp z31.d, p15.d
86 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: 25ed81ff <unknown>
90 decp z31.d, p15.d
91 // CHECK-INST: decp z31.d, p15.d
92 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: 25ed81ff <unknown>
97 // --------------------------------------------------------------------------//
98 // Test compatibility with MOVPRFX instruction.
100 movprfx z31, z6
101 // CHECK-INST: movprfx z31, z6
102 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
103 // CHECK-ERROR: instruction requires: sve or sme
104 // CHECK-UNKNOWN: 0420bcdf <unknown>
106 decp z31.d, p15.d
107 // CHECK-INST: decp z31.d, p15
108 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
109 // CHECK-ERROR: instruction requires: sve or sme
110 // CHECK-UNKNOWN: 25ed81ff <unknown>