[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / fcmuo.s
blob15a21323fa819af63e0545f17a132e7e9829ba14
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 fcmuo p0.h, p0/z, z0.h, z1.h
13 // CHECK-INST: fcmuo p0.h, p0/z, z0.h, z1.h
14 // CHECK-ENCODING: [0x00,0xc0,0x41,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 6541c000 <unknown>
18 fcmuo p0.s, p0/z, z0.s, z1.s
19 // CHECK-INST: fcmuo p0.s, p0/z, z0.s, z1.s
20 // CHECK-ENCODING: [0x00,0xc0,0x81,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 6581c000 <unknown>
24 fcmuo p0.d, p0/z, z0.d, z1.d
25 // CHECK-INST: fcmuo p0.d, p0/z, z0.d, z1.d
26 // CHECK-ENCODING: [0x00,0xc0,0xc1,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 65c1c000 <unknown>