[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / fcvtzu.s
blob80031ed7c373064a522037468ba58369a76c8df8
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 fcvtzu z0.h, p0/m, z0.h
13 // CHECK-INST: fcvtzu z0.h, p0/m, z0.h
14 // CHECK-ENCODING: [0x00,0xa0,0x5b,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 655ba000 <unknown>
18 fcvtzu z0.s, p0/m, z0.h
19 // CHECK-INST: fcvtzu z0.s, p0/m, z0.h
20 // CHECK-ENCODING: [0x00,0xa0,0x5d,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 655da000 <unknown>
24 fcvtzu z0.s, p0/m, z0.s
25 // CHECK-INST: fcvtzu z0.s, p0/m, z0.s
26 // CHECK-ENCODING: [0x00,0xa0,0x9d,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 659da000 <unknown>
30 fcvtzu z0.s, p0/m, z0.d
31 // CHECK-INST: fcvtzu z0.s, p0/m, z0.d
32 // CHECK-ENCODING: [0x00,0xa0,0xd9,0x65]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 65d9a000 <unknown>
36 fcvtzu z0.d, p0/m, z0.h
37 // CHECK-INST: fcvtzu z0.d, p0/m, z0.h
38 // CHECK-ENCODING: [0x00,0xa0,0x5f,0x65]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 655fa000 <unknown>
42 fcvtzu z0.d, p0/m, z0.s
43 // CHECK-INST: fcvtzu z0.d, p0/m, z0.s
44 // CHECK-ENCODING: [0x00,0xa0,0xdd,0x65]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 65dda000 <unknown>
48 fcvtzu z0.d, p0/m, z0.d
49 // CHECK-INST: fcvtzu z0.d, p0/m, z0.d
50 // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 65dfa000 <unknown>
55 // --------------------------------------------------------------------------//
56 // Test compatibility with MOVPRFX instruction.
58 movprfx z5.d, p0/z, z7.d
59 // CHECK-INST: movprfx z5.d, p0/z, z7.d
60 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
61 // CHECK-ERROR: instruction requires: sve or sme
62 // CHECK-UNKNOWN: 04d020e5 <unknown>
64 fcvtzu z5.d, p0/m, z0.d
65 // CHECK-INST: fcvtzu z5.d, p0/m, z0.d
66 // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
67 // CHECK-ERROR: instruction requires: sve or sme
68 // CHECK-UNKNOWN: 65dfa005 <unknown>
70 movprfx z5, z7
71 // CHECK-INST: movprfx z5, z7
72 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
73 // CHECK-ERROR: instruction requires: sve or sme
74 // CHECK-UNKNOWN: 0420bce5 <unknown>
76 fcvtzu z5.d, p0/m, z0.d
77 // CHECK-INST: fcvtzu z5.d, p0/m, z0.d
78 // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
79 // CHECK-ERROR: instruction requires: sve or sme
80 // CHECK-UNKNOWN: 65dfa005 <unknown>