[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / fdiv.s
blob4ac0e27918c32bc3529a9fec1a6a58d0e77f035b
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 fdiv z0.h, p7/m, z0.h, z31.h
13 // CHECK-INST: fdiv z0.h, p7/m, z0.h, z31.h
14 // CHECK-ENCODING: [0xe0,0x9f,0x4d,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 654d9fe0 <unknown>
18 fdiv z0.s, p7/m, z0.s, z31.s
19 // CHECK-INST: fdiv z0.s, p7/m, z0.s, z31.s
20 // CHECK-ENCODING: [0xe0,0x9f,0x8d,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 658d9fe0 <unknown>
24 fdiv z0.d, p7/m, z0.d, z31.d
25 // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
26 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 65cd9fe0 <unknown>
31 // --------------------------------------------------------------------------//
32 // Test compatibility with MOVPRFX instruction.
34 movprfx z0.d, p7/z, z7.d
35 // CHECK-INST: movprfx z0.d, p7/z, z7.d
36 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
37 // CHECK-ERROR: instruction requires: sve or sme
38 // CHECK-UNKNOWN: 04d03ce0 <unknown>
40 fdiv z0.d, p7/m, z0.d, z31.d
41 // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
42 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
43 // CHECK-ERROR: instruction requires: sve or sme
44 // CHECK-UNKNOWN: 65cd9fe0 <unknown>
46 movprfx z0, z7
47 // CHECK-INST: movprfx z0, z7
48 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
49 // CHECK-ERROR: instruction requires: sve or sme
50 // CHECK-UNKNOWN: 0420bce0 <unknown>
52 fdiv z0.d, p7/m, z0.d, z31.d
53 // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d
54 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
55 // CHECK-ERROR: instruction requires: sve or sme
56 // CHECK-UNKNOWN: 65cd9fe0 <unknown>