[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / fmul.s
blob474203b2602cbdb1191ac1eec25a1dd3a82c6e31
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 fmul z0.h, p0/m, z0.h, #0.5000000000000
13 // CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5
14 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 655a8000 <unknown>
18 fmul z0.h, p0/m, z0.h, #0.5
19 // CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5
20 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 655a8000 <unknown>
24 fmul z0.s, p0/m, z0.s, #0.5
25 // CHECK-INST: fmul z0.s, p0/m, z0.s, #0.5
26 // CHECK-ENCODING: [0x00,0x80,0x9a,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 659a8000 <unknown>
30 fmul z0.d, p0/m, z0.d, #0.5
31 // CHECK-INST: fmul z0.d, p0/m, z0.d, #0.5
32 // CHECK-ENCODING: [0x00,0x80,0xda,0x65]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 65da8000 <unknown>
36 fmul z31.h, p7/m, z31.h, #2.0
37 // CHECK-INST: fmul z31.h, p7/m, z31.h, #2.0
38 // CHECK-ENCODING: [0x3f,0x9c,0x5a,0x65]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 655a9c3f <unknown>
42 fmul z31.s, p7/m, z31.s, #2.0
43 // CHECK-INST: fmul z31.s, p7/m, z31.s, #2.0
44 // CHECK-ENCODING: [0x3f,0x9c,0x9a,0x65]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 659a9c3f <unknown>
48 fmul z31.d, p7/m, z31.d, #2.0
49 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
50 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 65da9c3f <unknown>
54 fmul z0.h, z0.h, z0.h[0]
55 // CHECK-INST: fmul z0.h, z0.h, z0.h[0]
56 // CHECK-ENCODING: [0x00,0x20,0x20,0x64]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 64202000 <unknown>
60 fmul z0.s, z0.s, z0.s[0]
61 // CHECK-INST: fmul z0.s, z0.s, z0.s[0]
62 // CHECK-ENCODING: [0x00,0x20,0xa0,0x64]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 64a02000 <unknown>
66 fmul z0.d, z0.d, z0.d[0]
67 // CHECK-INST: fmul z0.d, z0.d, z0.d[0]
68 // CHECK-ENCODING: [0x00,0x20,0xe0,0x64]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 64e02000 <unknown>
72 fmul z31.h, z31.h, z7.h[7]
73 // CHECK-INST: fmul z31.h, z31.h, z7.h[7]
74 // CHECK-ENCODING: [0xff,0x23,0x7f,0x64]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 647f23ff <unknown>
78 fmul z31.s, z31.s, z7.s[3]
79 // CHECK-INST: fmul z31.s, z31.s, z7.s[3]
80 // CHECK-ENCODING: [0xff,0x23,0xbf,0x64]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 64bf23ff <unknown>
84 fmul z31.d, z31.d, z15.d[1]
85 // CHECK-INST: fmul z31.d, z31.d, z15.d[1]
86 // CHECK-ENCODING: [0xff,0x23,0xff,0x64]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: 64ff23ff <unknown>
90 fmul z0.h, p7/m, z0.h, z31.h
91 // CHECK-INST: fmul z0.h, p7/m, z0.h, z31.h
92 // CHECK-ENCODING: [0xe0,0x9f,0x42,0x65]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: 65429fe0 <unknown>
96 fmul z0.s, p7/m, z0.s, z31.s
97 // CHECK-INST: fmul z0.s, p7/m, z0.s, z31.s
98 // CHECK-ENCODING: [0xe0,0x9f,0x82,0x65]
99 // CHECK-ERROR: instruction requires: sve or sme
100 // CHECK-UNKNOWN: 65829fe0 <unknown>
102 fmul z0.d, p7/m, z0.d, z31.d
103 // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
104 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
105 // CHECK-ERROR: instruction requires: sve or sme
106 // CHECK-UNKNOWN: 65c29fe0 <unknown>
108 fmul z0.h, z1.h, z31.h
109 // CHECK-INST: fmul z0.h, z1.h, z31.h
110 // CHECK-ENCODING: [0x20,0x08,0x5f,0x65]
111 // CHECK-ERROR: instruction requires: sve or sme
112 // CHECK-UNKNOWN: 655f0820 <unknown>
114 fmul z0.s, z1.s, z31.s
115 // CHECK-INST: fmul z0.s, z1.s, z31.s
116 // CHECK-ENCODING: [0x20,0x08,0x9f,0x65]
117 // CHECK-ERROR: instruction requires: sve or sme
118 // CHECK-UNKNOWN: 659f0820 <unknown>
120 fmul z0.d, z1.d, z31.d
121 // CHECK-INST: fmul z0.d, z1.d, z31.d
122 // CHECK-ENCODING: [0x20,0x08,0xdf,0x65]
123 // CHECK-ERROR: instruction requires: sve or sme
124 // CHECK-UNKNOWN: 65df0820 <unknown>
127 // --------------------------------------------------------------------------//
128 // Test compatibility with MOVPRFX instruction.
130 movprfx z31.d, p7/z, z6.d
131 // CHECK-INST: movprfx z31.d, p7/z, z6.d
132 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
133 // CHECK-ERROR: instruction requires: sve or sme
134 // CHECK-UNKNOWN: 04d03cdf <unknown>
136 fmul z31.d, p7/m, z31.d, #2.0
137 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
138 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
139 // CHECK-ERROR: instruction requires: sve or sme
140 // CHECK-UNKNOWN: 65da9c3f <unknown>
142 movprfx z31, z6
143 // CHECK-INST: movprfx z31, z6
144 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
145 // CHECK-ERROR: instruction requires: sve or sme
146 // CHECK-UNKNOWN: 0420bcdf <unknown>
148 fmul z31.d, p7/m, z31.d, #2.0
149 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
150 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
151 // CHECK-ERROR: instruction requires: sve or sme
152 // CHECK-UNKNOWN: 65da9c3f <unknown>
154 movprfx z0.d, p7/z, z7.d
155 // CHECK-INST: movprfx z0.d, p7/z, z7.d
156 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
157 // CHECK-ERROR: instruction requires: sve or sme
158 // CHECK-UNKNOWN: 04d03ce0 <unknown>
160 fmul z0.d, p7/m, z0.d, z31.d
161 // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
162 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
163 // CHECK-ERROR: instruction requires: sve or sme
164 // CHECK-UNKNOWN: 65c29fe0 <unknown>
166 movprfx z0, z7
167 // CHECK-INST: movprfx z0, z7
168 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
169 // CHECK-ERROR: instruction requires: sve or sme
170 // CHECK-UNKNOWN: 0420bce0 <unknown>
172 fmul z0.d, p7/m, z0.d, z31.d
173 // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
174 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
175 // CHECK-ERROR: instruction requires: sve or sme
176 // CHECK-UNKNOWN: 65c29fe0 <unknown>