[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / frintn.s
blobdf7d91122a372f1a9c7dfdb7216e341f41b9d969
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 frintn z31.h, p7/m, z31.h
13 // CHECK-INST: frintn z31.h, p7/m, z31.h
14 // CHECK-ENCODING: [0xff,0xbf,0x40,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 6540bfff <unknown>
18 frintn z31.s, p7/m, z31.s
19 // CHECK-INST: frintn z31.s, p7/m, z31.s
20 // CHECK-ENCODING: [0xff,0xbf,0x80,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 6580bfff <unknown>
24 frintn z31.d, p7/m, z31.d
25 // CHECK-INST: frintn z31.d, p7/m, z31.d
26 // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 65c0bfff <unknown>
31 // --------------------------------------------------------------------------//
32 // Test compatibility with MOVPRFX instruction.
34 movprfx z4.d, p7/z, z6.d
35 // CHECK-INST: movprfx z4.d, p7/z, z6.d
36 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
37 // CHECK-ERROR: instruction requires: sve or sme
38 // CHECK-UNKNOWN: 04d03cc4 <unknown>
40 frintn z4.d, p7/m, z31.d
41 // CHECK-INST: frintn z4.d, p7/m, z31.d
42 // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
43 // CHECK-ERROR: instruction requires: sve or sme
44 // CHECK-UNKNOWN: 65c0bfe4 <unknown>
46 movprfx z4, z6
47 // CHECK-INST: movprfx z4, z6
48 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
49 // CHECK-ERROR: instruction requires: sve or sme
50 // CHECK-UNKNOWN: 0420bcc4 <unknown>
52 frintn z4.d, p7/m, z31.d
53 // CHECK-INST: frintn z4.d, p7/m, z31.d
54 // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
55 // CHECK-ERROR: instruction requires: sve or sme
56 // CHECK-UNKNOWN: 65c0bfe4 <unknown>