[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / fsub.s
blob6b72bcfafb14372c87fc049bb82a8e4da01e985b
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 fsub z0.h, p0/m, z0.h, #0.500000000000000
13 // CHECK-INST: fsub z0.h, p0/m, z0.h, #0.5
14 // CHECK-ENCODING: [0x00,0x80,0x59,0x65]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 65598000 <unknown>
18 fsub z0.h, p0/m, z0.h, #0.5
19 // CHECK-INST: fsub z0.h, p0/m, z0.h, #0.5
20 // CHECK-ENCODING: [0x00,0x80,0x59,0x65]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 65598000 <unknown>
24 fsub z0.s, p0/m, z0.s, #0.5
25 // CHECK-INST: fsub z0.s, p0/m, z0.s, #0.5
26 // CHECK-ENCODING: [0x00,0x80,0x99,0x65]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 65998000 <unknown>
30 fsub z0.d, p0/m, z0.d, #0.5
31 // CHECK-INST: fsub z0.d, p0/m, z0.d, #0.5
32 // CHECK-ENCODING: [0x00,0x80,0xd9,0x65]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 65d98000 <unknown>
36 fsub z31.h, p7/m, z31.h, #1.000000000000000
37 // CHECK-INST: fsub z31.h, p7/m, z31.h, #1.0
38 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 65599c3f <unknown>
42 fsub z31.h, p7/m, z31.h, #1.0
43 // CHECK-INST: fsub z31.h, p7/m, z31.h, #1.0
44 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 65599c3f <unknown>
48 fsub z31.s, p7/m, z31.s, #1.0
49 // CHECK-INST: fsub z31.s, p7/m, z31.s, #1.0
50 // CHECK-ENCODING: [0x3f,0x9c,0x99,0x65]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 65999c3f <unknown>
54 fsub z31.d, p7/m, z31.d, #1.0
55 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0
56 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 65d99c3f <unknown>
60 fsub z0.h, p7/m, z0.h, z31.h
61 // CHECK-INST: fsub z0.h, p7/m, z0.h, z31.h
62 // CHECK-ENCODING: [0xe0,0x9f,0x41,0x65]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 65419fe0 <unknown>
66 fsub z0.s, p7/m, z0.s, z31.s
67 // CHECK-INST: fsub z0.s, p7/m, z0.s, z31.s
68 // CHECK-ENCODING: [0xe0,0x9f,0x81,0x65]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 65819fe0 <unknown>
72 fsub z0.d, p7/m, z0.d, z31.d
73 // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d
74 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 65c19fe0 <unknown>
78 fsub z0.h, z1.h, z31.h
79 // CHECK-INST: fsub z0.h, z1.h, z31.h
80 // CHECK-ENCODING: [0x20,0x04,0x5f,0x65]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 655f0420 <unknown>
84 fsub z0.s, z1.s, z31.s
85 // CHECK-INST: fsub z0.s, z1.s, z31.s
86 // CHECK-ENCODING: [0x20,0x04,0x9f,0x65]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: 659f0420 <unknown>
90 fsub z0.d, z1.d, z31.d
91 // CHECK-INST: fsub z0.d, z1.d, z31.d
92 // CHECK-ENCODING: [0x20,0x04,0xdf,0x65]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: 65df0420 <unknown>
97 // --------------------------------------------------------------------------//
98 // Test compatibility with MOVPRFX instruction.
100 movprfx z31.d, p7/z, z6.d
101 // CHECK-INST: movprfx z31.d, p7/z, z6.d
102 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
103 // CHECK-ERROR: instruction requires: sve or sme
104 // CHECK-UNKNOWN: 04d03cdf <unknown>
106 fsub z31.d, p7/m, z31.d, #1.0
107 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0
108 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
109 // CHECK-ERROR: instruction requires: sve or sme
110 // CHECK-UNKNOWN: 65d99c3f <unknown>
112 movprfx z31, z6
113 // CHECK-INST: movprfx z31, z6
114 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
115 // CHECK-ERROR: instruction requires: sve or sme
116 // CHECK-UNKNOWN: 0420bcdf <unknown>
118 fsub z31.d, p7/m, z31.d, #1.0
119 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0
120 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
121 // CHECK-ERROR: instruction requires: sve or sme
122 // CHECK-UNKNOWN: 65d99c3f <unknown>
124 movprfx z0.d, p7/z, z7.d
125 // CHECK-INST: movprfx z0.d, p7/z, z7.d
126 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
127 // CHECK-ERROR: instruction requires: sve or sme
128 // CHECK-UNKNOWN: 04d03ce0 <unknown>
130 fsub z0.d, p7/m, z0.d, z31.d
131 // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d
132 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
133 // CHECK-ERROR: instruction requires: sve or sme
134 // CHECK-UNKNOWN: 65c19fe0 <unknown>
136 movprfx z0, z7
137 // CHECK-INST: movprfx z0, z7
138 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
139 // CHECK-ERROR: instruction requires: sve or sme
140 // CHECK-UNKNOWN: 0420bce0 <unknown>
142 fsub z0.d, p7/m, z0.d, z31.d
143 // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d
144 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
145 // CHECK-ERROR: instruction requires: sve or sme
146 // CHECK-UNKNOWN: 65c19fe0 <unknown>