[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / ftssel.s
blobf631b667d761ac96ffe650f0b1bc9d8dd61561a7
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 ftssel z0.h, z1.h, z31.h
13 // CHECK-INST: ftssel z0.h, z1.h, z31.h
14 // CHECK-ENCODING: [0x20,0xb0,0x7f,0x04]
15 // CHECK-ERROR: instruction requires: sve
16 // CHECK-UNKNOWN: 047fb020 <unknown>
18 ftssel z0.s, z1.s, z31.s
19 // CHECK-INST: ftssel z0.s, z1.s, z31.s
20 // CHECK-ENCODING: [0x20,0xb0,0xbf,0x04]
21 // CHECK-ERROR: instruction requires: sve
22 // CHECK-UNKNOWN: 04bfb020 <unknown>
24 ftssel z0.d, z1.d, z31.d
25 // CHECK-INST: ftssel z0.d, z1.d, z31.d
26 // CHECK-ENCODING: [0x20,0xb0,0xff,0x04]
27 // CHECK-ERROR: instruction requires: sve
28 // CHECK-UNKNOWN: 04ffb020 <unknown>