[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / incp.s
blob03557f07b3b6f8bcfdd3d8747b44fa83f412c015
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 incp x0, p0.b
13 // CHECK-INST: incp x0, p0.b
14 // CHECK-ENCODING: [0x00,0x88,0x2c,0x25]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 252c8800 <unknown>
18 incp x0, p0.h
19 // CHECK-INST: incp x0, p0.h
20 // CHECK-ENCODING: [0x00,0x88,0x6c,0x25]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 256c8800 <unknown>
24 incp x0, p0.s
25 // CHECK-INST: incp x0, p0.s
26 // CHECK-ENCODING: [0x00,0x88,0xac,0x25]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 25ac8800 <unknown>
30 incp x0, p0.d
31 // CHECK-INST: incp x0, p0.d
32 // CHECK-ENCODING: [0x00,0x88,0xec,0x25]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 25ec8800 <unknown>
36 incp xzr, p15.b
37 // CHECK-INST: incp xzr, p15.b
38 // CHECK-ENCODING: [0xff,0x89,0x2c,0x25]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 252c89ff <unknown>
42 incp xzr, p15.h
43 // CHECK-INST: incp xzr, p15.h
44 // CHECK-ENCODING: [0xff,0x89,0x6c,0x25]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 256c89ff <unknown>
48 incp xzr, p15.s
49 // CHECK-INST: incp xzr, p15.s
50 // CHECK-ENCODING: [0xff,0x89,0xac,0x25]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 25ac89ff <unknown>
54 incp xzr, p15.d
55 // CHECK-INST: incp xzr, p15.d
56 // CHECK-ENCODING: [0xff,0x89,0xec,0x25]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 25ec89ff <unknown>
60 incp z31.h, p15
61 // CHECK-INST: incp z31.h, p15.h
62 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 256c81ff <unknown>
66 incp z31.h, p15.h
67 // CHECK-INST: incp z31.h, p15.h
68 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 256c81ff <unknown>
72 incp z31.s, p15
73 // CHECK-INST: incp z31.s, p15.s
74 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 25ac81ff <unknown>
78 incp z31.s, p15.s
79 // CHECK-INST: incp z31.s, p15.s
80 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 25ac81ff <unknown>
84 incp z31.d, p15
85 // CHECK-INST: incp z31.d, p15.d
86 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: 25ec81ff <unknown>
90 incp z31.d, p15.d
91 // CHECK-INST: incp z31.d, p15.d
92 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: 25ec81ff <unknown>
97 // --------------------------------------------------------------------------//
98 // Test compatibility with MOVPRFX instruction.
100 movprfx z31, z6
101 // CHECK-INST: movprfx z31, z6
102 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
103 // CHECK-ERROR: instruction requires: sve or sme
104 // CHECK-UNKNOWN: 0420bcdf <unknown>
106 incp z31.d, p15.d
107 // CHECK-INST: incp z31.d, p15.d
108 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
109 // CHECK-ERROR: instruction requires: sve or sme
110 // CHECK-UNKNOWN: 25ec81ff <unknown>