[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / ld1d-sve-only.s
blobf0887819fc1dd825b1815370994a3c01eb5c1bff
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 // Test instruction variants that aren't legal in streaming mode.
14 ld1d { z31.d }, p7/z, [sp, z31.d]
15 // CHECK-INST: ld1d { z31.d }, p7/z, [sp, z31.d]
16 // CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
17 // CHECK-ERROR: instruction requires: sve
18 // CHECK-UNKNOWN: c5dfdfff <unknown>
20 ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
21 // CHECK-INST: ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
22 // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
23 // CHECK-ERROR: instruction requires: sve
24 // CHECK-UNKNOWN: c5e8cdb7 <unknown>
26 ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
27 // CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
28 // CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
29 // CHECK-ERROR: instruction requires: sve
30 // CHECK-UNKNOWN: c5955555 <unknown>
32 ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
33 // CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
34 // CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
35 // CHECK-ERROR: instruction requires: sve
36 // CHECK-UNKNOWN: c5d55555 <unknown>
38 ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
39 // CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
40 // CHECK-ENCODING: [0x00,0x40,0xa0,0xc5]
41 // CHECK-ERROR: instruction requires: sve
42 // CHECK-UNKNOWN: c5a04000 <unknown>
44 ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
45 // CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
46 // CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
47 // CHECK-ERROR: instruction requires: sve
48 // CHECK-UNKNOWN: c5e04000 <unknown>
50 ld1d { z31.d }, p7/z, [z31.d, #248]
51 // CHECK-INST: ld1d { z31.d }, p7/z, [z31.d, #248]
52 // CHECK-ENCODING: [0xff,0xdf,0xbf,0xc5]
53 // CHECK-ERROR: instruction requires: sve
54 // CHECK-UNKNOWN: c5bfdfff <unknown>
56 ld1d { z0.d }, p0/z, [z0.d]
57 // CHECK-INST: ld1d { z0.d }, p0/z, [z0.d]
58 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xc5]
59 // CHECK-ERROR: instruction requires: sve
60 // CHECK-UNKNOWN: c5a0c000 <unknown>