[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / ld4h.s
blobacaf06dde2aa57eca1455e849b72ffd01a62792e
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
13 // CHECK-INST: ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
14 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa4]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: a4e0c000 <unknown>
18 ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
19 // CHECK-INST: ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
20 // CHECK-ENCODING: [0x25,0xce,0xf0,0xa4]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: a4f0ce25 <unknown>
24 ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
25 // CHECK-INST: ld4h { z0.h - z3.h }, p0/z, [x0]
26 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa4]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: a4e0e000 <unknown>
30 ld4h { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
31 // CHECK-INST: ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
32 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa4]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: a4e8edb7 <unknown>
36 ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
37 // CHECK-INST: ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
38 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa4]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: a4e5f555 <unknown>
42 ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]
43 // CHECK-INST: ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]
44 // CHECK-ENCODING: [0x5f,0xf5,0xe5,0xa4]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: a4e5f55f <unknown>