[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / ldnt1d.s
blob4e2971792324d4822c4d2bfc980d133eb837e41c
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 ldnt1d z0.d, p0/z, [x0]
13 // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0]
14 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: a580e000 <unknown>
18 ldnt1d { z0.d }, p0/z, [x0]
19 // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0]
20 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: a580e000 <unknown>
24 ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
25 // CHECK-INST: ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
26 // CHECK-ENCODING: [0xb7,0xed,0x88,0xa5]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: a588edb7 <unknown>
30 ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
31 // CHECK-INST: ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
32 // CHECK-ENCODING: [0x55,0xf5,0x87,0xa5]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: a587f555 <unknown>
36 ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
37 // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
38 // CHECK-ENCODING: [0x00,0xc0,0x80,0xa5]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: a580c000 <unknown>