[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / ldnt1h.s
blob9a96e80ed1dd8589982ce9c88e12bd9c86181c5f
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 ldnt1h z0.h, p0/z, [x0]
13 // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0]
14 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: a480e000 <unknown>
18 ldnt1h { z0.h }, p0/z, [x0]
19 // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0]
20 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: a480e000 <unknown>
24 ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
25 // CHECK-INST: ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
26 // CHECK-ENCODING: [0xb7,0xed,0x88,0xa4]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: a488edb7 <unknown>
30 ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
31 // CHECK-INST: ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
32 // CHECK-ENCODING: [0x55,0xf5,0x87,0xa4]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: a487f555 <unknown>
36 ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
37 // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
38 // CHECK-ENCODING: [0x00,0xc0,0x80,0xa4]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: a480c000 <unknown>