[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / lsr.s
blob72bb652679dfea3e55893e0090c27130e240239e
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 lsr z0.b, z0.b, #1
13 // CHECK-INST: lsr z0.b, z0.b, #1
14 // CHECK-ENCODING: [0x00,0x94,0x2f,0x04]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 042f9400 <unknown>
18 lsr z31.b, z31.b, #8
19 // CHECK-INST: lsr z31.b, z31.b, #8
20 // CHECK-ENCODING: [0xff,0x97,0x28,0x04]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 042897ff <unknown>
24 lsr z0.h, z0.h, #1
25 // CHECK-INST: lsr z0.h, z0.h, #1
26 // CHECK-ENCODING: [0x00,0x94,0x3f,0x04]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 043f9400 <unknown>
30 lsr z31.h, z31.h, #16
31 // CHECK-INST: lsr z31.h, z31.h, #16
32 // CHECK-ENCODING: [0xff,0x97,0x30,0x04]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 043097ff <unknown>
36 lsr z0.s, z0.s, #1
37 // CHECK-INST: lsr z0.s, z0.s, #1
38 // CHECK-ENCODING: [0x00,0x94,0x7f,0x04]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: 047f9400 <unknown>
42 lsr z31.s, z31.s, #32
43 // CHECK-INST: lsr z31.s, z31.s, #32
44 // CHECK-ENCODING: [0xff,0x97,0x60,0x04]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: 046097ff <unknown>
48 lsr z0.d, z0.d, #1
49 // CHECK-INST: lsr z0.d, z0.d, #1
50 // CHECK-ENCODING: [0x00,0x94,0xff,0x04]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: 04ff9400 <unknown>
54 lsr z31.d, z31.d, #64
55 // CHECK-INST: lsr z31.d, z31.d, #64
56 // CHECK-ENCODING: [0xff,0x97,0xa0,0x04]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: 04a097ff <unknown>
60 lsr z0.b, p0/m, z0.b, #1
61 // CHECK-INST: lsr z0.b, p0/m, z0.b, #1
62 // CHECK-ENCODING: [0xe0,0x81,0x01,0x04]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: 040181e0 <unknown>
66 lsr z31.b, p0/m, z31.b, #8
67 // CHECK-INST: lsr z31.b, p0/m, z31.b, #8
68 // CHECK-ENCODING: [0x1f,0x81,0x01,0x04]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: 0401811f <unknown>
72 lsr z0.h, p0/m, z0.h, #1
73 // CHECK-INST: lsr z0.h, p0/m, z0.h, #1
74 // CHECK-ENCODING: [0xe0,0x83,0x01,0x04]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: 040183e0 <unknown>
78 lsr z31.h, p0/m, z31.h, #16
79 // CHECK-INST: lsr z31.h, p0/m, z31.h, #16
80 // CHECK-ENCODING: [0x1f,0x82,0x01,0x04]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: 0401821f <unknown>
84 lsr z0.s, p0/m, z0.s, #1
85 // CHECK-INST: lsr z0.s, p0/m, z0.s, #1
86 // CHECK-ENCODING: [0xe0,0x83,0x41,0x04]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: 044183e0 <unknown>
90 lsr z31.s, p0/m, z31.s, #32
91 // CHECK-INST: lsr z31.s, p0/m, z31.s, #32
92 // CHECK-ENCODING: [0x1f,0x80,0x41,0x04]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: 0441801f <unknown>
96 lsr z0.d, p0/m, z0.d, #1
97 // CHECK-INST: lsr z0.d, p0/m, z0.d, #1
98 // CHECK-ENCODING: [0xe0,0x83,0xc1,0x04]
99 // CHECK-ERROR: instruction requires: sve or sme
100 // CHECK-UNKNOWN: 04c183e0 <unknown>
102 lsr z31.d, p0/m, z31.d, #64
103 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64
104 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
105 // CHECK-ERROR: instruction requires: sve or sme
106 // CHECK-UNKNOWN: 0481801f <unknown>
108 lsr z0.b, p0/m, z0.b, z0.b
109 // CHECK-INST: lsr z0.b, p0/m, z0.b, z0.b
110 // CHECK-ENCODING: [0x00,0x80,0x11,0x04]
111 // CHECK-ERROR: instruction requires: sve or sme
112 // CHECK-UNKNOWN: 04118000 <unknown>
114 lsr z0.h, p0/m, z0.h, z0.h
115 // CHECK-INST: lsr z0.h, p0/m, z0.h, z0.h
116 // CHECK-ENCODING: [0x00,0x80,0x51,0x04]
117 // CHECK-ERROR: instruction requires: sve or sme
118 // CHECK-UNKNOWN: 04518000 <unknown>
120 lsr z0.s, p0/m, z0.s, z0.s
121 // CHECK-INST: lsr z0.s, p0/m, z0.s, z0.s
122 // CHECK-ENCODING: [0x00,0x80,0x91,0x04]
123 // CHECK-ERROR: instruction requires: sve or sme
124 // CHECK-UNKNOWN: 04918000 <unknown>
126 lsr z0.d, p0/m, z0.d, z0.d
127 // CHECK-INST: lsr z0.d, p0/m, z0.d, z0.d
128 // CHECK-ENCODING: [0x00,0x80,0xd1,0x04]
129 // CHECK-ERROR: instruction requires: sve or sme
130 // CHECK-UNKNOWN: 04d18000 <unknown>
132 lsr z0.b, p0/m, z0.b, z1.d
133 // CHECK-INST: lsr z0.b, p0/m, z0.b, z1.d
134 // CHECK-ENCODING: [0x20,0x80,0x19,0x04]
135 // CHECK-ERROR: instruction requires: sve or sme
136 // CHECK-UNKNOWN: 04198020 <unknown>
138 lsr z0.h, p0/m, z0.h, z1.d
139 // CHECK-INST: lsr z0.h, p0/m, z0.h, z1.d
140 // CHECK-ENCODING: [0x20,0x80,0x59,0x04]
141 // CHECK-ERROR: instruction requires: sve or sme
142 // CHECK-UNKNOWN: 04598020 <unknown>
144 lsr z0.s, p0/m, z0.s, z1.d
145 // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d
146 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
147 // CHECK-ERROR: instruction requires: sve or sme
148 // CHECK-UNKNOWN: 04998020 <unknown>
150 lsr z0.b, z1.b, z2.d
151 // CHECK-INST: lsr z0.b, z1.b, z2.d
152 // CHECK-ENCODING: [0x20,0x84,0x22,0x04]
153 // CHECK-ERROR: instruction requires: sve or sme
154 // CHECK-UNKNOWN: 04228420 <unknown>
156 lsr z0.h, z1.h, z2.d
157 // CHECK-INST: lsr z0.h, z1.h, z2.d
158 // CHECK-ENCODING: [0x20,0x84,0x62,0x04]
159 // CHECK-ERROR: instruction requires: sve or sme
160 // CHECK-UNKNOWN: 04628420 <unknown>
162 lsr z0.s, z1.s, z2.d
163 // CHECK-INST: lsr z0.s, z1.s, z2.d
164 // CHECK-ENCODING: [0x20,0x84,0xa2,0x04]
165 // CHECK-ERROR: instruction requires: sve or sme
166 // CHECK-UNKNOWN: 04a28420 <unknown>
169 // --------------------------------------------------------------------------//
170 // Test compatibility with MOVPRFX instruction.
172 movprfx z31.d, p0/z, z6.d
173 // CHECK-INST: movprfx z31.d, p0/z, z6.d
174 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
175 // CHECK-ERROR: instruction requires: sve or sme
176 // CHECK-UNKNOWN: 04d020df <unknown>
178 lsr z31.d, p0/m, z31.d, #64
179 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64
180 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
181 // CHECK-ERROR: instruction requires: sve or sme
182 // CHECK-UNKNOWN: 0481801f <unknown>
184 movprfx z31, z6
185 // CHECK-INST: movprfx z31, z6
186 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
187 // CHECK-ERROR: instruction requires: sve or sme
188 // CHECK-UNKNOWN: 0420bcdf <unknown>
190 lsr z31.d, p0/m, z31.d, #64
191 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64
192 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
193 // CHECK-ERROR: instruction requires: sve or sme
194 // CHECK-UNKNOWN: 0481801f <unknown>
196 movprfx z0.s, p0/z, z7.s
197 // CHECK-INST: movprfx z0.s, p0/z, z7.s
198 // CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
199 // CHECK-ERROR: instruction requires: sve or sme
200 // CHECK-UNKNOWN: 049020e0 <unknown>
202 lsr z0.s, p0/m, z0.s, z1.d
203 // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d
204 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
205 // CHECK-ERROR: instruction requires: sve or sme
206 // CHECK-UNKNOWN: 04998020 <unknown>
208 movprfx z0, z7
209 // CHECK-INST: movprfx z0, z7
210 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
211 // CHECK-ERROR: instruction requires: sve or sme
212 // CHECK-UNKNOWN: 0420bce0 <unknown>
214 lsr z0.s, p0/m, z0.s, z1.d
215 // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d
216 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
217 // CHECK-ERROR: instruction requires: sve or sme
218 // CHECK-UNKNOWN: 04998020 <unknown>