llvm/test/MC/AArch64/SVE/movprfx.s

   1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
   2 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
   3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
   4 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
   5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
   6 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
   7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
   8 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
   9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
  10 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
  11
  12 // This test file is mostly empty because most 'movprfx' tests are embedded
  13 // with other instructions that are destructive and can be prefixed
  14 // by the movprfx instruction. A list of destructive instructions
  15 // is given below by their mnemonic, which have tests in corresponding
  16 // <mnemonic>.s test files:
  17 //
  18 // abs     decp    fdivr   fnmla   fsubr   mov     sdivr   sqincw  umulh
  19 // add     eon     fmad    fnmls   ftmad   msb     sdot    sqsub   uqadd
  20 // and     eor     fmax    fnmsb   incd    mul     smax    sub     uqdecd
  21 // asr     ext     fmaxnm  frecpx  inch    neg     smin    subr    uqdech
  22 // asrd    fabd    fmin    frinta  incp    not     smulh   sxtb    uqdecp
  23 // asrr    fabs    fminnm  frinti  incw    orn     splice  sxth    uqdecw
  24 // bic     fadd    fmla    frintm  insr    orr     sqadd   sxtw    uqincd
  25 // clasta  fcadd   fmls    frintn  lsl     rbit    sqdecd  uabd    uqinch
  26 // clastb  fcmla   fmov    frintp  lslr    revb    sqdech  ucvtf   uqincp
  27 // cls     fcpy    fmsb    frintx  lsr     revh    sqdecp  udiv    uqincw
  28 // clz     fcvt    fmul    frintz  lsrr    revw    sqdecw  udivr   uqsub
  29 // cnot    fcvtzs  fmulx   fscale  mad     sabd    sqincd  udot    uxtb
  30 // cnt     fcvtzu  fneg    fsqrt   mla     scvtf   sqinch  umax    uxth
  31 // cpy     fdiv    fnmad   fsub    mls     sdiv    sqincp  umin    uxtw
  32
  33
  34 // ------------------------------------------------------------------------- //
  35 // Test compatibility with MOVPRFX instruction with BRK and HLT.
  36 //
  37 // Section 7.1.2 of the SVE Architecture Reference Manual Supplement:
  38 //   "it is permitted to use MOVPRFX to prefix an A64 BRK or HLT instruction"
  39
  40 movprfx z0, z1
  41 // CHECK-INST: movprfx  z0, z1
  42 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
  43 // CHECK-ERROR: instruction requires: sve or sme
  44 // CHECK-UNKNOWN: 0420bc20 <unknown>
  45
  46 hlt #1
  47 // CHECK-INST: hlt      #0x1
  48 // CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
  49
  50 movprfx z0.d, p0/z, z1.d
  51 // CHECK-INST: movprfx  z0.d, p0/z, z1.d
  52 // CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
  53 // CHECK-ERROR: instruction requires: sve or sme
  54 // CHECK-UNKNOWN: 04d02020 <unknown>
  55
  56 hlt #1
  57 // CHECK-INST: hlt      #0x1
  58 // CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
  59
  60 movprfx z0, z1
  61 // CHECK-INST: movprfx  z0, z1
  62 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
  63 // CHECK-ERROR: instruction requires: sve or sme
  64 // CHECK-UNKNOWN: 0420bc20 <unknown>
  65
  66 brk #1
  67 // CHECK-INST: brk      #0x1
  68 // CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
  69
  70 movprfx z0.d, p0/z, z1.d
  71 // CHECK-INST: movprfx  z0.d, p0/z, z1.d
  72 // CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
  73 // CHECK-ERROR: instruction requires: sve or sme
  74 // CHECK-UNKNOWN: 04d02020 <unknown>
  75
  76 brk #1
  77 // CHECK-INST: brk      #0x1
  78 // CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
  79
  80 // ------------------------------------------------------------------------- //
  81 // Ensure we don't try to apply a prefix to subsequent instructions (upon success)
  82
  83 movprfx z0, z1
  84 // CHECK-INST: movprfx  z0, z1
  85 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
  86 // CHECK-ERROR: instruction requires: sve or sme
  87 // CHECK-UNKNOWN: 0420bc20 <unknown>
  88
  89 add z0.d, p0/m, z0.d, z1.d
  90 // CHECK-INST: add      z0.d, p0/m, z0.d, z1.d
  91 // CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
  92 // CHECK-ERROR: instruction requires: sve or sme
  93 // CHECK-UNKNOWN: 04c00020 <unknown>
  94
  95 add z0.d, p0/m, z0.d, z1.d
  96 // CHECK-INST: add      z0.d, p0/m, z0.d, z1.d
  97 // CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
  98 // CHECK-ERROR: instruction requires: sve or sme
  99 // CHECK-UNKNOWN: 04c00020 <unknown>