[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / movs.s
blob7124db150202a89fb41a4ae3f2012d86b219de9f
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 movs p0.b, p0.b
13 // CHECK-INST: movs p0.b, p0.b
14 // CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: 25c04000 <unknown>
18 movs p15.b, p15.b
19 // CHECK-INST: movs p15.b, p15.b
20 // CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: 25cf7def <unknown>
24 movs p0.b, p0/z, p0.b
25 // CHECK-INST: movs p0.b, p0/z, p0.b
26 // CHECK-ENCODING: [0x00,0x40,0x40,0x25]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: 25404000 <unknown>
30 movs p15.b, p15/z, p15.b
31 // CHECK-INST: movs p15.b, p15/z, p15.b
32 // CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: 254f7def <unknown>