[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / pfalse-diagnostics.s
blob4f2c22c4a88895df60f223514652bf30d37f218a
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Only .b is supported
7 pfalse p15.h
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
9 // CHECK-NEXT: pfalse p15.h
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 // Support until pn15.b
14 pfalse pn16.b
15 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
16 // CHECK-NEXT: pfalse pn16.b
17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: