[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / sqincd.s
blob0742de17a562ed70278acef654cdb6b02227cd26
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 // ---------------------------------------------------------------------------//
13 // Test 64-bit form (x0) and its aliases
14 // ---------------------------------------------------------------------------//
16 sqincd x0
17 // CHECK-INST: sqincd x0
18 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
19 // CHECK-ERROR: instruction requires: sve or sme
20 // CHECK-UNKNOWN: 04f0f3e0 <unknown>
22 sqincd x0, all
23 // CHECK-INST: sqincd x0
24 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
25 // CHECK-ERROR: instruction requires: sve or sme
26 // CHECK-UNKNOWN: 04f0f3e0 <unknown>
28 sqincd x0, all, mul #1
29 // CHECK-INST: sqincd x0
30 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
31 // CHECK-ERROR: instruction requires: sve or sme
32 // CHECK-UNKNOWN: 04f0f3e0 <unknown>
34 sqincd x0, all, mul #16
35 // CHECK-INST: sqincd x0, all, mul #16
36 // CHECK-ENCODING: [0xe0,0xf3,0xff,0x04]
37 // CHECK-ERROR: instruction requires: sve or sme
38 // CHECK-UNKNOWN: 04fff3e0 <unknown>
41 // ---------------------------------------------------------------------------//
42 // Test 32-bit form (x0, w0) and its aliases
43 // ---------------------------------------------------------------------------//
45 sqincd x0, w0
46 // CHECK-INST: sqincd x0, w0
47 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
48 // CHECK-ERROR: instruction requires: sve or sme
49 // CHECK-UNKNOWN: 04e0f3e0 <unknown>
51 sqincd x0, w0, all
52 // CHECK-INST: sqincd x0, w0
53 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
54 // CHECK-ERROR: instruction requires: sve or sme
55 // CHECK-UNKNOWN: 04e0f3e0 <unknown>
57 sqincd x0, w0, all, mul #1
58 // CHECK-INST: sqincd x0, w0
59 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
60 // CHECK-ERROR: instruction requires: sve or sme
61 // CHECK-UNKNOWN: 04e0f3e0 <unknown>
63 sqincd x0, w0, all, mul #16
64 // CHECK-INST: sqincd x0, w0, all
65 // CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
66 // CHECK-ERROR: instruction requires: sve or sme
67 // CHECK-UNKNOWN: 04eff3e0 <unknown>
69 sqincd x0, w0, pow2
70 // CHECK-INST: sqincd x0, w0, pow2
71 // CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
72 // CHECK-ERROR: instruction requires: sve or sme
73 // CHECK-UNKNOWN: 04e0f000 <unknown>
75 sqincd x0, w0, pow2, mul #16
76 // CHECK-INST: sqincd x0, w0, pow2, mul #16
77 // CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
78 // CHECK-ERROR: instruction requires: sve or sme
79 // CHECK-UNKNOWN: 04eff000 <unknown>
82 // ---------------------------------------------------------------------------//
83 // Test vector form and aliases.
84 // ---------------------------------------------------------------------------//
85 sqincd z0.d
86 // CHECK-INST: sqincd z0.d
87 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
88 // CHECK-ERROR: instruction requires: sve or sme
89 // CHECK-UNKNOWN: 04e0c3e0 <unknown>
91 sqincd z0.d, all
92 // CHECK-INST: sqincd z0.d
93 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
94 // CHECK-ERROR: instruction requires: sve or sme
95 // CHECK-UNKNOWN: 04e0c3e0 <unknown>
97 sqincd z0.d, all, mul #1
98 // CHECK-INST: sqincd z0.d
99 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
100 // CHECK-ERROR: instruction requires: sve or sme
101 // CHECK-UNKNOWN: 04e0c3e0 <unknown>
103 sqincd z0.d, all, mul #16
104 // CHECK-INST: sqincd z0.d, all, mul #16
105 // CHECK-ENCODING: [0xe0,0xc3,0xef,0x04]
106 // CHECK-ERROR: instruction requires: sve or sme
107 // CHECK-UNKNOWN: 04efc3e0 <unknown>
109 sqincd z0.d, pow2
110 // CHECK-INST: sqincd z0.d, pow2
111 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
112 // CHECK-ERROR: instruction requires: sve or sme
113 // CHECK-UNKNOWN: 04e0c000 <unknown>
115 sqincd z0.d, pow2, mul #16
116 // CHECK-INST: sqincd z0.d, pow2, mul #16
117 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
118 // CHECK-ERROR: instruction requires: sve or sme
119 // CHECK-UNKNOWN: 04efc000 <unknown>
122 // ---------------------------------------------------------------------------//
123 // Test all patterns for 64-bit form
124 // ---------------------------------------------------------------------------//
126 sqincd x0, pow2
127 // CHECK-INST: sqincd x0, pow2
128 // CHECK-ENCODING: [0x00,0xf0,0xf0,0x04]
129 // CHECK-ERROR: instruction requires: sve or sme
130 // CHECK-UNKNOWN: 04f0f000 <unknown>
132 sqincd x0, vl1
133 // CHECK-INST: sqincd x0, vl1
134 // CHECK-ENCODING: [0x20,0xf0,0xf0,0x04]
135 // CHECK-ERROR: instruction requires: sve or sme
136 // CHECK-UNKNOWN: 04f0f020 <unknown>
138 sqincd x0, vl2
139 // CHECK-INST: sqincd x0, vl2
140 // CHECK-ENCODING: [0x40,0xf0,0xf0,0x04]
141 // CHECK-ERROR: instruction requires: sve or sme
142 // CHECK-UNKNOWN: 04f0f040 <unknown>
144 sqincd x0, vl3
145 // CHECK-INST: sqincd x0, vl3
146 // CHECK-ENCODING: [0x60,0xf0,0xf0,0x04]
147 // CHECK-ERROR: instruction requires: sve or sme
148 // CHECK-UNKNOWN: 04f0f060 <unknown>
150 sqincd x0, vl4
151 // CHECK-INST: sqincd x0, vl4
152 // CHECK-ENCODING: [0x80,0xf0,0xf0,0x04]
153 // CHECK-ERROR: instruction requires: sve or sme
154 // CHECK-UNKNOWN: 04f0f080 <unknown>
156 sqincd x0, vl5
157 // CHECK-INST: sqincd x0, vl5
158 // CHECK-ENCODING: [0xa0,0xf0,0xf0,0x04]
159 // CHECK-ERROR: instruction requires: sve or sme
160 // CHECK-UNKNOWN: 04f0f0a0 <unknown>
162 sqincd x0, vl6
163 // CHECK-INST: sqincd x0, vl6
164 // CHECK-ENCODING: [0xc0,0xf0,0xf0,0x04]
165 // CHECK-ERROR: instruction requires: sve or sme
166 // CHECK-UNKNOWN: 04f0f0c0 <unknown>
168 sqincd x0, vl7
169 // CHECK-INST: sqincd x0, vl7
170 // CHECK-ENCODING: [0xe0,0xf0,0xf0,0x04]
171 // CHECK-ERROR: instruction requires: sve or sme
172 // CHECK-UNKNOWN: 04f0f0e0 <unknown>
174 sqincd x0, vl8
175 // CHECK-INST: sqincd x0, vl8
176 // CHECK-ENCODING: [0x00,0xf1,0xf0,0x04]
177 // CHECK-ERROR: instruction requires: sve or sme
178 // CHECK-UNKNOWN: 04f0f100 <unknown>
180 sqincd x0, vl16
181 // CHECK-INST: sqincd x0, vl16
182 // CHECK-ENCODING: [0x20,0xf1,0xf0,0x04]
183 // CHECK-ERROR: instruction requires: sve or sme
184 // CHECK-UNKNOWN: 04f0f120 <unknown>
186 sqincd x0, vl32
187 // CHECK-INST: sqincd x0, vl32
188 // CHECK-ENCODING: [0x40,0xf1,0xf0,0x04]
189 // CHECK-ERROR: instruction requires: sve or sme
190 // CHECK-UNKNOWN: 04f0f140 <unknown>
192 sqincd x0, vl64
193 // CHECK-INST: sqincd x0, vl64
194 // CHECK-ENCODING: [0x60,0xf1,0xf0,0x04]
195 // CHECK-ERROR: instruction requires: sve or sme
196 // CHECK-UNKNOWN: 04f0f160 <unknown>
198 sqincd x0, vl128
199 // CHECK-INST: sqincd x0, vl128
200 // CHECK-ENCODING: [0x80,0xf1,0xf0,0x04]
201 // CHECK-ERROR: instruction requires: sve or sme
202 // CHECK-UNKNOWN: 04f0f180 <unknown>
204 sqincd x0, vl256
205 // CHECK-INST: sqincd x0, vl256
206 // CHECK-ENCODING: [0xa0,0xf1,0xf0,0x04]
207 // CHECK-ERROR: instruction requires: sve or sme
208 // CHECK-UNKNOWN: 04f0f1a0 <unknown>
210 sqincd x0, #14
211 // CHECK-INST: sqincd x0, #14
212 // CHECK-ENCODING: [0xc0,0xf1,0xf0,0x04]
213 // CHECK-ERROR: instruction requires: sve or sme
214 // CHECK-UNKNOWN: 04f0f1c0 <unknown>
216 sqincd x0, #15
217 // CHECK-INST: sqincd x0, #15
218 // CHECK-ENCODING: [0xe0,0xf1,0xf0,0x04]
219 // CHECK-ERROR: instruction requires: sve or sme
220 // CHECK-UNKNOWN: 04f0f1e0 <unknown>
222 sqincd x0, #16
223 // CHECK-INST: sqincd x0, #16
224 // CHECK-ENCODING: [0x00,0xf2,0xf0,0x04]
225 // CHECK-ERROR: instruction requires: sve or sme
226 // CHECK-UNKNOWN: 04f0f200 <unknown>
228 sqincd x0, #17
229 // CHECK-INST: sqincd x0, #17
230 // CHECK-ENCODING: [0x20,0xf2,0xf0,0x04]
231 // CHECK-ERROR: instruction requires: sve or sme
232 // CHECK-UNKNOWN: 04f0f220 <unknown>
234 sqincd x0, #18
235 // CHECK-INST: sqincd x0, #18
236 // CHECK-ENCODING: [0x40,0xf2,0xf0,0x04]
237 // CHECK-ERROR: instruction requires: sve or sme
238 // CHECK-UNKNOWN: 04f0f240 <unknown>
240 sqincd x0, #19
241 // CHECK-INST: sqincd x0, #19
242 // CHECK-ENCODING: [0x60,0xf2,0xf0,0x04]
243 // CHECK-ERROR: instruction requires: sve or sme
244 // CHECK-UNKNOWN: 04f0f260 <unknown>
246 sqincd x0, #20
247 // CHECK-INST: sqincd x0, #20
248 // CHECK-ENCODING: [0x80,0xf2,0xf0,0x04]
249 // CHECK-ERROR: instruction requires: sve or sme
250 // CHECK-UNKNOWN: 04f0f280 <unknown>
252 sqincd x0, #21
253 // CHECK-INST: sqincd x0, #21
254 // CHECK-ENCODING: [0xa0,0xf2,0xf0,0x04]
255 // CHECK-ERROR: instruction requires: sve or sme
256 // CHECK-UNKNOWN: 04f0f2a0 <unknown>
258 sqincd x0, #22
259 // CHECK-INST: sqincd x0, #22
260 // CHECK-ENCODING: [0xc0,0xf2,0xf0,0x04]
261 // CHECK-ERROR: instruction requires: sve or sme
262 // CHECK-UNKNOWN: 04f0f2c0 <unknown>
264 sqincd x0, #23
265 // CHECK-INST: sqincd x0, #23
266 // CHECK-ENCODING: [0xe0,0xf2,0xf0,0x04]
267 // CHECK-ERROR: instruction requires: sve or sme
268 // CHECK-UNKNOWN: 04f0f2e0 <unknown>
270 sqincd x0, #24
271 // CHECK-INST: sqincd x0, #24
272 // CHECK-ENCODING: [0x00,0xf3,0xf0,0x04]
273 // CHECK-ERROR: instruction requires: sve or sme
274 // CHECK-UNKNOWN: 04f0f300 <unknown>
276 sqincd x0, #25
277 // CHECK-INST: sqincd x0, #25
278 // CHECK-ENCODING: [0x20,0xf3,0xf0,0x04]
279 // CHECK-ERROR: instruction requires: sve or sme
280 // CHECK-UNKNOWN: 04f0f320 <unknown>
282 sqincd x0, #26
283 // CHECK-INST: sqincd x0, #26
284 // CHECK-ENCODING: [0x40,0xf3,0xf0,0x04]
285 // CHECK-ERROR: instruction requires: sve or sme
286 // CHECK-UNKNOWN: 04f0f340 <unknown>
288 sqincd x0, #27
289 // CHECK-INST: sqincd x0, #27
290 // CHECK-ENCODING: [0x60,0xf3,0xf0,0x04]
291 // CHECK-ERROR: instruction requires: sve or sme
292 // CHECK-UNKNOWN: 04f0f360 <unknown>
294 sqincd x0, #28
295 // CHECK-INST: sqincd x0, #28
296 // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04]
297 // CHECK-ERROR: instruction requires: sve or sme
298 // CHECK-UNKNOWN: 04f0f380 <unknown>
301 // --------------------------------------------------------------------------//
302 // Test compatibility with MOVPRFX instruction.
304 movprfx z0, z7
305 // CHECK-INST: movprfx z0, z7
306 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
307 // CHECK-ERROR: instruction requires: sve or sme
308 // CHECK-UNKNOWN: 0420bce0 <unknown>
310 sqincd z0.d
311 // CHECK-INST: sqincd z0.d
312 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
313 // CHECK-ERROR: instruction requires: sve or sme
314 // CHECK-UNKNOWN: 04e0c3e0 <unknown>
316 movprfx z0, z7
317 // CHECK-INST: movprfx z0, z7
318 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
319 // CHECK-ERROR: instruction requires: sve or sme
320 // CHECK-UNKNOWN: 0420bce0 <unknown>
322 sqincd z0.d, pow2, mul #16
323 // CHECK-INST: sqincd z0.d, pow2, mul #16
324 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
325 // CHECK-ERROR: instruction requires: sve or sme
326 // CHECK-UNKNOWN: 04efc000 <unknown>
328 movprfx z0, z7
329 // CHECK-INST: movprfx z0, z7
330 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
331 // CHECK-ERROR: instruction requires: sve or sme
332 // CHECK-UNKNOWN: 0420bce0 <unknown>
334 sqincd z0.d, pow2
335 // CHECK-INST: sqincd z0.d, pow2
336 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
337 // CHECK-ERROR: instruction requires: sve or sme
338 // CHECK-UNKNOWN: 04e0c000 <unknown>