[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / st1b.s
blobe122b3c44cbb064dc1828d9d91c72167add450cb
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 st1b z0.b, p0, [x0]
13 // CHECK-INST: st1b { z0.b }, p0, [x0]
14 // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: e400e000 <unknown>
18 st1b z0.h, p0, [x0]
19 // CHECK-INST: st1b { z0.h }, p0, [x0]
20 // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: e420e000 <unknown>
24 st1b z0.s, p0, [x0]
25 // CHECK-INST: st1b { z0.s }, p0, [x0]
26 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: e440e000 <unknown>
30 st1b z0.d, p0, [x0]
31 // CHECK-INST: st1b { z0.d }, p0, [x0]
32 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: e460e000 <unknown>
36 st1b { z0.b }, p0, [x0]
37 // CHECK-INST: st1b { z0.b }, p0, [x0]
38 // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: e400e000 <unknown>
42 st1b { z0.h }, p0, [x0]
43 // CHECK-INST: st1b { z0.h }, p0, [x0]
44 // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: e420e000 <unknown>
48 st1b { z0.s }, p0, [x0]
49 // CHECK-INST: st1b { z0.s }, p0, [x0]
50 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: e440e000 <unknown>
54 st1b { z0.d }, p0, [x0]
55 // CHECK-INST: st1b { z0.d }, p0, [x0]
56 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: e460e000 <unknown>
60 st1b { z31.b }, p7, [sp, #-1, mul vl]
61 // CHECK-INST: st1b { z31.b }, p7, [sp, #-1, mul vl]
62 // CHECK-ENCODING: [0xff,0xff,0x0f,0xe4]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: e40fffff <unknown>
66 st1b { z21.b }, p5, [x10, #5, mul vl]
67 // CHECK-INST: st1b { z21.b }, p5, [x10, #5, mul vl]
68 // CHECK-ENCODING: [0x55,0xf5,0x05,0xe4]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: e405f555 <unknown>
72 st1b { z31.h }, p7, [sp, #-1, mul vl]
73 // CHECK-INST: st1b { z31.h }, p7, [sp, #-1, mul vl]
74 // CHECK-ENCODING: [0xff,0xff,0x2f,0xe4]
75 // CHECK-ERROR: instruction requires: sve or sme
76 // CHECK-UNKNOWN: e42fffff <unknown>
78 st1b { z21.h }, p5, [x10, #5, mul vl]
79 // CHECK-INST: st1b { z21.h }, p5, [x10, #5, mul vl]
80 // CHECK-ENCODING: [0x55,0xf5,0x25,0xe4]
81 // CHECK-ERROR: instruction requires: sve or sme
82 // CHECK-UNKNOWN: e425f555 <unknown>
84 st1b { z31.s }, p7, [sp, #-1, mul vl]
85 // CHECK-INST: st1b { z31.s }, p7, [sp, #-1, mul vl]
86 // CHECK-ENCODING: [0xff,0xff,0x4f,0xe4]
87 // CHECK-ERROR: instruction requires: sve or sme
88 // CHECK-UNKNOWN: e44fffff <unknown>
90 st1b { z21.s }, p5, [x10, #5, mul vl]
91 // CHECK-INST: st1b { z21.s }, p5, [x10, #5, mul vl]
92 // CHECK-ENCODING: [0x55,0xf5,0x45,0xe4]
93 // CHECK-ERROR: instruction requires: sve or sme
94 // CHECK-UNKNOWN: e445f555 <unknown>
96 st1b { z31.d }, p7, [sp, #-1, mul vl]
97 // CHECK-INST: st1b { z31.d }, p7, [sp, #-1, mul vl]
98 // CHECK-ENCODING: [0xff,0xff,0x6f,0xe4]
99 // CHECK-ERROR: instruction requires: sve or sme
100 // CHECK-UNKNOWN: e46fffff <unknown>
102 st1b { z21.d }, p5, [x10, #5, mul vl]
103 // CHECK-INST: st1b { z21.d }, p5, [x10, #5, mul vl]
104 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe4]
105 // CHECK-ERROR: instruction requires: sve or sme
106 // CHECK-UNKNOWN: e465f555 <unknown>
108 st1b { z0.b }, p0, [x0, x0]
109 // CHECK-INST: st1b { z0.b }, p0, [x0, x0]
110 // CHECK-ENCODING: [0x00,0x40,0x00,0xe4]
111 // CHECK-ERROR: instruction requires: sve or sme
112 // CHECK-UNKNOWN: e4004000 <unknown>
114 st1b { z0.h }, p0, [x0, x0]
115 // CHECK-INST: st1b { z0.h }, p0, [x0, x0]
116 // CHECK-ENCODING: [0x00,0x40,0x20,0xe4]
117 // CHECK-ERROR: instruction requires: sve or sme
118 // CHECK-UNKNOWN: e4204000 <unknown>
120 st1b { z0.s }, p0, [x0, x0]
121 // CHECK-INST: st1b { z0.s }, p0, [x0, x0]
122 // CHECK-ENCODING: [0x00,0x40,0x40,0xe4]
123 // CHECK-ERROR: instruction requires: sve or sme
124 // CHECK-UNKNOWN: e4404000 <unknown>
126 st1b { z0.d }, p0, [x0, x0]
127 // CHECK-INST: st1b { z0.d }, p0, [x0, x0]
128 // CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
129 // CHECK-ERROR: instruction requires: sve or sme
130 // CHECK-UNKNOWN: e4604000 <unknown>