[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / st1h-sve-only.s
blobaa6eea4710fc045a3a29d4e046c980b7d13c96e7
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 // Test instruction variants that aren't legal in streaming mode.
14 st1h { z0.s }, p0, [x0, z0.s, uxtw]
15 // CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, uxtw]
16 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe4]
17 // CHECK-ERROR: instruction requires: sve
18 // CHECK-UNKNOWN: e4c08000 <unknown>
20 st1h { z0.s }, p0, [x0, z0.s, sxtw]
21 // CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, sxtw]
22 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xe4]
23 // CHECK-ERROR: instruction requires: sve
24 // CHECK-UNKNOWN: e4c0c000 <unknown>
26 st1h { z0.d }, p0, [x0, z0.d, uxtw]
27 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, uxtw]
28 // CHECK-ENCODING: [0x00,0x80,0x80,0xe4]
29 // CHECK-ERROR: instruction requires: sve
30 // CHECK-UNKNOWN: e4808000 <unknown>
32 st1h { z0.d }, p0, [x0, z0.d, sxtw]
33 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, sxtw]
34 // CHECK-ENCODING: [0x00,0xc0,0x80,0xe4]
35 // CHECK-ERROR: instruction requires: sve
36 // CHECK-UNKNOWN: e480c000 <unknown>
38 st1h { z0.s }, p0, [x0, z0.s, uxtw #1]
39 // CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, uxtw #1]
40 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe4]
41 // CHECK-ERROR: instruction requires: sve
42 // CHECK-UNKNOWN: e4e08000 <unknown>
44 st1h { z0.s }, p0, [x0, z0.s, sxtw #1]
45 // CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, sxtw #1]
46 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xe4]
47 // CHECK-ERROR: instruction requires: sve
48 // CHECK-UNKNOWN: e4e0c000 <unknown>
50 st1h { z0.d }, p0, [x0, z0.d, uxtw #1]
51 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, uxtw #1]
52 // CHECK-ENCODING: [0x00,0x80,0xa0,0xe4]
53 // CHECK-ERROR: instruction requires: sve
54 // CHECK-UNKNOWN: e4a08000 <unknown>
56 st1h { z0.d }, p0, [x0, z0.d, sxtw #1]
57 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, sxtw #1]
58 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xe4]
59 // CHECK-ERROR: instruction requires: sve
60 // CHECK-UNKNOWN: e4a0c000 <unknown>
62 st1h { z0.d }, p0, [x0, z0.d]
63 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d]
64 // CHECK-ENCODING: [0x00,0xa0,0x80,0xe4]
65 // CHECK-ERROR: instruction requires: sve
66 // CHECK-UNKNOWN: e480a000 <unknown>
68 st1h { z0.d }, p0, [x0, z0.d, lsl #1]
69 // CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, lsl #1]
70 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xe4]
71 // CHECK-ERROR: instruction requires: sve
72 // CHECK-UNKNOWN: e4a0a000 <unknown>
74 st1h { z31.s }, p7, [z31.s, #62]
75 // CHECK-INST: st1h { z31.s }, p7, [z31.s, #62]
76 // CHECK-ENCODING: [0xff,0xbf,0xff,0xe4]
77 // CHECK-ERROR: instruction requires: sve
78 // CHECK-UNKNOWN: e4ffbfff <unknown>
80 st1h { z31.d }, p7, [z31.d, #62]
81 // CHECK-INST: st1h { z31.d }, p7, [z31.d, #62]
82 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
83 // CHECK-ERROR: instruction requires: sve
84 // CHECK-UNKNOWN: e4dfbfff <unknown>
86 st1h { z0.s }, p7, [z0.s, #0]
87 // CHECK-INST: st1h { z0.s }, p7, [z0.s]
88 // CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
89 // CHECK-ERROR: instruction requires: sve
90 // CHECK-UNKNOWN: e4e0bc00 <unknown>
92 st1h { z0.s }, p7, [z0.s]
93 // CHECK-INST: st1h { z0.s }, p7, [z0.s]
94 // CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
95 // CHECK-ERROR: instruction requires: sve
96 // CHECK-UNKNOWN: e4e0bc00 <unknown>
98 st1h { z0.d }, p7, [z0.d, #0]
99 // CHECK-INST: st1h { z0.d }, p7, [z0.d]
100 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
101 // CHECK-ERROR: instruction requires: sve
102 // CHECK-UNKNOWN: e4c0bc00 <unknown>
104 st1h { z0.d }, p7, [z0.d]
105 // CHECK-INST: st1h { z0.d }, p7, [z0.d]
106 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
107 // CHECK-ERROR: instruction requires: sve
108 // CHECK-UNKNOWN: e4c0bc00 <unknown>