[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / st1w.s
blob3c35cbea1ec24df4bd5822eaa80897bc7a7e08ac
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 st1w z0.s, p0, [x0]
13 // CHECK-INST: st1w { z0.s }, p0, [x0]
14 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5]
15 // CHECK-ERROR: instruction requires: sve or sme
16 // CHECK-UNKNOWN: e540e000 <unknown>
18 st1w z0.d, p0, [x0]
19 // CHECK-INST: st1w { z0.d }, p0, [x0]
20 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5]
21 // CHECK-ERROR: instruction requires: sve or sme
22 // CHECK-UNKNOWN: e560e000 <unknown>
24 st1w { z0.s }, p0, [x0]
25 // CHECK-INST: st1w { z0.s }, p0, [x0]
26 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5]
27 // CHECK-ERROR: instruction requires: sve or sme
28 // CHECK-UNKNOWN: e540e000 <unknown>
30 st1w { z0.d }, p0, [x0]
31 // CHECK-INST: st1w { z0.d }, p0, [x0]
32 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5]
33 // CHECK-ERROR: instruction requires: sve or sme
34 // CHECK-UNKNOWN: e560e000 <unknown>
36 st1w { z31.s }, p7, [sp, #-1, mul vl]
37 // CHECK-INST: st1w { z31.s }, p7, [sp, #-1, mul vl]
38 // CHECK-ENCODING: [0xff,0xff,0x4f,0xe5]
39 // CHECK-ERROR: instruction requires: sve or sme
40 // CHECK-UNKNOWN: e54fffff <unknown>
42 st1w { z21.s }, p5, [x10, #5, mul vl]
43 // CHECK-INST: st1w { z21.s }, p5, [x10, #5, mul vl]
44 // CHECK-ENCODING: [0x55,0xf5,0x45,0xe5]
45 // CHECK-ERROR: instruction requires: sve or sme
46 // CHECK-UNKNOWN: e545f555 <unknown>
48 st1w { z31.d }, p7, [sp, #-1, mul vl]
49 // CHECK-INST: st1w { z31.d }, p7, [sp, #-1, mul vl]
50 // CHECK-ENCODING: [0xff,0xff,0x6f,0xe5]
51 // CHECK-ERROR: instruction requires: sve or sme
52 // CHECK-UNKNOWN: e56fffff <unknown>
54 st1w { z21.d }, p5, [x10, #5, mul vl]
55 // CHECK-INST: st1w { z21.d }, p5, [x10, #5, mul vl]
56 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe5]
57 // CHECK-ERROR: instruction requires: sve or sme
58 // CHECK-UNKNOWN: e565f555 <unknown>
60 st1w { z0.s }, p0, [x0, x0, lsl #2]
61 // CHECK-INST: st1w { z0.s }, p0, [x0, x0, lsl #2]
62 // CHECK-ENCODING: [0x00,0x40,0x40,0xe5]
63 // CHECK-ERROR: instruction requires: sve or sme
64 // CHECK-UNKNOWN: e5404000 <unknown>
66 st1w { z0.d }, p0, [x0, x0, lsl #2]
67 // CHECK-INST: st1w { z0.d }, p0, [x0, x0, lsl #2]
68 // CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
69 // CHECK-ERROR: instruction requires: sve or sme
70 // CHECK-UNKNOWN: e5604000 <unknown>