[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE / uqdecd.s
blob027c959935c7d9f2609c6b7278798e9d63665e53
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
13 // ---------------------------------------------------------------------------//
14 // Test 64-bit form (x0) and its aliases
15 // ---------------------------------------------------------------------------//
16 uqdecd x0
17 // CHECK-INST: uqdecd x0
18 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
19 // CHECK-ERROR: instruction requires: sve or sme
20 // CHECK-UNKNOWN: 04f0ffe0 <unknown>
22 uqdecd x0, all
23 // CHECK-INST: uqdecd x0
24 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
25 // CHECK-ERROR: instruction requires: sve or sme
26 // CHECK-UNKNOWN: 04f0ffe0 <unknown>
28 uqdecd x0, all, mul #1
29 // CHECK-INST: uqdecd x0
30 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
31 // CHECK-ERROR: instruction requires: sve or sme
32 // CHECK-UNKNOWN: 04f0ffe0 <unknown>
34 uqdecd x0, all, mul #16
35 // CHECK-INST: uqdecd x0, all, mul #16
36 // CHECK-ENCODING: [0xe0,0xff,0xff,0x04]
37 // CHECK-ERROR: instruction requires: sve or sme
38 // CHECK-UNKNOWN: 04ffffe0 <unknown>
41 // ---------------------------------------------------------------------------//
42 // Test 32-bit form (w0) and its aliases
43 // ---------------------------------------------------------------------------//
45 uqdecd w0
46 // CHECK-INST: uqdecd w0
47 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
48 // CHECK-ERROR: instruction requires: sve or sme
49 // CHECK-UNKNOWN: 04e0ffe0 <unknown>
51 uqdecd w0, all
52 // CHECK-INST: uqdecd w0
53 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
54 // CHECK-ERROR: instruction requires: sve or sme
55 // CHECK-UNKNOWN: 04e0ffe0 <unknown>
57 uqdecd w0, all, mul #1
58 // CHECK-INST: uqdecd w0
59 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
60 // CHECK-ERROR: instruction requires: sve or sme
61 // CHECK-UNKNOWN: 04e0ffe0 <unknown>
63 uqdecd w0, all, mul #16
64 // CHECK-INST: uqdecd w0, all, mul #16
65 // CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
66 // CHECK-ERROR: instruction requires: sve or sme
67 // CHECK-UNKNOWN: 04efffe0 <unknown>
69 uqdecd w0, pow2
70 // CHECK-INST: uqdecd w0, pow2
71 // CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
72 // CHECK-ERROR: instruction requires: sve or sme
73 // CHECK-UNKNOWN: 04e0fc00 <unknown>
75 uqdecd w0, pow2, mul #16
76 // CHECK-INST: uqdecd w0, pow2, mul #16
77 // CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
78 // CHECK-ERROR: instruction requires: sve or sme
79 // CHECK-UNKNOWN: 04effc00 <unknown>
82 // ---------------------------------------------------------------------------//
83 // Test vector form and aliases.
84 // ---------------------------------------------------------------------------//
85 uqdecd z0.d
86 // CHECK-INST: uqdecd z0.d
87 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
88 // CHECK-ERROR: instruction requires: sve or sme
89 // CHECK-UNKNOWN: 04e0cfe0 <unknown>
91 uqdecd z0.d, all
92 // CHECK-INST: uqdecd z0.d
93 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
94 // CHECK-ERROR: instruction requires: sve or sme
95 // CHECK-UNKNOWN: 04e0cfe0 <unknown>
97 uqdecd z0.d, all, mul #1
98 // CHECK-INST: uqdecd z0.d
99 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
100 // CHECK-ERROR: instruction requires: sve or sme
101 // CHECK-UNKNOWN: 04e0cfe0 <unknown>
103 uqdecd z0.d, all, mul #16
104 // CHECK-INST: uqdecd z0.d, all, mul #16
105 // CHECK-ENCODING: [0xe0,0xcf,0xef,0x04]
106 // CHECK-ERROR: instruction requires: sve or sme
107 // CHECK-UNKNOWN: 04efcfe0 <unknown>
109 uqdecd z0.d, pow2
110 // CHECK-INST: uqdecd z0.d, pow2
111 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
112 // CHECK-ERROR: instruction requires: sve or sme
113 // CHECK-UNKNOWN: 04e0cc00 <unknown>
115 uqdecd z0.d, pow2, mul #16
116 // CHECK-INST: uqdecd z0.d, pow2, mul #16
117 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
118 // CHECK-ERROR: instruction requires: sve or sme
119 // CHECK-UNKNOWN: 04efcc00 <unknown>
122 // ---------------------------------------------------------------------------//
123 // Test all patterns for 64-bit form
124 // ---------------------------------------------------------------------------//
126 uqdecd x0, pow2
127 // CHECK-INST: uqdecd x0, pow2
128 // CHECK-ENCODING: [0x00,0xfc,0xf0,0x04]
129 // CHECK-ERROR: instruction requires: sve or sme
130 // CHECK-UNKNOWN: 04f0fc00 <unknown>
132 uqdecd x0, vl1
133 // CHECK-INST: uqdecd x0, vl1
134 // CHECK-ENCODING: [0x20,0xfc,0xf0,0x04]
135 // CHECK-ERROR: instruction requires: sve or sme
136 // CHECK-UNKNOWN: 04f0fc20 <unknown>
138 uqdecd x0, vl2
139 // CHECK-INST: uqdecd x0, vl2
140 // CHECK-ENCODING: [0x40,0xfc,0xf0,0x04]
141 // CHECK-ERROR: instruction requires: sve or sme
142 // CHECK-UNKNOWN: 04f0fc40 <unknown>
144 uqdecd x0, vl3
145 // CHECK-INST: uqdecd x0, vl3
146 // CHECK-ENCODING: [0x60,0xfc,0xf0,0x04]
147 // CHECK-ERROR: instruction requires: sve or sme
148 // CHECK-UNKNOWN: 04f0fc60 <unknown>
150 uqdecd x0, vl4
151 // CHECK-INST: uqdecd x0, vl4
152 // CHECK-ENCODING: [0x80,0xfc,0xf0,0x04]
153 // CHECK-ERROR: instruction requires: sve or sme
154 // CHECK-UNKNOWN: 04f0fc80 <unknown>
156 uqdecd x0, vl5
157 // CHECK-INST: uqdecd x0, vl5
158 // CHECK-ENCODING: [0xa0,0xfc,0xf0,0x04]
159 // CHECK-ERROR: instruction requires: sve or sme
160 // CHECK-UNKNOWN: 04f0fca0 <unknown>
162 uqdecd x0, vl6
163 // CHECK-INST: uqdecd x0, vl6
164 // CHECK-ENCODING: [0xc0,0xfc,0xf0,0x04]
165 // CHECK-ERROR: instruction requires: sve or sme
166 // CHECK-UNKNOWN: 04f0fcc0 <unknown>
168 uqdecd x0, vl7
169 // CHECK-INST: uqdecd x0, vl7
170 // CHECK-ENCODING: [0xe0,0xfc,0xf0,0x04]
171 // CHECK-ERROR: instruction requires: sve or sme
172 // CHECK-UNKNOWN: 04f0fce0 <unknown>
174 uqdecd x0, vl8
175 // CHECK-INST: uqdecd x0, vl8
176 // CHECK-ENCODING: [0x00,0xfd,0xf0,0x04]
177 // CHECK-ERROR: instruction requires: sve or sme
178 // CHECK-UNKNOWN: 04f0fd00 <unknown>
180 uqdecd x0, vl16
181 // CHECK-INST: uqdecd x0, vl16
182 // CHECK-ENCODING: [0x20,0xfd,0xf0,0x04]
183 // CHECK-ERROR: instruction requires: sve or sme
184 // CHECK-UNKNOWN: 04f0fd20 <unknown>
186 uqdecd x0, vl32
187 // CHECK-INST: uqdecd x0, vl32
188 // CHECK-ENCODING: [0x40,0xfd,0xf0,0x04]
189 // CHECK-ERROR: instruction requires: sve or sme
190 // CHECK-UNKNOWN: 04f0fd40 <unknown>
192 uqdecd x0, vl64
193 // CHECK-INST: uqdecd x0, vl64
194 // CHECK-ENCODING: [0x60,0xfd,0xf0,0x04]
195 // CHECK-ERROR: instruction requires: sve or sme
196 // CHECK-UNKNOWN: 04f0fd60 <unknown>
198 uqdecd x0, vl128
199 // CHECK-INST: uqdecd x0, vl128
200 // CHECK-ENCODING: [0x80,0xfd,0xf0,0x04]
201 // CHECK-ERROR: instruction requires: sve or sme
202 // CHECK-UNKNOWN: 04f0fd80 <unknown>
204 uqdecd x0, vl256
205 // CHECK-INST: uqdecd x0, vl256
206 // CHECK-ENCODING: [0xa0,0xfd,0xf0,0x04]
207 // CHECK-ERROR: instruction requires: sve or sme
208 // CHECK-UNKNOWN: 04f0fda0 <unknown>
210 uqdecd x0, #14
211 // CHECK-INST: uqdecd x0, #14
212 // CHECK-ENCODING: [0xc0,0xfd,0xf0,0x04]
213 // CHECK-ERROR: instruction requires: sve or sme
214 // CHECK-UNKNOWN: 04f0fdc0 <unknown>
216 uqdecd x0, #15
217 // CHECK-INST: uqdecd x0, #15
218 // CHECK-ENCODING: [0xe0,0xfd,0xf0,0x04]
219 // CHECK-ERROR: instruction requires: sve or sme
220 // CHECK-UNKNOWN: 04f0fde0 <unknown>
222 uqdecd x0, #16
223 // CHECK-INST: uqdecd x0, #16
224 // CHECK-ENCODING: [0x00,0xfe,0xf0,0x04]
225 // CHECK-ERROR: instruction requires: sve or sme
226 // CHECK-UNKNOWN: 04f0fe00 <unknown>
228 uqdecd x0, #17
229 // CHECK-INST: uqdecd x0, #17
230 // CHECK-ENCODING: [0x20,0xfe,0xf0,0x04]
231 // CHECK-ERROR: instruction requires: sve or sme
232 // CHECK-UNKNOWN: 04f0fe20 <unknown>
234 uqdecd x0, #18
235 // CHECK-INST: uqdecd x0, #18
236 // CHECK-ENCODING: [0x40,0xfe,0xf0,0x04]
237 // CHECK-ERROR: instruction requires: sve or sme
238 // CHECK-UNKNOWN: 04f0fe40 <unknown>
240 uqdecd x0, #19
241 // CHECK-INST: uqdecd x0, #19
242 // CHECK-ENCODING: [0x60,0xfe,0xf0,0x04]
243 // CHECK-ERROR: instruction requires: sve or sme
244 // CHECK-UNKNOWN: 04f0fe60 <unknown>
246 uqdecd x0, #20
247 // CHECK-INST: uqdecd x0, #20
248 // CHECK-ENCODING: [0x80,0xfe,0xf0,0x04]
249 // CHECK-ERROR: instruction requires: sve or sme
250 // CHECK-UNKNOWN: 04f0fe80 <unknown>
252 uqdecd x0, #21
253 // CHECK-INST: uqdecd x0, #21
254 // CHECK-ENCODING: [0xa0,0xfe,0xf0,0x04]
255 // CHECK-ERROR: instruction requires: sve or sme
256 // CHECK-UNKNOWN: 04f0fea0 <unknown>
258 uqdecd x0, #22
259 // CHECK-INST: uqdecd x0, #22
260 // CHECK-ENCODING: [0xc0,0xfe,0xf0,0x04]
261 // CHECK-ERROR: instruction requires: sve or sme
262 // CHECK-UNKNOWN: 04f0fec0 <unknown>
264 uqdecd x0, #23
265 // CHECK-INST: uqdecd x0, #23
266 // CHECK-ENCODING: [0xe0,0xfe,0xf0,0x04]
267 // CHECK-ERROR: instruction requires: sve or sme
268 // CHECK-UNKNOWN: 04f0fee0 <unknown>
270 uqdecd x0, #24
271 // CHECK-INST: uqdecd x0, #24
272 // CHECK-ENCODING: [0x00,0xff,0xf0,0x04]
273 // CHECK-ERROR: instruction requires: sve or sme
274 // CHECK-UNKNOWN: 04f0ff00 <unknown>
276 uqdecd x0, #25
277 // CHECK-INST: uqdecd x0, #25
278 // CHECK-ENCODING: [0x20,0xff,0xf0,0x04]
279 // CHECK-ERROR: instruction requires: sve or sme
280 // CHECK-UNKNOWN: 04f0ff20 <unknown>
282 uqdecd x0, #26
283 // CHECK-INST: uqdecd x0, #26
284 // CHECK-ENCODING: [0x40,0xff,0xf0,0x04]
285 // CHECK-ERROR: instruction requires: sve or sme
286 // CHECK-UNKNOWN: 04f0ff40 <unknown>
288 uqdecd x0, #27
289 // CHECK-INST: uqdecd x0, #27
290 // CHECK-ENCODING: [0x60,0xff,0xf0,0x04]
291 // CHECK-ERROR: instruction requires: sve or sme
292 // CHECK-UNKNOWN: 04f0ff60 <unknown>
294 uqdecd x0, #28
295 // CHECK-INST: uqdecd x0, #28
296 // CHECK-ENCODING: [0x80,0xff,0xf0,0x04]
297 // CHECK-ERROR: instruction requires: sve or sme
298 // CHECK-UNKNOWN: 04f0ff80 <unknown>
301 // --------------------------------------------------------------------------//
302 // Test compatibility with MOVPRFX instruction.
304 movprfx z0, z7
305 // CHECK-INST: movprfx z0, z7
306 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
307 // CHECK-ERROR: instruction requires: sve or sme
308 // CHECK-UNKNOWN: 0420bce0 <unknown>
310 uqdecd z0.d
311 // CHECK-INST: uqdecd z0.d
312 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
313 // CHECK-ERROR: instruction requires: sve or sme
314 // CHECK-UNKNOWN: 04e0cfe0 <unknown>
316 movprfx z0, z7
317 // CHECK-INST: movprfx z0, z7
318 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
319 // CHECK-ERROR: instruction requires: sve or sme
320 // CHECK-UNKNOWN: 0420bce0 <unknown>
322 uqdecd z0.d, pow2, mul #16
323 // CHECK-INST: uqdecd z0.d, pow2, mul #16
324 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
325 // CHECK-ERROR: instruction requires: sve or sme
326 // CHECK-UNKNOWN: 04efcc00 <unknown>
328 movprfx z0, z7
329 // CHECK-INST: movprfx z0, z7
330 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
331 // CHECK-ERROR: instruction requires: sve or sme
332 // CHECK-UNKNOWN: 0420bce0 <unknown>
334 uqdecd z0.d, pow2
335 // CHECK-INST: uqdecd z0.d, pow2
336 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
337 // CHECK-ERROR: instruction requires: sve or sme
338 // CHECK-UNKNOWN: 04e0cc00 <unknown>