[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / fcvtxnt.s
blobd906146d7ed70f8d0937de55b9c7030b2d64d5d7
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
13 fcvtxnt z0.s, p0/m, z1.d
14 // CHECK-INST: fcvtxnt z0.s, p0/m, z1.d
15 // CHECK-ENCODING: [0x20,0xa0,0x0a,0x64]
16 // CHECK-ERROR: instruction requires: sve2 or sme
17 // CHECK-UNKNOWN: 640aa020 <unknown>
19 fcvtxnt z30.s, p7/m, z31.d
20 // CHECK-INST: fcvtxnt z30.s, p7/m, z31.d
21 // CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64]
22 // CHECK-ERROR: instruction requires: sve2 or sme
23 // CHECK-UNKNOWN: 640abffe <unknown>