[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / sabalb.s
blob15e73d1443c518c5479eb6b123e3d71c55e07492
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
13 sabalb z0.h, z1.b, z31.b
14 // CHECK-INST: sabalb z0.h, z1.b, z31.b
15 // CHECK-ENCODING: [0x20,0xc0,0x5f,0x45]
16 // CHECK-ERROR: instruction requires: sve2 or sme
17 // CHECK-UNKNOWN: 455fc020 <unknown>
19 sabalb z0.s, z1.h, z31.h
20 // CHECK-INST: sabalb z0.s, z1.h, z31.h
21 // CHECK-ENCODING: [0x20,0xc0,0x9f,0x45]
22 // CHECK-ERROR: instruction requires: sve2 or sme
23 // CHECK-UNKNOWN: 459fc020 <unknown>
25 sabalb z0.d, z1.s, z31.s
26 // CHECK-INST: sabalb z0.d, z1.s, z31.s
27 // CHECK-ENCODING: [0x20,0xc0,0xdf,0x45]
28 // CHECK-ERROR: instruction requires: sve2 or sme
29 // CHECK-UNKNOWN: 45dfc020 <unknown>
32 // --------------------------------------------------------------------------//
33 // Test compatibility with MOVPRFX instruction.
35 movprfx z21, z28
36 // CHECK-INST: movprfx z21, z28
37 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
38 // CHECK-ERROR: instruction requires: sve or sme
39 // CHECK-UNKNOWN: 0420bf95 <unknown>
41 sabalb z21.d, z1.s, z31.s
42 // CHECK-INST: sabalb z21.d, z1.s, z31.s
43 // CHECK-ENCODING: [0x35,0xc0,0xdf,0x45]
44 // CHECK-ERROR: instruction requires: sve2 or sme
45 // CHECK-UNKNOWN: 45dfc035 <unknown>